April 2021 - U-Boot

[PATCH v10 0/3] Add support for stack-protector
by Heinrich Schuchardt 20 Apr '21

20 Apr '21

Add support for stack protector for UBOOT, SPL, and TPL as well as new pytest for stackprotector Two preparatory patches are needed. The first one avoids random failures of a unit test. The second cleans up the usage of CFLAGS_NON_EFI. The series was passes Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/7133 v10: Preparatory patches. Fix build errors. Heinrich Schuchardt (2): test: fix test/dm/regmap.c x86: correct usage of CFLAGS_NON_EFI Joel Peshkin (1): Add support for stack-protector MAINTAINERS | 7 +++++++ Makefile | 5 +++++ arch/arm/config.mk | 3 ++- arch/riscv/lib/Makefile | 1 + arch/x86/config.mk | 10 ++++++---- cmd/Kconfig | 9 +++++++++ cmd/Makefile | 1 + cmd/stackprot_test.c | 19 +++++++++++++++++++ common/Kconfig | 17 +++++++++++++++++ common/Makefile | 1 + common/stackprot.c | 20 ++++++++++++++++++++ configs/sandbox_defconfig | 2 ++ scripts/Makefile.spl | 6 ++++++ test/dm/regmap.c | 9 +++++---- test/py/tests/test_stackprotector.py | 14 ++++++++++++++ 15 files changed, 115 insertions(+), 9 deletions(-) create mode 100644 cmd/stackprot_test.c create mode 100644 common/stackprot.c create mode 100644 test/py/tests/test_stackprotector.py -- 2.30.2

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[PATCH] toradex: configblock: fix module revision in config block
by denys.drozdov＠toradex.com 20 Apr '21

20 Apr '21

From: Denys Drozdov <denys.drozdov(a)toradex.com> U-boot might display wrong module revision information for modules with an assembly version 'K'. "cfgblock create" does not takes into account all revision digits from PID8. This fix takes into account all digits of PID8 to store module revision. Signed-off-by: Denys Drozdov <denys.drozdov(a)toradex.com> --- board/toradex/common/tdx-cfg-block.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index adab0a0802..9be58d538b 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -555,6 +555,8 @@ static int get_cfgblock_interactive(void) static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag, u32 *serial) { + char revision[3] = {barcode[6], barcode[7], '\0'}; + if (strlen(barcode) < 16) { printf("Argument too short, barcode is 16 chars long\n"); return -1; @@ -563,7 +565,7 @@ static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag, /* Get hardware information from the first 8 digits */ tag->ver_major = barcode[4] - '0'; tag->ver_minor = barcode[5] - '0'; - tag->ver_assembly = barcode[7] - '0'; + tag->ver_assembly = simple_strtoul(revision, NULL, 10); barcode[4] = '\0'; tag->prodid = simple_strtoul(barcode, NULL, 10); -- 2.17.1

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[PATCH 0/6] highbank: Update to driver model
by Andre Przywara 20 Apr '21

20 Apr '21

The Calxeda Highbank and Midway systems have not been updated in a while, so were gathering more and more warning messages about not being DM compliant over time. To avoid the support being removed, update the board to comply with modern U-Boot standards: - Enable OF_CONTROL, and use the DTB provided by previous firmware stages. - Convert the XGMAC network driver over to the driver model. - Read the actual DRAM size (as detect by the management processor) from the DTB and use that to populate the memory node, and U-Boot internal idea of DRAM. Access to SATA drives broke with commit 66c54f1a3e46 ("scsi: Simplify scsi_read()/_write()") before the v2020.01 release, and remains non-functional with this series for now. Reverting that commit (and massaging it a bit) brought it back to life. I will send a proper patch once I wrapped my head around the SCSI/SATA/AHCI/DM-block connections. To test this build, you can use chain-loading on an existing installation (firmware updates in flash on those boards are not trivial): $ mkimage -A arm -O u-boot -T standalone -C none -a 0x8000 -e 0x8000 \ -d u-boot.bin -n U-Boot /srv/tftp/u-boot-highbank.img => tftpboot 0x8000 u-boot-highbank.img => bootm 0x8000 Cheers, Andre Andre Przywara (6): arm: highbank: Limit FDT and initrd load addresses arm: highbank: Enable OF_CONTROL net: calxedagmac: Convert to DM_ETH arm: highbank: Remove artificial SDRAM size arm: highbank: Do DRAM init from DT arm: highbank: Update maintainership arch/arm/Kconfig | 11 +- board/highbank/MAINTAINERS | 2 +- board/highbank/highbank.c | 32 +++--- configs/highbank_defconfig | 4 +- drivers/net/Kconfig | 7 ++ drivers/net/calxedaxgmac.c | 192 +++++++++++++++++++++++------------ include/configs/highbank.h | 13 +-- include/netdev.h | 1 - scripts/config_whitelist.txt | 1 - 9 files changed, 170 insertions(+), 93 deletions(-) -- 2.17.5

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[PATCH v5 0/2] power: regulator: add driver for ANATOP regulator
by Ying-Chun Liu 20 Apr '21

20 Apr '21

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Anatop is an integrated regulator inside i.MX6 SoC. There are 3 digital regulators which controls PU, CORE (ARM), and SOC. And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB). This patch adds the Anatop regulator driver. Ying-Chun Liu (PaulLiu) (2): power: regulator: add driver for ANATOP regulator doc: device-tree-bindings: regulator: anatop regulator v2: add functions for set selector and delay. Define ANATOP_REGULATOR_STEP v3: add vin-supply. move regmap retrival to probe v4: check control_reg and return -ENOSYS if error. check vin-supply error v5: fix typo "wrie" -> "write" .../regulator/fsl,anatop-regulator.txt | 45 +++ drivers/power/regulator/Kconfig | 10 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/anatop_regulator.c | 278 ++++++++++++++++++ 4 files changed, 334 insertions(+) create mode 100644 doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt create mode 100644 drivers/power/regulator/anatop_regulator.c -- 2.30.2

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[PATCH 1/1] cmd: CONFIG_CMD_MMC depends on CONFIG_MMC
by Heinrich Schuchardt 20 Apr '21

20 Apr '21

Trying to compile with CONFIG_CMD_MMC=y and CONFIG_MMC=n leads to errors: riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmcops': cmd/mmc.c:984: undefined reference to `get_mmc_num' riscv64-linux-gnu-ld.bfd: cmd/built-in.o: in function `do_mmc_setdsr': cmd/mmc.c:873: undefined reference to `find_mmc_device' Add missing dependency. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 0107c0fa3e..3ce223bed0 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1052,6 +1052,7 @@ config CMD_MISC config CMD_MMC bool "mmc" + depends on MMC help MMC memory mapped support. -- 2.29.2

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[PATCH] lz4: Fix unaligned accesses
by karl.beldan＠gmail.com 20 Apr '21

20 Apr '21

From: Karl Beldan <karl.beldan+oss(a)gmail.com> Signed-off-by: Karl Beldan <karl.beldan+oss(a)gmail.com> --- lib/lz4_wrapper.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c index e0f7d3688e..cdbcd05bd4 100644 --- a/lib/lz4_wrapper.c +++ b/lib/lz4_wrapper.c @@ -11,9 +11,18 @@ #include <linux/types.h> #include <asm/unaligned.h> -static u16 LZ4_readLE16(const void *src) { return le16_to_cpu(*(u16 *)src); } -static void LZ4_copy4(void *dst, const void *src) { *(u32 *)dst = *(u32 *)src; } -static void LZ4_copy8(void *dst, const void *src) { *(u64 *)dst = *(u64 *)src; } +static u16 LZ4_readLE16(const void *src) +{ + return get_unaligned_le16(src); +} +static void LZ4_copy4(void *dst, const void *src) +{ + put_unaligned(get_unaligned((const u32 *)src), (u32 *)dst); +} +static void LZ4_copy8(void *dst, const void *src) +{ + put_unaligned(get_unaligned((const u64 *)src), (u64 *)dst); +} typedef uint8_t BYTE; typedef uint16_t U16; -- 2.30.2

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[PATCH] Fix IDE commands issued, fix endian issues, fix non MMIO
by Reinoud Zandijk 20 Apr '21

20 Apr '21

Fixes IDE issues found on the Malta board under Qemu: 1) DMA implied commands were sent to the controller in stead of the PIO variants. The rest of the code is DMA free and written for PIO operation. 2) direct pointer access was used to read and write the registers instead of the inb/inw/outb/outw functions/macros. Registers don't have to be memory mapped and ATA_CURR_BASE() does not have to return an offset from address zero. 3) Endian isues in ide_ident() and reading/writing data in general. Names were corrupted and sizes misreported. Tested malta_defconfig and maltael_defconfig to work again in Qemu. Signed-off-by: Reinoud Zandijk <reinoud(a)NetBSD.org> --- drivers/block/ide.c | 152 +++++++++++++------------------------------- include/ata.h | 2 +- 2 files changed, 44 insertions(+), 110 deletions(-) diff --git a/drivers/block/ide.c b/drivers/block/ide.c index 43a0776099..862a85bc87 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -130,56 +130,38 @@ OUT: * ATAPI Support */ -#if defined(CONFIG_IDE_SWAP_IO) /* since ATAPI may use commands with not 4 bytes alligned length * we have our own transfer functions, 2 bytes alligned */ __weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) { + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; - debug("in output data shorts base for read is %lx\n", - (unsigned long) pbuf); + debug("in output data shorts base for read is %p\n", (void *)paddr); while (shorts--) { EIEIO; - *pbuf = *dbuf++; + outw(cpu_to_le16(*dbuf++), paddr); } } __weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) { + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; - debug("in input data shorts base for read is %lx\n", - (unsigned long) pbuf); + debug("in input data shorts base for read is %p\n", (void *)paddr); while (shorts--) { EIEIO; - *dbuf++ = *pbuf; + *dbuf++ = le16_to_cpu(inw(paddr)); } } -#else /* ! CONFIG_IDE_SWAP_IO */ -__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); -} - -__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); -} - -#endif /* CONFIG_IDE_SWAP_IO */ - /* * Wait until (Status & mask) == res, or timeout (in ms) * Return last status @@ -636,19 +618,6 @@ static void ide_ident(struct blk_desc *dev_desc) sizeof(dev_desc->vendor)); ident_cpy((unsigned char *)dev_desc->product, iop.serial_no, sizeof(dev_desc->product)); -#ifdef __LITTLE_ENDIAN - /* - * firmware revision, model, and serial number have Big Endian Byte - * order in Word. Convert all three to little endian. - * - * See CF+ and CompactFlash Specification Revision 2.0: - * 6.2.1.6: Identify Drive, Table 39 for more details - */ - - strswab(dev_desc->revision); - strswab(dev_desc->vendor); - strswab(dev_desc->product); -#endif /* __LITTLE_ENDIAN */ if ((iop.config & 0x0080) == 0x0080) dev_desc->removable = 1; @@ -662,26 +631,22 @@ static void ide_ident(struct blk_desc *dev_desc) } #endif /* CONFIG_ATAPI */ -#ifdef __BIG_ENDIAN - /* swap shorts */ - dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16); -#else /* ! __BIG_ENDIAN */ - /* - * do not swap shorts on little endian - * - * See CF+ and CompactFlash Specification Revision 2.0: - * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details. - */ - dev_desc->lba = iop.lba_capacity; -#endif /* __BIG_ENDIAN */ + iop.lba_capacity[0] = be16_to_cpu(iop.lba_capacity[0]); + iop.lba_capacity[1] = be16_to_cpu(iop.lba_capacity[1]); + dev_desc->lba = + ((unsigned long)iop.lba_capacity[0]) | + ((unsigned long)iop.lba_capacity[1] << 16); #ifdef CONFIG_LBA48 if (iop.command_set_2 & 0x0400) { /* LBA 48 support */ dev_desc->lba48 = 1; - dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] | - ((unsigned long long) iop.lba48_capacity[1] << 16) | - ((unsigned long long) iop.lba48_capacity[2] << 32) | - ((unsigned long long) iop.lba48_capacity[3] << 48); + for (int i = 0; i < 4; i++) + iop.lba48_capacity[i] = be16_to_cpu(iop.lba48_capacity[i]); + dev_desc->lba = + ((unsigned long long)iop.lba48_capacity[0] | + ((unsigned long long)iop.lba48_capacity[1] << 16) | + ((unsigned long long)iop.lba48_capacity[2] << 32) | + ((unsigned long long)iop.lba48_capacity[3] << 48)); } else { dev_desc->lba48 = 0; } @@ -846,90 +811,59 @@ void ide_init(void) #endif } -/* We only need to swap data if we are running on a big endian cpu. */ -#if defined(__LITTLE_ENDIAN) __weak void ide_input_swap_data(int dev, ulong *sect_buf, int words) { - ide_input_data(dev, sect_buf, words); -} -#else -__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words) -{ - volatile ushort *pbuf = - (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf = (ushort *)sect_buf; - debug("in input swap data base for read is %lx\n", - (unsigned long) pbuf); + debug("in input swap data base for read is %p\n", (void *)paddr); while (words--) { -#ifdef __MIPS__ - *dbuf++ = swab16p((u16 *)pbuf); - *dbuf++ = swab16p((u16 *)pbuf); -#else - *dbuf++ = ld_le16(pbuf); - *dbuf++ = ld_le16(pbuf); -#endif /* !MIPS */ + EIEIO; + *dbuf++ = be16_to_cpu(inw(paddr)); + EIEIO; + *dbuf++ = be16_to_cpu(inw(paddr)); } } -#endif /* __LITTLE_ENDIAN */ - -#if defined(CONFIG_IDE_SWAP_IO) __weak void ide_output_data(int dev, const ulong *sect_buf, int words) { +#if defined(CONFIG_IDE_AHB) + ide_write_data(dev, sect_buf, words); +#else + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; while (words--) { EIEIO; - *pbuf = *dbuf++; + outw(cpu_to_le16(*dbuf++), paddr); EIEIO; - *pbuf = *dbuf++; + outw(cpu_to_le16(*dbuf++), paddr); } +#endif /* CONFIG_IDE_AHB */ } -#else /* ! CONFIG_IDE_SWAP_IO */ -__weak void ide_output_data(int dev, const ulong *sect_buf, int words) -{ -#if defined(CONFIG_IDE_AHB) - ide_write_data(dev, sect_buf, words); -#else - outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1); -#endif -} -#endif /* CONFIG_IDE_SWAP_IO */ -#if defined(CONFIG_IDE_SWAP_IO) __weak void ide_input_data(int dev, ulong *sect_buf, int words) { +#if defined(CONFIG_IDE_AHB) + ide_read_data(dev, sect_buf, words); +#else + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; - debug("in input data base for read is %lx\n", (unsigned long) pbuf); + debug("in input data base for read is %p\n", (void *)paddr); while (words--) { EIEIO; - *dbuf++ = *pbuf; + *dbuf++ = le16_to_cpu(inw(paddr)); EIEIO; - *dbuf++ = *pbuf; + *dbuf++ = le16_to_cpu(inw(paddr)); } +#endif /* CONFIG_IDE_AHB */ } -#else /* ! CONFIG_IDE_SWAP_IO */ -__weak void ide_input_data(int dev, ulong *sect_buf, int words) -{ -#if defined(CONFIG_IDE_AHB) - ide_read_data(dev, sect_buf, words); -#else - insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1); -#endif -} - -#endif /* CONFIG_IDE_SWAP_IO */ #ifdef CONFIG_BLK ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, @@ -1019,14 +953,14 @@ ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, if (lba48) { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); - ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ_EXT); } else #endif { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) | ((blknr >> 24) & 0xF)); - ide_outb(device, ATA_COMMAND, ATA_CMD_READ); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ); } udelay(50); @@ -1116,14 +1050,14 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, if (lba48) { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); - ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE_EXT); } else #endif { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) | ((blknr >> 24) & 0xF)); - ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE); } udelay(50); diff --git a/include/ata.h b/include/ata.h index 3d870c973f..32ad5f6427 100644 --- a/include/ata.h +++ b/include/ata.h @@ -134,7 +134,7 @@ typedef struct hd_driveid { unsigned short cur_capacity1; /* (2 words, misaligned int) */ unsigned char multsect; /* current multiple sector count */ unsigned char multsect_valid; /* when (bit0==1) multsect is ok */ - unsigned int lba_capacity; /* total number of sectors */ + unsigned short lba_capacity[2];/* two words containing total number of sectors */ unsigned short dma_1word; /* single-word dma info */ unsigned short dma_mword; /* multiple-word dma info */ unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */ -- 2.29.2

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[PATCH v2 1/4] misc: make CONFIG_IRQ selectable for all platforms
by Wasim Khan 20 Apr '21

20 Apr '21

From: Wasim Khan <wasim.khan(a)nxp.com> UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ selectable for all platforms. Signed-off-by: Wasim Khan <wasim.khan(a)nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean(a)nxp.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Corrected typo in commit description drivers/misc/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 29432ae7eb..5eab1ed9c6 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -211,10 +211,9 @@ config FSL_SEC_MON like software violations or hardware security violations. config IRQ - bool "Intel Interrupt controller" - depends on X86 || SANDBOX + bool "Interrupt controller" help - This enables support for Intel interrupt controllers, including ITSS. + This enables support for interrupt controllers, including ITSS. Some devices have extra features, such as Apollo Lake. The device has its own uclass since there are several operations involved. -- 2.25.1

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[PATCHv3] arm64: gic-v3-its: Clear the Pending table before enabling LPIs
by Zhiqiang Hou 20 Apr '21

20 Apr '21

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must contain only zeros on initial allocation, and this must be visible to the Redistributors, or else the effect is UNPREDICTABLE". And as the following statement, we here clear the whole Pending tables instead of the first 1KB. "An LPI Pending table that contains only zeros, including in the first 1KB, indicates that there are no pending LPIs. The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However, if the first 1KB of the LPI Pending table and the rest of the table contain only zeros, this must indicate that there are no pending LPIs." And there isn't any pending LPI under U-Boot, so it's unnecessary to load the contents of the Pending table during the enablement, then set the GICR_PENDBASER.PTZ flag. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- V3: - Fix a mistake code delete in v2. arch/arm/lib/gic-v3-its.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index f5a921b3d1..2d3fdb600e 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -3,6 +3,7 @@ * Copyright 2019 Broadcom. */ #include <common.h> +#include <cpu_func.h> #include <dm.h> #include <regmap.h> #include <syscon.h> @@ -108,6 +109,8 @@ int gic_lpi_tables_init(void) int i; u64 redist_lpi_base; u64 pend_base; + ulong pend_tab_total_sz; + void *pend_tab_va; if (gic_v3_its_get_gic_addr(&priv)) return -EINVAL; @@ -161,6 +164,12 @@ int gic_lpi_tables_init(void) } redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ; + pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ; + pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz, + MAP_NOCACHE); + memset(pend_tab_va, 0, pend_tab_total_sz); + flush_cache((ulong)pend_tab_va, pend_tab_total_sz); + unmap_physmem(pend_tab_va, MAP_NOCACHE); pend_base = priv.gicr_base + GICR_PENDBASER; for (i = 0; i < priv.num_redist; i++) { @@ -168,7 +177,8 @@ int gic_lpi_tables_init(void) val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) | GICR_PENDBASER_INNERSHAREABLE | - GICR_PENDBASER_RAWAWB); + GICR_PENDBASER_RAWAWB | + GICR_PENDBASER_PTZ); writeq(val, (uintptr_t)(pend_base + offset)); tmp = readq((uintptr_t)(pend_base + offset)); -- 2.17.1

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[PULL u-boot] Please pull u-boot-amlogic-20210419
by Neil Armstrong 20 Apr '21

20 Apr '21

Hi Tom, This serie fixes Ethernet on Odroid-C2 and enables support for PCIe on the Khadas VIM3 & VIM3L with all the necessary bits after Bin merged the PCIe driver. The CI job is at https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/7216 Thanks, Neil The following changes since commit 3a9aaefcaa3efc2a1cef86fbe0bf229a1bff9902: Merge tag 'efi-2021-07-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2021-04-18 08:47:27 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-20210419 for you to fetch changes up to fcf3c9deae1acfda81051c8c211fcbefd4217e1d: boards: amlogic: update documentation for PCIe support (2021-04-19 16:59:33 +0200) ---------------------------------------------------------------- - fix Ethernet on Odroid-C2 by re-adding old bindings style PHY reset - add G12A PCIe clock gates - add G12A PCIe PHY OPs - enable PCIe for Khadas VIM3/VIM3L boards DT - enable PCIe and NVME for Khadas VIM3/VIM3L boards config - update Amlogic board documentation for PCIe support ---------------------------------------------------------------- Neil Armstrong (6): clk: meson-g12a: add PCIe gates phy: meson-g12a-usb3-pcie: add support for PCIe ops arm: dts: meson-khadas-vim3: enable PCIe in U-boot configs: khadas-vim3: enable PCIe and NVMe configs: meson64: add NVME boot target boards: amlogic: update documentation for PCIe support Stefan Agner (1): arm64: dts: meson: odroidc2: readd PHY reset properties arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 6 +++ arch/arm/dts/meson-khadas-vim3-u-boot.dtsi | 4 ++ configs/khadas-vim3_defconfig | 5 ++ configs/khadas-vim3l_defconfig | 5 ++ doc/board/amlogic/index.rst | 2 + drivers/clk/meson/g12a.c | 2 + drivers/phy/meson-g12a-usb3-pcie.c | 81 ++++++++++++++++++++++++++-- include/configs/meson64.h | 7 +++ 8 files changed, 108 insertions(+), 4 deletions(-)

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