April 2021 - U-Boot

[PATCH] arm: mach-imx: Fix speculative instruction prefetch issue
by Ye Li 02 May '21

02 May '21

Default ARM32 MMU setting in u-boot sets XN bit to entire 4GB space no matter which DCACHE option is used, and set domain permission to manager. This causes MMU ignores the access check and XN bit, so speculative instruction can fetch from entire space. This patch sets the DDR, ROM, OCRAM without XN bit, and set domain to client to enable the XN and access check. So speculative instruction fetch can only happens on these 3 regions to avoid prefetch from peripherals and invalid regions. Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/mach-imx/cache.c | 49 ++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index 4e3b49a..8486c2d 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -10,6 +10,10 @@ #include <asm/pl310.h> #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> +#include <asm/global_data.h> +#include <log.h> + +DECLARE_GLOBAL_DATA_PTR; static void enable_ca7_smp(void) { @@ -40,13 +44,13 @@ static void enable_ca7_smp(void) } #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) + +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) +#define IMX_ARMV7_DCACHE_OPTION (DCACHE_DEFAULT_OPTION & ~TTB_SECT_XN_MASK) + void enable_caches(void) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - enum dcache_option option = DCACHE_WRITETHROUGH; -#else - enum dcache_option option = DCACHE_WRITEBACK; -#endif /* Avoid random hang when download by usb */ invalidate_dcache_all(); @@ -59,11 +63,42 @@ void enable_caches(void) /* Enable caching on OCRAM and ROM */ mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, ROMCP_ARB_END_ADDR, - option); + IMX_ARMV7_DCACHE_OPTION); mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, - option); + IMX_ARMV7_DCACHE_OPTION); +} + +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + int i; + + /* bd->bi_dram is available only after relocation */ + if ((gd->flags & GD_FLG_RELOC) == 0) + return; + + debug("%s: bank: %d\n", __func__, bank); + for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); + i++) + set_section_dcache(i, IMX_ARMV7_DCACHE_OPTION); } + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set domain to client to do access and XN check + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} + #else void enable_caches(void) { -- 2.7.4

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[PATCH v4 00/12] Add support for pinmux status command on beaglebone
by Dario Binacchi 02 May '21

02 May '21

The series was born from the need to check the pinmux setting of a peripheral on a beaglebone board. I then ran the 'pinmux status -a' command but it failed because some operations (get_pin_muxing, get_pin_name and get_pins_count) were missing in the 'pinctrl-single' driver. The patch series can be cleanly applied to the HEAD of the master which at the time of release points to 3f2e3c7845 ("Merge tag 'u-boot-stm32-20210409' of https://source.denx.de/u-boot/custodians/u-boot-stm") Changes in v4: - Added CONFIG_PINCTRL_SINGLE to sandbox_flattree_defconfig to fix sandbox_flattree test errors. Changes in v3: - Added Pratyush Yadav review tag. - Updated commit message. - Added Pratyush Yadav review tag. - Added Pratyush Yadav review tag. - Added Simon Glass review tag. - Added Simon Glass review tag. - Added Simon Glass review tag. Changes in v2: - Added Simon Glass review tag. - Updated commit message. - Added Simon Glass review tag. - Added Pratyush Yadav review tag. - Updated commit message - Split in 2 commits - Check dev_read_addr_size return value. - Updated commit message. - Added Simon Glass review tag. - Updated commit message. - Remove pointer to access functions. - Added Simon Glass review tag. - Added Simon Glass review tag. - Added Simon Glass review tag. - Added error checking when the 'width' property is missing. - Fix coding style. Dario Binacchi (12): pinctrl: single: fix format of structure documentation pinctrl: single: fix the loop counter variable type pinctrl: single: fix offset management pinctrl: single: fix debug messages formatting pinctrl: single: get register area size by device API pinctrl: single: check "register-width" DT property pinctrl: single: change function mask default value pinctrl: single: add register access functions pinctrl: single: add get_pins_count operation pinctrl: single: add get_pin_name operation pinctrl: single: add get_pin_muxing operation test: pinmux: add test for 'pinctrl-single' driver arch/sandbox/dts/test.dts | 72 +++++ configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + drivers/pinctrl/pinctrl-single.c | 474 +++++++++++++++++++++++++---- test/dm/pinmux.c | 91 +++++- 5 files changed, 574 insertions(+), 65 deletions(-) -- 2.17.1

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32-bit DMA limit for devices (and drivers)
by Andre Przywara 02 May '21

02 May '21

Hi, We now see the first Allwinner devices [1] having DRAM located above 4GB in address space (4GB DRAM starting at 1GB). After one fix[2] this works somewhat fine, but the sun8i-emac network device is still limited to 32-bit DMA addresses. With U-Boot relocating itself (plus stack and heap) to the end of DRAM, it now runs completely beyond 4GB on those machines, so not giving pure 32-bit addresses for buffers anymore. In Linux we handle this easily by just keeping the default DMA mask at 32 bits, and letting the DMA framework deal with the nasty details. I was wondering how this should be handled in U-Boot? The straight forward solution would be: - Let the driver allocate the RX and TX buffers separately, placing them below 4GB in the address space (using lmb_reserve(), I guess?) - Use those RX buffers and hand the addresses back to the upper layers. - We already copy TX packets, so this would also be covered, in this situation. Other drivers might need to introduce copying. This sounds like a common problem, so I was wondering if there is a more generic solution to this? Maybe there are already platforms or devices affected? Or should the whole heap and stack be moved below 4GB (if this is easily possible)? In our case we make the buffers part of our priv struct, so should there be an option to let the priv_auto allocation come from below 4GB? Grateful for any input on this! Thanks! Andre [1] https://linux-sunxi.org/X96_Mate [2] https://lists.denx.de/pipermail/u-boot/2021-April/448327.html

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sunxi_nand_spl reading zeros on NextThing C.H.I.P.
by Yevhenii Hrabliuk 02 May '21

02 May '21

Hello, I'm trying to get latest U-Boot to work on the NextThing C.H.I.P. After borrowing NFC config from the Chip Pro .dts, I can write the SPL to NAND after loading U-Boot via sunxi-fel and the bootrom will pick it up fine. So the "full" sunxi_nand.c works. SPL's sunxi_nand_spl.c appears to read all zeros however - I checked by adding prints in spl.c/jump_to_image_no_args(). Can someone please suggest possible things to try to make it work? I tried tinkering with the settings but I have no idea if that's even the issue. The NAND is a Toshiba "TC58TEG5DCLTA00"; NTC's settings for it are presumably [1] and sunxi_nand_spl.c autodetects the following settings: page_size:16384 ecc_strength:4 ecc_size:1024 addr_cycles:5 nseeds:8 randomize:0 Thanks. [1]: https://raw.githubusercontent.com/nextthingco/chip-nand-scripts/master/nand…

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[RFC PATCH v7 0/2] riscv: cpu: Add callback to init each core
by Green Wan 01 May '21

01 May '21

Add a callback interface, harts_early_init() to perform proprietary or customized CRSs configuration for each hart. harts_early_init() is placed after stack of harts are initialized and before main boot hart is picked up. Several conditions should be aware of or avoided are listed: - cannot access gd At the moment, gd hasn't initialized yet. - all operations in harts_early_init() should only affect core itself For example, the operations for board level should be moved to mach_xxx() or board_init_xxx() functions instead. - Common resource need protection if multicore Since all harts might enter harts_early_init() in parallel, common resource need a mechanism to handle race condition. - A reference implementation is added in ./arch/riscv/cpu/cpu.c The implementation is declared with '__weak' and can be overridden. Changelogs: v7 - remove M-mode check in [v6 1/2] - remove 'arch' from title of patch - add Reviewed-by v6 - revised the description in both of commit message and comment [1/2] - moved the implementation of harts_early_init() in [2/2] from board/sifive/unmatched/spl.c to arch/riscv/cpu/fu740/spl.c. and revised commit message v5 - rename riscv_hart_early_init to harts_early_init - rephrase dummy for harts_early_init() to callback but keep current comments not specific for customizing CSRs only. - Fix nit in [2/2] and add reviewed-by v4 - Revising the comments for riscv_hart_early_init() in [1/2] - Remove unnecessary braces and add reviewed-by in [2/2] Green Wan (2): riscv: cpu: Add callback to init each core riscv: cpu: fu740: clear feature disable CSR arch/riscv/cpu/cpu.c | 11 +++++++++++ arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++ arch/riscv/cpu/start.S | 6 ++++++ 3 files changed, 32 insertions(+) -- 2.31.0

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[PATCH] ARM: stm32: Add additional ID register check for KSZ8851 presence
by Marek Vasut 30 Apr '21

30 Apr '21

Currently the code sets eth1addr only if /ethernet1 alias exists in DT, the node pointed to by the alias has "micrel,ks8851-mll" compatible string, and the KSZ8851 CCR register read indicates programmed EEPROM is not connected. This is not sufficient to detect cases where the DT still contains the KSZ8851 nodes, but the chip itself is not present. Extend the detection to handle these cases. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)st.com> Cc: Patrick Delaunay <patrick.delaunay(a)st.com> --- board/dhelectronics/dh_stm32mp1/board.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 49b12c4c042..ac1af718d4a 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -86,6 +86,8 @@ DECLARE_GLOBAL_DATA_PTR; #define KS_CCR_EEPROM BIT(9) #define KS_BE0 BIT(12) #define KS_BE1 BIT(13) +#define KS_CIDER 0xC0 +#define CIDER_ID 0x8870 int setup_mac_address(void) { @@ -123,11 +125,18 @@ int setup_mac_address(void) * is present. If EEPROM is present, it must contain valid * MAC address. */ - u32 reg, ccr; + u32 reg, cider, ccr; reg = fdt_get_base_address(gd->fdt_blob, off); if (!reg) goto out_set_ethaddr; + writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2); + cider = readw(reg); + if ((cider & 0xfff0) != CIDER_ID) { + skip_eth1 = true; + goto out_set_ethaddr; + } + writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2); ccr = readw(reg); if (ccr & KS_CCR_EEPROM) { -- 2.30.2

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[PATCH] ARM: stm32: Enable UNZIP on DHSOM by default
by Marek Vasut 30 Apr '21

30 Apr '21

The CMD_UNZIP provides the 'gzwrite' command, which is convenient for writing e.g. gz-compressed images to eMMC from U-Boot. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)st.com> Cc: Patrick Delaunay <patrick.delaunay(a)st.com> --- configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index e36d34d001e..df702547081 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -36,6 +36,7 @@ CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_UNZIP=y CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 4794b1a14d5..4508d4158af 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_UNZIP=y CONFIG_CMD_ADC=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y -- 2.30.2

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[PATCH v3, 1/2] driver: watchdog: reset watchdog in designware_wdt_stop() function
by Meng.Li＠windriver.com 30 Apr '21

30 Apr '21

From: MengLi <meng.li(a)windriver.com> In uboot command line environment, watchdog is not able to be stopped with below commands: SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200 SOCFPGA_STRATIX10 # wdt stop Refer to watchdog driver in linux kernel, it is also need to reset watchdog after disable it so that the disable action takes effect. Signed-off-by: Meng Li <Meng.Li(a)windriver.com> Reviewed-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Sean Anderson <sean.anderson(a)seco.com> --- v3: Add the resets to designware_wdt_priv and initialize it in probe(). v2: Change "#if CONFIG_IS_ENABLED(DM_RESET)" into "if (CONFIG_IS_ENABLED(DM_RESET)) {", and define the variable into if condition sentence. --- drivers/watchdog/designware_wdt.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index 12f09a7a39..cdf6b5709b 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -23,6 +23,7 @@ struct designware_wdt_priv { void __iomem *base; unsigned int clk_khz; + struct reset_ctl_bulk *resets; }; /* @@ -96,6 +97,18 @@ static int designware_wdt_stop(struct udevice *dev) designware_wdt_reset(dev); writel(0, priv->base + DW_WDT_CR); + if (CONFIG_IS_ENABLED(DM_RESET)) { + int ret; + + ret = reset_assert_bulk(priv->resets); + if (ret) + return ret; + + ret = reset_deassert_bulk(priv->resets); + if (ret) + return ret; + } + return 0; } @@ -137,17 +150,15 @@ static int designware_wdt_probe(struct udevice *dev) priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ; #endif -#if CONFIG_IS_ENABLED(DM_RESET) - struct reset_ctl_bulk resets; + if (CONFIG_IS_ENABLED(DM_RESET)) { + ret = reset_get_bulk(dev, priv->resets); + if (ret) + return ret; - ret = reset_get_bulk(dev, &resets); - if (ret) - return ret; - - ret = reset_deassert_bulk(&resets); - if (ret) - return ret; -#endif + ret = reset_deassert_bulk(priv->resets); + if (ret) + return ret; + } /* reset to disable the watchdog */ return designware_wdt_stop(dev); -- 2.17.1

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[PATCH] pcie: designware: mvebu: do not configure ATU for IO when not used
by Stefan Roese 30 Apr '21

30 Apr '21

From: Marcin Wojtas <mw(a)semihalf.com> The pcie_dw_mvebu configure ATU regions for memory, configuration and IO space types. However the latter is not obligatory and when not specified in the device tree, causes wrong ATU configuration. Fix that by adding a dependency on the detected PCIE regions count. Signed-off-by: Marcin Wojtas <mw(a)semihalf.com> Reviewed-on: https://sj1git1.cavium.com/18136 Reviewed-by: Kostya Porotchkin <kostap(a)marvell.com> Tested-by: Kostya Porotchkin <kostap(a)marvell.com> --- drivers/pci/pcie_dw_mvebu.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 93e57cf0cf14..0490fd337705 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -115,6 +115,7 @@ struct pcie_dw_mvebu { int first_busno; /* IO and MEM PCI regions */ + int region_count; struct pci_region io; struct pci_region mem; }; @@ -267,9 +268,10 @@ static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf, debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); *valuep = pci_conv_32_to_size(value, offset, size); - pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_IO, pcie->io.phys_start, - pcie->io.bus_start, pcie->io.size); + if (pcie->region_count > 1) + pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_IO, pcie->io.phys_start, + pcie->io.bus_start, pcie->io.size); return 0; } @@ -312,9 +314,10 @@ static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf, value = pci_conv_size_to_32(old, value, offset, size); writel(value, va_address); - pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_IO, pcie->io.phys_start, - pcie->io.bus_start, pcie->io.size); + if (pcie->region_count > 1) + pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_IO, pcie->io.phys_start, + pcie->io.bus_start, pcie->io.size); return 0; } @@ -513,14 +516,24 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) hose->first_busno); } + pcie->region_count = hose->region_count - CONFIG_NR_DRAM_BANKS; + /* Store the IO and MEM windows settings for future use by the ATU */ - pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */ - pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ - pcie->io.size = hose->regions[0].size; /* IO size */ + if (pcie->region_count > 1) { + /* IO base */ + pcie->io.phys_start = hose->regions[0].phys_start; + /* IO_bus_addr */ + pcie->io.bus_start = hose->regions[0].bus_start; + /* IO size */ + pcie->io.size = hose->regions[0].size; + } - pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ - pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ - pcie->mem.size = hose->regions[1].size; /* MEM size */ + /* MEM base */ + pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start; + /* MEM_bus_addr */ + pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start; + /* MEM size */ + pcie->mem.size = hose->regions[pcie->region_count - 1].size; pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_MEM, pcie->mem.phys_start, -- 2.31.1

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[PATCH v1 0/4] arm64: mvebu: Sync Marvell armada8k MMU setup with Marvell version
by Stefan Roese 30 Apr '21

30 Apr '21

This patchset adds some Armada8k MMU setup related patches from the Marvell SDK. This is needed to resolve some PCI related issues that I exprienced while porting mainline U-Boot to the CN9132 DB board. Thanks, Stefan Grzegorz Jaszczyk (3): arm64: mvebu: do not map firmware RT service region arm64: mvebu: a8k: move firmware related definitions to fw info arm64: mvebu: extend the mmio region jinghua (1): arm64: mvebu: a8k: align memory regions arch/arm/mach-mvebu/armada8k/cpu.c | 70 +++++----------------- arch/arm/mach-mvebu/include/mach/fw_info.h | 18 ++++++ 2 files changed, 34 insertions(+), 54 deletions(-) create mode 100644 arch/arm/mach-mvebu/include/mach/fw_info.h -- 2.31.1

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