March 2021 - U-Boot

[PATCH 1/3] riscv: mpfs-icicle-kit: Increase SYS_MALLOC_F_LEN
by Bin Meng 06 Apr '21

06 Apr '21

The RISC-V architecture default value of CONFIG_SYS_MALLOC_F_LEN (0x1000) would not provide enough memory for devices like mpfs clock and ns16550 serial to bind well before relocation. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- configs/microchip_mpfs_icicle_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 0c15c3bd38..1cb29201b4 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -1,4 +1,5 @@ CONFIG_RISCV=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit" CONFIG_TARGET_MICROCHIP_ICICLE=y -- 2.25.1

2 6

[RFC PATCH v4 0/2] arch: riscv: cpu: Add callback to init each core
by Green Wan 06 Apr '21

06 Apr '21

Add a callback interface, riscv_hart_early_init() to perform riscv CPU hart-dependent configuration for each hart. riscv_hart_early_init() is placed after stack of harts are initialized and before main boot hart is picked up. Several conditions should be aware of or avoided are listed: - cannot access gd At the moment, gd hasn't initialized yet. - all operations in riscv_hart_early_init() should only affect core itself For example, the operations for board level should be moved to mach_xxx() or board_init_xxx() functions instead. - Common resource need protection if multicore Since all harts might enter riscv_hart_early_init() in parallel, common resource need a mechanism to handle race condition. - A dummy implementation is added in ./arch/riscv/cpu/cpu.c The implementation is declared with '__weak' and can be overridden. Changelogs: v4 - Revising the comments for riscv_hart_early_init() in [1/2] - Remove unnecessary braces and add reviewed-by in [2/2] Green Wan (2): arch: riscv: cpu: Add callback to init each core board: sifive: unmatched: clear feature disable CSR arch/riscv/cpu/cpu.c | 15 +++++++++++++++ arch/riscv/cpu/start.S | 14 ++++++++++++++ board/sifive/unmatched/spl.c | 15 +++++++++++++++ 3 files changed, 44 insertions(+) -- 2.31.0

3 6

[PATCH 1/1] patch for OpenPiton SoC of RISC-V Architecture
by Tianrui Wei 06 Apr '21

06 Apr '21

This patch enables u-boot support for Openpiton SoC of RISC-V architecture Signed-off-by: Tianrui Wei <tianrui-wei(a)outlook.com> Acked-by: Jonathan Balkind <jbalkind(a)ucsb.edu> --- arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/openpiton-riscv64.dts | 149 +++++++++++++++++++ board/openpiton/riscv/Kconfig | 42 ++++++ board/openpiton/riscv/MAINTAINERS | 6 + board/openpiton/riscv/Makefile | 5 + board/openpiton/riscv/openpiton-riscv.c | 39 +++++ configs/openpiton_riscv64_defconfig | 132 +++++++++++++++++ drivers/mmc/Kconfig | 6 + drivers/mmc/Makefile | 1 + drivers/mmc/piton_mmc.c | 182 ++++++++++++++++++++++++ include/configs/openpiton-riscv.h | 58 ++++++++ 12 files changed, 625 insertions(+) create mode 100644 arch/riscv/dts/openpiton-riscv64.dts create mode 100644 board/openpiton/riscv/Kconfig create mode 100644 board/openpiton/riscv/MAINTAINERS create mode 100644 board/openpiton/riscv/Makefile create mode 100644 board/openpiton/riscv/openpiton-riscv.c create mode 100644 configs/openpiton_riscv64_defconfig create mode 100644 drivers/mmc/piton_mmc.c create mode 100644 include/configs/openpiton-riscv.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 30b05408..79f2b0b9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,6 +23,9 @@ config TARGET_SIFIVE_FU540 config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" +config TARGET_OPENPITON_RISCV + bool "Support RISC-V cores on OpenPiton SoC" + endchoice config SYS_ICACHE_OFF @@ -57,6 +60,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/openpiton/riscv/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 3a6f96c6..0eb8014b 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb +dtb-$(CONFIG_TARGET_OPENPITON_RISCV) += openpiton-riscv64.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/openpiton-riscv64.dts b/arch/riscv/dts/openpiton-riscv64.dts new file mode 100644 index 00000000..91c000c3 --- /dev/null +++ b/arch/riscv/dts/openpiton-riscv64.dts @@ -0,0 +1,149 @@ +// This dts is for a dual core instance of OpenPiton+Ariane built +// to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files +// are automatically generated by the OpenPiton build system and +// this configuration may not be what you need if your configuration +// is different from the below. + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + compatible = "openpiton,ariane"; + + chosen { + u-boot,dm-pre-reloc; + bootargs = "debug loglevel=9"; + stdout-path = "uart0:115200"; + }; + + aliases { + u-boot,dm-pre-reloc; + console = &uart0; + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + timebase-frequency = <520835>; + + CPU0: cpu@0 { + clock-frequency = <66667000>; + u-boot,dm-pre-reloc; + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU1: cpu@1 { + clock-frequency = <66667000>; + u-boot,dm-pre-reloc; + device_type = "cpu"; + reg = <1>; + status = "okay"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + }; + + memory@80000000 { + u-boot,dm-pre-reloc; + device_type = "memory"; + reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >; + }; + + uart0: uart@fff0c2c000 { + u-boot,dm-pre-reloc; + compatible = "ns16550"; + reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >; + clock-frequency = <66667000>; + current-speed = <115200>; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <0>; // regs are spaced on 8 bit boundary (modified from Xilinx UART16550 to be ns16550 compatible) + }; + + eth: ethernet@fff0d00000 { + compatible = "xlnx,xps-ethernetlite-1.00.a"; + device_type = "network"; + reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >; + interrupt-parent = <&PLIC0>; + interrupts = <2>; + local-mac-address = [ 00 18 3E 02 E3 E5 ]; + phy-handle = <&phy0>; + xlnx,duplex = <0x1>; + xlnx,include-global-buffers = <0x1>; + xlnx,include-internal-loopback = <0x0>; + xlnx,include-mdio = <0x1>; + xlnx,rx-ping-pong = <0x1>; + xlnx,s-axi-id-width = <0x1>; + xlnx,tx-ping-pong = <0x1>; + xlnx,use-internal = <0x0>; + axi_ethernetlite_0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + compatible = "ethernet-phy-id001C.C915"; + device_type = "ethernet-phy"; + reg = <1>; + }; + }; + }; + + debug-controller@fff1000000 { + compatible = "riscv,debug-013"; + interrupts-extended = <&CPU0_intc 65535 &CPU1_intc 65535 >; + reg = < 0x000000ff 0xf1000000 0x00000000 0x00001000 >; + reg-names = "control"; + }; + + sdhci_0: sdhci@0xf000000000 { + u-boot,dm-pre-reloc; + status = "okay"; + compatible = "openpiton,piton-mmc"; + reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >; + }; + clint@fff1020000 { + u-boot,dm-pre-reloc; + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 &CPU1_intc 3 &CPU1_intc 7 >; + reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >; + reg-names = "control"; + }; + + PLIC0: plic@fff1100000 { + u-boot,dm-pre-reloc; + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 >; + reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >; + riscv,max-priority = <7>; + riscv,ndev = <2>; + }; + +}; + diff --git a/board/openpiton/riscv/Kconfig b/board/openpiton/riscv/Kconfig new file mode 100644 index 00000000..31ae44d5 --- /dev/null +++ b/board/openpiton/riscv/Kconfig @@ -0,0 +1,42 @@ +if TARGET_OPENPITON_RISCV + +config SYS_BOARD + default "riscv" + +config SYS_VENDOR + default "openpiton" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "openpiton-riscv" + +config SYS_TEXT_BASE + default 0x81000000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x81000000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x80000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x81000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_EARLY_INIT_R + select SUPPORT_SPL + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT + imply SPL_SMP + imply SPL_MMC + imply SMP + imply SPL_RISCV_MMODE + +endif diff --git a/board/openpiton/riscv/MAINTAINERS b/board/openpiton/riscv/MAINTAINERS new file mode 100644 index 00000000..1db6fb60 --- /dev/null +++ b/board/openpiton/riscv/MAINTAINERS @@ -0,0 +1,6 @@ +Openpiton Riscv Bootloader +M: Tianrui Wei<tianrui-wei(a)outlook.com> +S: Maintained +F: board/openpiton/riscv/ +F: include/configs/openpiton-riscv.h +F: configs/openpiton_riscv_defconfig diff --git a/board/openpiton/riscv/Makefile b/board/openpiton/riscv/Makefile new file mode 100644 index 00000000..8cc20e7c --- /dev/null +++ b/board/openpiton/riscv/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Tianrui Wei +# Tianrui Wei <tianrui-wei(a)outlook.com> +obj-y += openpiton-riscv.o diff --git a/board/openpiton/riscv/openpiton-riscv.c b/board/openpiton/riscv/openpiton-riscv.c new file mode 100644 index 00000000..7cc621bc --- /dev/null +++ b/board/openpiton/riscv/openpiton-riscv.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * Copyright (c) 2021 Tianrui Wei + * + * + * Authors: + * Pragnesh Patel <pragnesh.patel(a)sifive.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ +#include <common.h> +#include <init.h> +#include <configs/openpiton-riscv.h> +#include <dm.h> +#include <spl.h> + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) { + u8 i; + u32 boot_devices[] = { + BOOT_DEVICE_MMC1, + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) { + /* boot using first FIT config */ + return 0; +} +#endif + +int board_init() +{ + return 0; +} diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig new file mode 100644 index 00000000..37aa3c80 --- /dev/null +++ b/configs/openpiton_riscv64_defconfig @@ -0,0 +1,132 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" +CONFIG_TARGET_OPENPITON_RISCV=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_MISC_INIT_R=n +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_PAYLOAD="" +CONFIG_LIBDISK_SUPPORT=y +CONFIG_NR_CPUS=32 +CONFIG_CMODEL_MEDANY=y +CONFIG_EXPORT=n +CONFIG_HASH=n +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_BANNER_PRINT=n +CONFIG_SPL_CRC32_SUPPORT=n +CONFIG_GENERATE_SMBIOS_TABLE=n +CONFIG_EFI_LOADER=n +CONFIG_LIB_DATA=y +CONFIG_SPL_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_FS_EXT4=y +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_SPL_OPENSBI=n +CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=n +CONFIG_CMD_NET=n +CONFIG_EFI_PARTITION=y +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=128 +CONFIG_EFI_PARTITION_ENTRIES_OFF=0 +CONFIG_SPL_EFI_PARTITION=y +CONFIG_PARTITION_UUIDS=y +CONFIG_OF_EMBED=y +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CPU=y +CONFIG_CPU_RISCV=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_MMC_PITON=y +CONFIG_MMC_QUIRKS=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y +CONFIG_DEBUG_UART_SHIFT=0 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_DEBUG_UART_BASE=0xfff0c2c000 +CONFIG_DEBUG_UART_CLOCK=66667000 +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_MMC_VERBOSE=n +CONFIG_MMC_WRITE=n +CONFIG_MMC_HW_PARTITIONING=n +CONFIG_SYS_RELOC_GD_ENV_ADDR=n +CONFIG_SAVEENV=n +CONFIG_NET=n +CONFIG_SPL_PARTITION_UUIDS=n +CONFIG_CMD_EXT4=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_READ=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MEMINFO=y +CONFIG_EXPERT=n +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_LEGACY_IMAGE_FORMAT=n +CONFIG_ARCH_FIXUP_FDT_MEMORY=n +CONFIG_MENU=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_PART=y +CONFIG_SHOW_REGS=y +CONFIG_LOG=y +CONFIG_LOGLEVEL=9 +CONFIG_SPL_LOGLEVEL=9 +CONFIG_TPL_LOGLEVEL=9 +CONFIG_SPL_LOG=y +CONFIG_SPL_LOG_MAX_LEVEL=9 +CONFIG_SPL_LOG_CONSOLE=y +CONFIG_LOG_ERROR_RETURN=y +CONFIG_CMD_CPU=n +CONFIG_BOOTM_NETBSD=n +CONFIG_BOOTM_PLAN9=n +CONFIG_BOOTM_RTEMS=n +CONFIG_BOOTM_VXWORKS=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_SAVEENV=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_RANDOM=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_UNLZ4=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_FLASH=n +CONFIG_RANDOM_UUID=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_BLOCK_CACHE=n +CONFIG_CMD_DATE=n +CONFIG_CMD_SLEEP=n +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_FAT=y +CONFIG_DOS_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_DM_ETH=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=65536 +CONFIG_FS_SQUASHFS=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_MD5=y +CONFIG_ZLIB_UNCOMPRESS=y +CONFIG_SPL_GZIP=y +CONFIG_SPL_ZLIB=y +CONFIG_GETOPT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_RAM_SIFIVE=n diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 14d79139..a3650211 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -707,6 +707,12 @@ config MMC_SUNXI_HAS_MODE_SWITCH bool depends on MMC_SUNXI +config MMC_PITON + bool "MMC support for OpenPiton SoC" + default y + help + This driver enables mmc controller support in uboot port for OpenPiton + config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" depends on DM_MMC && BLK && ARCH_AT91 diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 1c849cba..698dfe05 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o +obj-$(CONFIG_MMC_PITON) += piton_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c new file mode 100644 index 00000000..e54be447 --- /dev/null +++ b/drivers/mmc/piton_mmc.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Jaehoon Chung <jh80.chung(a)samsung.com> + * Portions Copyright 2011-2019 NVIDIA Corporation + * Portions Copyright 2021 Tianrui Wei + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ + +#include <asm/gpio.h> +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <log.h> +#include <div64.h> +#include <mmc.h> + +struct piton_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct piton_mmc_priv { + uint64_t piton_mmc_base_addr; /* peripheral id */ +}; + +// see mmc_read_blocks to see how it is used. +// start block is hidden at cmd->arg +// also, initialize the block size at init +static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) { + // check first if this is a pure command + if (data == NULL) { + return 0; + } + + // byte count counts all the bytes required for this command + uint64_t byte_cnt = data->blocks * data->blocksize; + // get which block in mmc card to start from + uint64_t start_block = cmd->cmdarg; + // buff points to the address we store the data stored at mmc card + unsigned *buff = (unsigned int *) data->dest; + + struct piton_mmc_priv *priv = dev_get_priv(dev); + // start address denotes the absolute address where the transmission start + uint64_t start_addr = priv->piton_mmc_base_addr + (start_block); + + /* if data is not empty*/ + if (data) { + + /* if there is a read */ + if (data->flags & MMC_DATA_READ) { + for (uint64_t i = 0; i < byte_cnt; i += 4) { + *(buff) = readl((void *)(start_addr + i)); + buff++; + } + } else { + /* else there is a write + * we don't handle write, so error right away + */ + return -ENODEV; + } + } + + return 0; +} + +static int piton_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct piton_mmc_priv *priv = dev_get_priv(dev); + struct piton_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg; + struct mmc *mmc; + + priv->piton_mmc_base_addr = dev_read_addr(dev); + cfg = &plat->cfg; + cfg->name = "PITON MMC"; + cfg->host_caps = MMC_MODE_8BIT; + cfg->f_max = 100000; + cfg->f_min = 400000; + cfg->voltages = MMC_VDD_21_22; + + mmc = &plat->mmc; + mmc->read_bl_len = MMC_MAX_BLOCK_LEN; + mmc->capacity_user = 0x100000000ULL; + mmc->capacity_user *= mmc->read_bl_len; + mmc->capacity_boot = 0; + mmc->capacity_rpmb = 0; + for (int i = 0; i < 4; i++) + mmc->capacity_gp[i] = 0; + mmc->capacity = 0x800000000ULL; + mmc->has_init = 1; + + /* fill in device description */ + struct blk_desc *bdesc; + + bdesc = mmc_get_blk_desc(mmc); + bdesc->lun = 0; + bdesc->hwpart = 0; + bdesc->type = 0; + bdesc->blksz = mmc->read_bl_len; + bdesc->log2blksz = LOG2(bdesc->blksz); + bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); + + return 0; +} +/* + * currently, this is ignored. we only use fixed speed + */ +static int piton_mmc_set_ios(struct udevice *dev) { return 0; } + +/* test if piton has the micro mmc card present + * always return 1, which means present + */ +static int piton_mmc_getcd(struct udevice *dev) { + + return 1; +} + +/* dummy function, piton_mmc don't need initialization in hw*/ +static int piton_mmc_init(struct udevice *dev) { + + return 0; +} + +static const struct dm_mmc_ops piton_mmc_ops = { + // send a command to mmc device + .send_cmd = piton_mmc_send_cmd, + // set iospeed + .set_ios = piton_mmc_set_ios, + // detect if card is present + .get_cd = piton_mmc_getcd, +}; + +static int piton_mmc_probe(struct udevice *dev) { + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct piton_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg = &plat->cfg; + + cfg->name = dev->name; + upriv->mmc = &plat->mmc; + upriv->mmc->has_init = 1; + upriv->mmc->capacity = 0x2000000000ULL; + upriv->mmc->read_bl_len = MMC_MAX_BLOCK_LEN; + + return piton_mmc_init(dev); +} + +static int piton_mmc_bind(struct udevice *dev) { + struct piton_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg = &plat->cfg; + + cfg->name = dev->name; + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT; + cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->f_min = 1000000; + cfg->f_max = 52000000; + cfg->b_max = U32_MAX; + + return mmc_bind(dev, &plat->mmc, cfg); +} + +static const struct udevice_id piton_mmc_ids[] = { + {.compatible = "openpiton,piton-mmc"}, {}}; + +U_BOOT_DRIVER(piton_mmc_drv) = { + .name = "piton_mmc", + .id = UCLASS_MMC, + .of_match = piton_mmc_ids, + .ofdata_to_platdata = piton_mmc_ofdata_to_platdata, + .bind = piton_mmc_bind, + .probe = piton_mmc_probe, + .ops = &piton_mmc_ops, + .platdata_auto_alloc_size = sizeof(struct piton_mmc_plat), + .priv_auto_alloc_size = sizeof(struct piton_mmc_priv), +}; diff --git a/include/configs/openpiton-riscv.h b/include/configs/openpiton-riscv.h new file mode 100644 index 00000000..514edbc6 --- /dev/null +++ b/include/configs/openpiton-riscv.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2021 Tianrui Wei + * + * Authors: + * Anup Patel <anup.patel(a)wdc.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ + +#ifndef __OPENPITON_RISCV_CONFIG_H +#define __OPENPITON_RISCV_CONFIG_H + +#include <linux/sizes.h> +#define DEBUG +#ifdef CONFIG_SPL +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x82000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000 +#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin" +#define CONFIG_SPL_GD_ADDR 0x85000000 +#endif + +/* Environment options */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +#define CONFIG_SYS_MALLOC_LEN SZ_256M +#define CONFIG_SYS_BOOTM_LEN SZ_256M + +/* ------------------------------------------------- + * Environment + */ +//Disable persistent environment variable storage +#define CONFIG_ENV_IS_NOWHERE 1 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ + +#define CONFIG_EXTRA_ENV_SETTINGS "\0" + +#define CONFIG_USE_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "fdt addr ${fdtcontroladdr}; " \ + "fdt move ${fdtcontroladdr} 0x86000000; " \ + "ext4load mmc 0:1 0x80200000 boot/Image; " \ + "booti 0x80200000 - 0x86000000; " + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#endif/* __CONFIG_H */ -- 2.17.1

1 1

[PATCH 1/4] watchdog: Set/unset GD_FLG_WDT_READY flag in wdt_start()/wdt_stop()
by Pali Rohár 06 Apr '21

06 Apr '21

Watchdog is ready after successful call of ops->start() callback in wdt_start() function. And is stopped after successful call of ops->stop() callback in wdt_stop function. So move setting of GD_FLG_WDT_READY flag from initr_watchdog() function to wdt_start() and ensure that GD_FLG_WDT_READY flag is unset in wdt_stop() function. This change ensures that GD_FLG_WDT_READY flag is set only when watchdog is running. And ensures that flag is also also when watchdog was started not only by initr_watchdog() call (e.g. by U-Boot 'wdt' command). Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/watchdog/wdt-uclass.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 28f7918c4673..3f707f61f74f 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -51,7 +51,6 @@ int initr_watchdog(void) } wdt_start(gd->watchdog_dev, timeout * 1000, 0); - gd->flags |= GD_FLG_WDT_READY; printf("WDT: Started with%s servicing (%ds timeout)\n", IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout); @@ -61,21 +60,31 @@ int initr_watchdog(void) int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { const struct wdt_ops *ops = device_get_ops(dev); + int ret; if (!ops->start) return -ENOSYS; - return ops->start(dev, timeout_ms, flags); + ret = ops->start(dev, timeout_ms, flags); + if (ret == 0) + gd->flags |= GD_FLG_WDT_READY; + + return ret; } int wdt_stop(struct udevice *dev) { const struct wdt_ops *ops = device_get_ops(dev); + int ret; if (!ops->stop) return -ENOSYS; - return ops->stop(dev); + ret = ops->stop(dev); + if (ret == 0) + gd->flags &= ~GD_FLG_WDT_READY; + + return ret; } int wdt_reset(struct udevice *dev) -- 2.20.1

2 19

[PATCH v2] mmc: mtk-sd: increase the minimum bus frequency
by Weijie Gao 06 Apr '21

06 Apr '21

With a 48MHz input clock, the lowest bus frequency can be as low as 48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause the mmc framework take seconds to finish the initialization. Limiting the minimum bus frequency to a slightly higher value can solve the issue without any side effects. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/mmc/mtk-sd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 3b9c122..626a4d3 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -232,6 +232,8 @@ #define SCLK_CYCLES_SHIFT 20 +#define MIN_BUS_CLK 200000 + #define CMD_INTS_MASK \ (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) @@ -1639,6 +1641,9 @@ static int msdc_drv_probe(struct udevice *dev) else cfg->f_min = host->src_clk_freq / (4 * 4095); + if (cfg->f_min < MIN_BUS_CLK) + cfg->f_min = MIN_BUS_CLK; + cfg->f_max = host->src_clk_freq; cfg->b_max = 1024; -- 1.9.1

3 2

[PATCH v2] cfi_flash: Fix detection of 8-bit bus flash devices via address shift
by Stefan Roese 06 Apr '21

06 Apr '21

From: Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki(a)xilinx.com> We had a problem detecting 8/16bit flash devices connected only via 8bits to the SoC for quite a while. Commit 239cb9d9 [mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support] finally fixed this 8-bit bus support. But also broke some other boards using this cfi driver. So this patch had to be reverted. I spotted a different, simpler approach for this 8-bit bus support on the barebox mailing list posted by Oleksij Rempel <bug-track(a)fisher-privat.net>: http://www.spinics.net/lists/u-boot-v2/msg14687.html Here the commit text: " Many cfi chips support 16 and 8 bit modes. Most important difference is use of so called "Q15/A-1" pin. In 16bit mode this pin is used for data IO. In 8bit mode, it is an address input which add one more least significant bit (LSB). In this case we should shift all adresses by one: For example 0xaa << 1 = 0x154 " This patch now is a port of this barebox patch to U-Boot. Along with the change w.r.t from barebox, Some flash chips can support multiple bus widths, override the interface width and limit it to the port width. Tested on 16-bit Spansion flash on sequoia. Tested 8-bit flashes like 256M29EW, 512M29EW. Signed-off-by: Stefan Roese <sr(a)denx.de> Tested-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Cc: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Cc: Aaron Williams <awilliams(a)marvell.com> Cc: Chandrakala Chavva <cchavva(a)marvell.com> Cc: Andre Przywara <andre.przywara(a)arm.com> Cc: Vignesh Raghavendra <vigneshr(a)ti.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Mario Six <mario.six(a)gdsys.cc> Cc: York Sun <york.sun(a)nxp.com> Cc: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- v2: - Rebase on current mainline I've run into problems with CFI flash on the MIPS Octeon EBB7304, where the CFI detection did not work. While testing and digging through the very old CFI related patches, I stumbled over this patch which fixes the problems on the EBB7304. I would really like to see some further testing of this patch on other boards using CFI parallel flash though. That's why I added some developers who did send CFI related patches in the last few years. So please test with this patch applied if possible. Thanks, Stefan drivers/mtd/cfi_flash.c | 37 +++++++++++++++++++++++++++++++++---- include/flash.h | 2 ++ 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index b4512e3a5f..9642d7c7dc 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -218,7 +218,7 @@ flash_map(flash_info_t *info, flash_sect_t sect, uint offset) { unsigned int byte_offset = offset * info->portwidth; - return (void *)(info->start[sect] + byte_offset); + return (void *)(info->start[sect] + (byte_offset << info->chip_lsb)); } static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, @@ -1918,12 +1918,27 @@ static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, sizeof(struct cfi_qry)); info->interface = le16_to_cpu(qry->interface_desc); + /* Some flash chips can support multiple bus widths. + * In this case, override the interface width and + * limit it to the port width. + */ + if ((info->interface == FLASH_CFI_X8X16) && + (info->portwidth == FLASH_CFI_8BIT)) { + debug("Overriding 16-bit interface width to" + " 8-bit port width\n"); + info->interface = FLASH_CFI_X8; + } else if ((info->interface == FLASH_CFI_X16X32) && + (info->portwidth == FLASH_CFI_16BIT)) { + debug("Overriding 16-bit interface width to" + " 16-bit port width\n"); + info->interface = FLASH_CFI_X16; + } info->cfi_offset = flash_offset_cfi[cfi_offset]; debug("device interface is %d\n", info->interface); - debug("found port %d chip %d ", - info->portwidth, info->chipwidth); + debug("found port %d chip %d chip_lsb %d ", + info->portwidth, info->chipwidth, info->chip_lsb); debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); @@ -1962,9 +1977,23 @@ static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) + info->chipwidth <<= 1) { + /* + * First, try detection without shifting the addresses + * for 8bit devices (16bit wide connection) + */ + info->chip_lsb = 0; + if (__flash_detect_cfi(info, qry)) + return 1; + + /* + * Not detected, so let's try with shifting + * for 8bit devices + */ + info->chip_lsb = 1; if (__flash_detect_cfi(info, qry)) return 1; + } } debug("not found\n"); return 0; diff --git a/include/flash.h b/include/flash.h index 3bf6b22399..42b18a6047 100644 --- a/include/flash.h +++ b/include/flash.h @@ -24,6 +24,8 @@ typedef struct { #ifdef CONFIG_SYS_FLASH_CFI uchar portwidth; /* the width of the port */ uchar chipwidth; /* the width of the chip */ + uchar chip_lsb; /* extra Least Significant Bit in the */ + /* address of chip */ ushort buffer_size; /* # of bytes in write buffer */ ulong erase_blk_tout; /* maximum block erase timeout */ ulong write_tout; /* maximum write timeout */ -- 2.30.1

1 1

[PATCH] timer: sifive_clint: Support the official clint DT bindings
by Bin Meng 06 Apr '21

06 Apr '21

Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings") adds the official DT bindings for CLINT, which uses "sifive,clint0" as the compatible string. "riscv,clint0" is now legacy and has to be kept for backward compatibility of legacy systems. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/timer/sifive_clint_timer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index de7b4b95c9..939b99d937 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -54,6 +54,7 @@ static int sifive_clint_probe(struct udevice *dev) static const struct udevice_id sifive_clint_ids[] = { { .compatible = "riscv,clint0" }, + { .compatible = "sifive,clint0" }, { } }; -- 2.25.1

2 2

[PATCH v2 00/19] video: sunxi: rework DE2 driver
by Jernej Skrabec 06 Apr '21

06 Apr '21

This series greatly reworks DE2 mixer and accompanying DW-HDMI platform driver. Main goal was to use as many information from device tree as possible and thus removing SoC speficic ifdefs from the code. This was largely accomplished for mixer, HDMI and HDMI PHY driver. Most of these changes are not user visible. Only improvements relevant to the user are filtering HDMI modes based on pixel clock and searching for additional detailed timings in EDID extension block. This change allows me to use 4k monitor that I have - base EDID block on this monitor holds only 4k@60 detailed timing. Other detailed timings, which are appropriate for HDMI 1.4 controller, are contained in extension block. There is plenty of work to do. TCON handling should go to dedicated driver and clock related code in TCON and DW-HDMI code should be moved to clock drivers. Testing was done only on H3. Best regards, Jernej Changes from v1: - collected tags - reword some commit messages - dropped patch 13 and 14 from v1 - 2 new patches, first add HDMI PHY driver and another drops PHY code from sunxi dw-hdmi driver and uses separate driver instead Jernej Skrabec (19): sunxi: video: select dw-hdmi in Kconfig, not Makefile video: sunxi: Add mode_valid callback to sunxi_dw_hdmi common: edid: check for digital display earlier common: edid: extract code for detailed timing search common: edid: Search for valid timing in extension block video: sunxi: Use DW-HDMI hpd function video: sunxi: Remove check for ddc-i2c-bus property video: sunxi: Remove TV probe from DE2 video: sunxi: de2: switch to public uclass functions video: sunxi: dw-hdmi: probe driver by compatible video: sunxi: dw-hdmi: read address from DT node video: sunxi: de2: switch to DT probing video: sunxi: de2: read address from DT node clk: sunxi: Add DE2 and HDMI clocks to H3 and A64 clk: sunxi: add DE2 clock driver video: sunxi: de2: switch clock setup to DM model video: dw-hdmi: modify phy init callback to include full timings video: sunxi: Add DW HDMI PHY driver video: sunxi: dw-hdmi: Use new PHY driver arch/arm/mach-sunxi/Kconfig | 3 + common/edid.c | 82 +++-- drivers/clk/sunxi/Kconfig | 5 + drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a64.c | 12 + drivers/clk/sunxi/clk_de2.c | 85 +++++ drivers/clk/sunxi/clk_h3.c | 12 + drivers/video/dw_hdmi.c | 6 +- drivers/video/meson/meson_dw_hdmi.c | 5 +- drivers/video/sunxi/Makefile | 2 +- drivers/video/sunxi/sunxi_de2.c | 191 +++++------ drivers/video/sunxi/sunxi_dw_hdmi.c | 300 ++++------------- drivers/video/sunxi/sunxi_dw_hdmi_phy.c | 423 ++++++++++++++++++++++++ drivers/video/sunxi/sunxi_dw_hdmi_phy.h | 24 ++ include/dw_hdmi.h | 4 +- 15 files changed, 780 insertions(+), 375 deletions(-) create mode 100644 drivers/clk/sunxi/clk_de2.c create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi_phy.c create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi_phy.h -- 2.30.1

5 36

[PATCH] patman: Continue on if warnings are found outside a commit
by Simon Glass 06 Apr '21

06 Apr '21

While we cannot know which commit the warning relates to, this should not be fatal. Print the warning and carry on. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/patman/patchstream.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index cdcd50a8499..a44cd861afc 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -133,8 +133,8 @@ class PatchStream: ValueError: Warning is generated with no commit associated """ if not self.commit: - raise ValueError('Warning outside commit: %s' % warn) - if warn not in self.commit.warn: + print('Warning outside commit: %s' % warn) + elif warn not in self.commit.warn: self.commit.warn.append(warn) def _add_to_series(self, line, name, value): -- 2.31.0.rc2.261.g7f71774620-goog

1 1

[PATCH v3 0/9] Use -ENOSYS consistently
by Simon Glass 06 Apr '21

06 Apr '21

A few places use -ENOTSUPP when they should use -ENOSYS. In two cases both are used. This little series tidies this up and documents the conventions. Changes in v3: - Add updates based on feedback from Sean Anderson <seanga2(a)gmail.com> Changes in v2: - Add a patch to document the common error codes - Add new patch for acpi_get_path() - Add new patch to update clk drivers to use -EINVAL Simon Glass (9): dm: core: Document the common error codes dm: core: Use -ENOSPC in acpi_get_path() usb: Return -ENOSYS when system call is not available spi: Return -ENOSYS when system call is not available tlv_eeprom: Return -ENOSYS when system call is not available clk: Update drivers to use -EINVAL clk: Return -ENOSYS when system call is not available simple-pm-bus: Use -ENOSYS for checking missing system call pinctrl: Return -ENOSYS when system call is not available doc/driver-model/design.rst | 133 +++++++++++++++++++++++++ drivers/clk/aspeed/clk_ast2600.c | 2 +- drivers/clk/clk-composite.c | 8 +- drivers/clk/clk-hsdk-cgu.c | 4 +- drivers/clk/imx/clk-imx8.c | 4 +- drivers/clk/imx/clk-imx8qm.c | 6 +- drivers/clk/imx/clk-imx8qxp.c | 6 +- drivers/clk/imx/clk-pllv3.c | 2 +- drivers/clk/kendryte/bypass.c | 2 +- drivers/clk/kendryte/clk.c | 2 +- drivers/clk/mvebu/armada-37xx-periph.c | 6 +- drivers/core/acpi.c | 2 +- drivers/core/simple-pm-bus.c | 4 +- drivers/pinctrl/pinctrl-uclass.c | 10 +- drivers/usb/gadget/udc/udc-uclass.c | 2 +- include/spi-mem.h | 2 +- include/tlv_eeprom.h | 6 +- 17 files changed, 168 insertions(+), 33 deletions(-) -- 2.31.0.291.g576ba9dcdaf-goog

2 19