March 2021 - U-Boot

[PATCH v2 1/2] mx23_olinuxino: enable device tree
by Trevor Woerner 09 Apr '21

09 Apr '21

Add the dts file for the Olimex Olinuxino from the linux kernel, and enable its use in this machine's defconfig. Signed-off-by: Trevor Woerner <twoerner(a)gmail.com> --- Changes in v2: - none --- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx23-olinuxino.dts | 131 +++++++++++++++++++++++++++++++ configs/mx23_olinuxino_defconfig | 3 +- 3 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx23-olinuxino.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c6710826a0..d5cffc90d4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -651,6 +651,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ dtb-$(CONFIG_MX23) += \ imx23-evk.dtb +dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \ + imx23-olinuxino.dtb + dtb-$(CONFIG_MX28) += \ imx28-xea.dtb diff --git a/arch/arm/dts/imx23-olinuxino.dts b/arch/arm/dts/imx23-olinuxino.dts new file mode 100644 index 0000000000..0729e72f22 --- /dev/null +++ b/arch/arm/dts/imx23-olinuxino.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx23.dtsi" + +/ { + model = "i.MX23 Olinuxino Low Cost Board"; + compatible = "olimex,imx23-olinuxino", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + broken-cd; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_ALE__GPIO_0_17 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + led_pin_gpio2_1: led_gpio2_1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DETECT__GPIO_2_1 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + }; + + ssp1: spi@80034000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + }; + }; + + apbx@80040000 { + lradc@80050000 { + status = "okay"; + }; + + i2c: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_b>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "host"; + vbus-supply = <&reg_usb0_vbus>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio2_1>; + + user { + label = "green"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 0da54c9e76..2bf6818ee3 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX23_OLINUXINO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -24,6 +25,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -44,4 +46,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_OF_LIBFDT=y -- 2.30.0.rc0

2 3

[PATCH v1] imx: bootaux fix elf loading
by Max Krummenacher 09 Apr '21

09 Apr '21

This reverts the arch/arm/mach-imx/imx_bootaux.c changes of commit 805b3cac1e0c. The loader function name was changed so that it does not clash with the generically available function in lib/elf.c. imx-bootaux loads an elf file linked for an auxilary core. Thus the loader function requires address translation from the auxilary core's address space to where those are mapped into U-Boot's address space. So the elf loader is specific and must not be replaced with a generic loader which doesn't provide the address translation functionality. Fixes commit 805b3cac1e0c ("lib: elf: Move the generic elf loading/validating functions to lib") Signed-off-by: Max Krummenacher <max.krummenacher(a)toradex.com> --- arch/arm/mach-imx/imx_bootaux.c | 67 ++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index e1fc4b3e19a..30fb45d48c2 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -14,6 +14,71 @@ #include <linux/compiler.h> #include <cpu_func.h> +#ifndef CONFIG_IMX8M +const __weak struct rproc_att hostmap[] = { }; + +static const struct rproc_att *get_host_mapping(unsigned long auxcore) +{ + const struct rproc_att *mmap = hostmap; + + while (mmap && mmap->size) { + if (mmap->da <= auxcore && + mmap->da + mmap->size > auxcore) + return mmap; + mmap++; + } + + return NULL; +} + +/* + * A very simple elf loader for the auxilary core, assumes the image + * is valid, returns the entry point address. + * Translates load addresses in the elf file to the U-Boot address space. + */ +static unsigned long load_elf_image_m_core_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* ELF header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { + const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr); + void *dst, *src; + + if (phdr->p_type != PT_LOAD) + continue; + + if (!mmap) { + printf("Invalid aux core address: %08x", + phdr->p_paddr); + return 0; + } + + dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa; + src = (void *)addr + phdr->p_offset; + + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst & + ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE)); + } + + return ehdr->e_entry; +} +#endif + int arch_auxiliary_core_up(u32 core_id, ulong addr) { ulong stack, pc; @@ -31,7 +96,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) */ if (valid_elf_image(addr)) { stack = 0x0; - pc = load_elf_image_phdr(addr); + pc = load_elf_image_m_core_phdr(addr); if (!pc) return CMD_RET_FAILURE; -- 2.20.1

3 2

[PATCH 1/2] mmc: fsl_esdhc_imx: remove redundant cmd11 related code.
by haibo.chen＠nxp.com 09 Apr '21

09 Apr '21

From: Haibo Chen <haibo.chen(a)nxp.com> Common code already handle the voltage switch sequence based on spec, so remove the redundant voltage switch code. Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 637537d262..722f33c68c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -521,15 +521,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, goto out; } - /* Switch voltage to 1.8V if CMD11 succeeded */ - if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { - esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); - - printf("Run CMD11 1.8V switch\n"); - /* Sleep for 5 ms - max time for card to switch to 1.8V */ - udelay(5000); - } - /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { int timeout = 50000; -- 2.17.1

4 5

[PATCH 1/2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
by haibo.chen＠nxp.com 09 Apr '21

09 Apr '21

From: Haibo Chen <haibo.chen(a)nxp.com> For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"), we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON, after CMD11, hardware will gate off the card clock automatically, so card do not detect the clock off/on behavior, so will draw the data0 line low until next command. Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support") Tested-by: Tim Harvey <tharvey(a)gateworks.com> Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 29 +++++++++++++++++++++-------- include/fsl_esdhc_imx.h | 2 ++ 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index e0e132698e..af36558b3c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -654,7 +654,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); #endif @@ -666,7 +669,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -721,8 +724,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); struct fsl_esdhc *regs = priv->esdhc_regs; u32 val; + u32 tmp; + int ret; if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); /* @@ -740,6 +749,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) pr_warn("HS400 strobe DLL status REF not lock!\n"); if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) pr_warn("HS400 strobe DLL status SLV not lock!\n"); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); } } @@ -963,14 +973,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); + u32 tmp; + + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); #endif } else { #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_CKEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -1046,7 +1060,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); #else - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif /* Set the initial clock speed */ @@ -1184,8 +1198,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_write32(&regs->autoc12err, 0); esdhc_write32(&regs->clktunectrlstatus, 0); #else - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif if (priv->vs18_enable) diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 45ed635a77..b092034464 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -39,6 +39,7 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -96,6 +97,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) -- 2.17.1

5 10

[PATCH] ARM: pcm058: Match mainline Linux NAND ECC layout/behaviour
by Niel Fourie 09 Apr '21

09 Apr '21

Enabled "fsl,legacy-bch-geometry" in U-Boot device tree overlay to match the legacy BCH geometry layout, which mainline Linux applies when "fsl,use-minimum-ecc" is not specified in the device tree. Reinstated SYS_NAND_ONFI_DETECTION, which when disabled, masked the mismatch on SOMs with Winbond NAND flash chips. Signed-off-by: Niel Fourie <lusus(a)denx.de> --- arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi | 5 +++++ include/configs/pcm058.h | 1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi index 8555be16966..0bea652beea 100644 --- a/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi +++ b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi @@ -40,3 +40,8 @@ &m25p80 { u-boot,dm-spl; }; + +&gpmi { + fsl,legacy-bch-geometry; +}; + diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 4f03699117b..bc48e809498 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -19,6 +19,7 @@ /* Enable NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -- 2.30.2

2 1

[PATCH 1/3] configs: stm32mp1: stm32mp1: Increase SPL malloc() size
by Alexandru Gagniuc 09 Apr '21

09 Apr '21

Since commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images"), FIT images must be malloc()'d before being loaded. The old size of 1 MiB is suitable for FIT images with u-boot and an FDT, but something containing a linux kernel is almost sure to fail. It's safe to extend malloc all the way to 0xc2000000, but no further. Linux likes to be loaded at 0xc2000000, so we use that as our cutoff point. This gives us 29 MiB of malloc() space, which suited for more complex FIT images including several DTBs, kernel, and OP-TEE images. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- include/configs/stm32mp1.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index db2117a3d7..7fdb3ffce4 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -53,7 +53,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0xC0200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x01D00000 /* limit SYSRAM usage to first 128 KB */ #define CONFIG_SPL_MAX_SIZE 0x00020000 -- 2.26.2

3 11

[PATCH v3 0/8] stm32: Add Engicam STM32MP1 SoM
by Jagan Teki 09 Apr '21

09 Apr '21

Patch series for Engicam i.Core and MicroGEA SoM and it's associated carrier board dts(i) support. Changes for v3: - collect Patrick Delaunay r-b - fixed comments from Patrick Delaunay Changes for v2: - add Linux dts commit ids in commit messages - drop CONFIG_BOARD_EARLY_INIT_F - order dts files in Makefile - collect Patrice r-b Any inputs? Jagan. Jagan Teki (8): ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3 ARM: stm32: Imply SPL_SPI_LOAD board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF arch/arm/dts/Makefile | 4 + .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 +++++++++++ ...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi | 51 +++++ .../stm32mp157a-icore-stm32mp1-ctouch2.dts | 47 +++++ ...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi | 51 +++++ .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 47 +++++ .../stm32mp157a-icore-stm32mp1-u-boot.dtsi | 146 +++++++++++++ arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 ++++++++++++++++++ ...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi | 51 +++++ ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++++++++++++++ ...-microgea-stm32mp1-microdev2.0-u-boot.dtsi | 51 +++++ ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 55 +++++ .../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 118 +++++++++++ .../dts/stm32mp157a-microgea-stm32mp1.dtsi | 148 +++++++++++++ arch/arm/mach-stm32mp/Kconfig | 54 ++++- board/engicam/stm32mp1/Kconfig | 12 ++ board/engicam/stm32mp1/MAINTAINERS | 26 +++ board/engicam/stm32mp1/Makefile | 10 + board/engicam/stm32mp1/spl.c | 48 +++++ board/engicam/stm32mp1/stm32mp1.c | 125 +++++++++++ ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 79 +++++++ ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig | 79 +++++++ ...-microgea-stm32mp1-microdev2-of7_defconfig | 79 +++++++ ...mp15-microgea-stm32mp1-microdev2_defconfig | 79 +++++++ 24 files changed, 1828 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi create mode 100644 board/engicam/stm32mp1/Kconfig create mode 100644 board/engicam/stm32mp1/MAINTAINERS create mode 100644 board/engicam/stm32mp1/Makefile create mode 100644 board/engicam/stm32mp1/spl.c create mode 100644 board/engicam/stm32mp1/stm32mp1.c create mode 100644 configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig create mode 100644 configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig -- 2.25.1

2 16

[PATCH] ARM: imx: imx8mn-ddr4-evk: Add ethernet support
by Marek Vasut 08 Apr '21

08 Apr '21

Add support for ethernet on the imx8mn-ddr4-evk. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/imx8mn-evk.dtsi | 1 + board/freescale/imx8mn_evk/imx8mn_evk.c | 41 +++++++++++++++++++++++-- configs/imx8mn_ddr4_evk_defconfig | 8 +++++ 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index 76d042a4cf0..416fadb22b1 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -53,6 +53,7 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <&ethphy0>; + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; fsl,magic-packet; status = "okay"; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index 9a0a0488bf4..8c4bb6c5b8e 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -6,18 +6,53 @@ #include <common.h> #include <env.h> #include <init.h> +#include <miiphy.h> +#include <netdev.h> #include <asm/global_data.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -int board_init(void) +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) { + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + return 0; } -int board_mmc_get_env_dev(int devno) +int board_phy_config(struct phy_device *phydev) { - return devno; + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; } int board_late_init(void) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index f7ea65886d5..c9a00bf2c2f 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -43,6 +43,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y @@ -71,7 +74,12 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -- 2.30.0

6 15

[PATCH 00/11] imx: ventana: convert Gateworks Ventana to dm
by Tim Harvey 08 Apr '21

08 Apr '21

This is the first series converting the IMX6 basd Gateworks Ventana boards to driver-model. This series resolves some issues with NAND SPL (non DM SPL) in order to read the FIT image. Additionally it covers conversions to DM_USB, DM_MMC, DM_MTD, and DM_SPI. Remaining items are DM_PCI and DM_ETH which I'm still working through. Tim Tim Harvey (11): spl: fit: nand: skip bad block handling if NAND chip not fully defined spl: fit: nand: allow for non-page-aligned elements dt-bindings: add tda1997x and bindings imx: ventana: add Gateworks Ventana dts arm: dts: imx6qdl-gw*: add dr_mode prop to dt to avoid error imx: ventana: convert U-Boot to OF_CONTROL using FIT image imx: ventana: add pinctrl and remove unneeded UART init and config imx: ventana: enable dm support for USB imx: ventana: enable dm support for MMC and SATA imx: ventana: enable dm for MTD and NAND imx: ventana: enable dm for SPI arch/arm/dts/Makefile | 28 + arch/arm/dts/imx6dl-gw51xx.dts | 13 + arch/arm/dts/imx6dl-gw52xx.dts | 71 ++ arch/arm/dts/imx6dl-gw53xx.dts | 71 ++ arch/arm/dts/imx6dl-gw54xx.dts | 71 ++ arch/arm/dts/imx6dl-gw551x.dts | 55 ++ arch/arm/dts/imx6dl-gw552x.dts | 14 + arch/arm/dts/imx6dl-gw553x.dts | 55 ++ arch/arm/dts/imx6dl-gw560x.dts | 55 ++ arch/arm/dts/imx6dl-gw5903.dts | 55 ++ arch/arm/dts/imx6dl-gw5904.dts | 55 ++ arch/arm/dts/imx6dl-gw5907.dts | 14 + arch/arm/dts/imx6dl-gw5910.dts | 14 + arch/arm/dts/imx6dl-gw5912.dts | 13 + arch/arm/dts/imx6dl-gw5913.dts | 14 + arch/arm/dts/imx6q-gw51xx.dts | 13 + arch/arm/dts/imx6q-gw52xx.dts | 75 ++ arch/arm/dts/imx6q-gw53xx.dts | 75 ++ arch/arm/dts/imx6q-gw54xx.dts | 177 ++++ arch/arm/dts/imx6q-gw551x.dts | 55 ++ arch/arm/dts/imx6q-gw552x.dts | 18 + arch/arm/dts/imx6q-gw553x.dts | 55 ++ arch/arm/dts/imx6q-gw560x.dts | 59 ++ arch/arm/dts/imx6q-gw5903.dts | 55 ++ arch/arm/dts/imx6q-gw5904.dts | 59 ++ arch/arm/dts/imx6q-gw5907.dts | 14 + arch/arm/dts/imx6q-gw5910.dts | 14 + arch/arm/dts/imx6q-gw5912.dts | 13 + arch/arm/dts/imx6q-gw5913.dts | 14 + arch/arm/dts/imx6qdl-gw51xx.dtsi | 638 +++++++++++++ arch/arm/dts/imx6qdl-gw52xx.dtsi | 782 ++++++++++++++++ arch/arm/dts/imx6qdl-gw53xx.dtsi | 772 ++++++++++++++++ arch/arm/dts/imx6qdl-gw54xx.dtsi | 866 ++++++++++++++++++ arch/arm/dts/imx6qdl-gw551x.dtsi | 698 +++++++++++++++ arch/arm/dts/imx6qdl-gw552x.dtsi | 522 +++++++++++ arch/arm/dts/imx6qdl-gw553x.dtsi | 738 +++++++++++++++ arch/arm/dts/imx6qdl-gw560x.dtsi | 937 ++++++++++++++++++++ arch/arm/dts/imx6qdl-gw5903.dtsi | 796 +++++++++++++++++ arch/arm/dts/imx6qdl-gw5904.dtsi | 814 +++++++++++++++++ arch/arm/dts/imx6qdl-gw5907.dtsi | 539 +++++++++++ arch/arm/dts/imx6qdl-gw5910.dtsi | 668 ++++++++++++++ arch/arm/dts/imx6qdl-gw5912.dtsi | 609 +++++++++++++ arch/arm/dts/imx6qdl-gw5913.dtsi | 501 +++++++++++ board/gateworks/gw_ventana/MAINTAINERS | 48 + board/gateworks/gw_ventana/common.c | 17 - board/gateworks/gw_ventana/common.h | 1 - board/gateworks/gw_ventana/gsc.c | 88 ++ board/gateworks/gw_ventana/gsc.h | 1 + board/gateworks/gw_ventana/gw_ventana.c | 138 +-- board/gateworks/gw_ventana/gw_ventana_spl.c | 10 +- common/spl/spl_nand.c | 24 +- configs/gwventana_emmc_defconfig | 20 +- configs/gwventana_gw5904_defconfig | 20 +- configs/gwventana_nand_defconfig | 22 +- drivers/mtd/nand/raw/mxs_nand_spl.c | 5 + include/configs/gw_ventana.h | 15 +- include/dt-bindings/media/tda1997x.h | 74 ++ 57 files changed, 11501 insertions(+), 156 deletions(-) create mode 100644 arch/arm/dts/imx6dl-gw51xx.dts create mode 100644 arch/arm/dts/imx6dl-gw52xx.dts create mode 100644 arch/arm/dts/imx6dl-gw53xx.dts create mode 100644 arch/arm/dts/imx6dl-gw54xx.dts create mode 100644 arch/arm/dts/imx6dl-gw551x.dts create mode 100644 arch/arm/dts/imx6dl-gw552x.dts create mode 100644 arch/arm/dts/imx6dl-gw553x.dts create mode 100644 arch/arm/dts/imx6dl-gw560x.dts create mode 100644 arch/arm/dts/imx6dl-gw5903.dts create mode 100644 arch/arm/dts/imx6dl-gw5904.dts create mode 100644 arch/arm/dts/imx6dl-gw5907.dts create mode 100644 arch/arm/dts/imx6dl-gw5910.dts create mode 100644 arch/arm/dts/imx6dl-gw5912.dts create mode 100644 arch/arm/dts/imx6dl-gw5913.dts create mode 100644 arch/arm/dts/imx6q-gw51xx.dts create mode 100644 arch/arm/dts/imx6q-gw52xx.dts create mode 100644 arch/arm/dts/imx6q-gw53xx.dts create mode 100644 arch/arm/dts/imx6q-gw54xx.dts create mode 100644 arch/arm/dts/imx6q-gw551x.dts create mode 100644 arch/arm/dts/imx6q-gw552x.dts create mode 100644 arch/arm/dts/imx6q-gw553x.dts create mode 100644 arch/arm/dts/imx6q-gw560x.dts create mode 100644 arch/arm/dts/imx6q-gw5903.dts create mode 100644 arch/arm/dts/imx6q-gw5904.dts create mode 100644 arch/arm/dts/imx6q-gw5907.dts create mode 100644 arch/arm/dts/imx6q-gw5910.dts create mode 100644 arch/arm/dts/imx6q-gw5912.dts create mode 100644 arch/arm/dts/imx6q-gw5913.dts create mode 100644 arch/arm/dts/imx6qdl-gw51xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw52xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw53xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw54xx.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw551x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw552x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw553x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw560x.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5903.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5904.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5907.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5910.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5912.dtsi create mode 100644 arch/arm/dts/imx6qdl-gw5913.dtsi create mode 100644 include/dt-bindings/media/tda1997x.h -- 2.17.1

6 33

[PATCH 0/4] Updates for Toradex boards
by Oleksandr Suvorov 08 Apr '21

08 Apr '21

This patchset includes fixes and improvements for Toradex boards. Igor Opaniuk (1): colibri_imx6: adjust boot order Oleksandr Suvorov (2): apalis/colibri_imx6: remove video= settings board: toradex: apalis-imx8x: fix build instructions Philippe Schenker (1): colibri_imx6ull/imx7: add missing tdxargs variable doc/board/toradex/apalix-imx8x.rst | 33 ++++++++++++++++-------------- include/configs/apalis_imx6.h | 5 +---- include/configs/colibri-imx6ull.h | 2 +- include/configs/colibri_imx6.h | 4 +--- include/configs/colibri_imx7.h | 2 +- 5 files changed, 22 insertions(+), 24 deletions(-) -- 2.29.2

2 8