February 2021 - U-Boot

[PATCH] rockchip: rk3399: rock960: explicitly disable SPI flash
by Peter Robinson 14 Feb '21

14 Feb '21

The Rock960 doesn't have SPI flash on-board, but the bits get enabled by default which means when booting we get some errors. Explicitly disable it to stop the errors. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- configs/rock960-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 56ebaeb34e..b274bbbbe9 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_SF is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y -- 2.29.2

1 0

[PATCH] include: configs: rk3399: drop a dangling comment
by Peter Robinson 14 Feb '21

14 Feb '21

Drop a irrelevent comment now the related configs have moved to the various config files. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- include/configs/rk3399_common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index d0fc598319..b37ed5cce0 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -75,6 +75,4 @@ #endif -/* enable usb config for usb ether */ - #endif -- 2.29.2

1 0

Pull request for UEFI sub-system for efi-2021-04-rc2-2
by Heinrich Schuchardt 14 Feb '21

14 Feb '21

Hello Tom, in the following pull request I have included a correction for binman because without it Gitlab has a time out on the binman job. The binman patch has been reviewed by Simon. See https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/6381 which passed and https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/6379 which timed out. The following changes since commit 7c82e12cc4e9e25d7c89fe15bfeec4e9b0bb2b4d: Merge tag 'u-boot-atmel-fixes-2021.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel (2021-02-12 09:09:10 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2021-04-rc2-2 for you to fetch changes up to fd434f47d4d008d41f4ee2fe5cb94791f780395c: buildman: 'Thread' object has no attribute 'isAlive' (2021-02-14 11:32:04 +0100) Gitlab shows no problem: https://gitlab.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/6381 ---------------------------------------------------------------- Pull request for UEFI sub-system for efi-2021-04-rc2-2 Bug fixes: * fix stack smashing in UEFI capsule updates * correct loading of UEFI binaries where Virtual size is not a multiple of FileAlignment * simplify detection of capsule files. * buildman: use threading.is_alive() instead of removed method IsAlive() ---------------------------------------------------------------- Asherah Connor (1): efi_loader: don't load beyond VirtualSize Heinrich Schuchardt (3): efi_loader: '.' and '..' are directories efi_loader: fix get_last_capsule() buildman: 'Thread' object has no attribute 'isAlive' lib/efi_loader/efi_capsule.c | 22 ++++++++++++++-------- lib/efi_loader/efi_image_loader.c | 2 +- tools/buildman/builder.py | 2 +- 3 files changed, 16 insertions(+), 10 deletions(-)

2 1

[PATCH] sunxi: Remove dead ifdefs in sunxi-common.h
by Samuel Holland 14 Feb '21

14 Feb '21

As variables were moved to Kconfig, some of the surrounding ifdefs were left around, even though they were empty. Clean them up. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- include/configs/sunxi-common.h | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 000f3864702..64a70f9375c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -134,11 +134,6 @@ #define CONFIG_BOARD_SIZE_LIMIT 0x7e000 #endif -#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 -/* If we have two devices (most likely eMMC + MMC), favour the eMMC */ -#else -/* Otherwise, use the only device we have */ -#endif #define CONFIG_SYS_MMC_MAX_DEVICE 4 #endif @@ -199,10 +194,6 @@ /* I2C */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_SY8106A_POWER -#endif - #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE @@ -232,12 +223,6 @@ extern int soft_i2c_gpio_scl; #define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ #endif -/* PMU */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \ - defined CONFIG_SY8106A_POWER -#endif - #ifdef CONFIG_REQUIRE_SERIAL_CONSOLE #if CONFIG_CONS_INDEX == 1 #ifdef CONFIG_MACH_SUN9I -- 2.26.2

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Re: [PATCH v2 1/1] timer: imx-gpt: Add timer support for i.MX SoCs family
by Giulio Benetti 14 Feb '21

14 Feb '21

Hi Jesse, I re-add all people and ML in Cc so they can follow. Next time reply to all. On 2/10/21 8:00 PM, Jesse Taube wrote: > > On 2/10/21 12:49 PM, Giulio Benetti wrote: >> On 2/10/21 1:04 AM, Jesse Taube wrote: >>> This timer driver is using GPT Timer (General Purpose Timer) >>> available on almost all i.MX SoCs family. >>> Since this driver is only meant to provide u-boot's timer and >>> counter, and most of the i.MX* SoCs use a 24Mhz crystal, let's only >>> deal with that specific source. >> >> We have a problem with columns on commit log, they shouldn't be longer >> than 72 cols, so please check the editor you're using for commit log >> writing and set 72 cols costrains. I use nano and you only need to set >> in .gitconfig under [core]: >> editor = nano -b -r 72 >> >> This way nano automatically put a CR. >> >>> >>> Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> >>> Signed-off-by: Jesse Taube <mr.bossman075(a)gmail.com> >>> >>> --- >>> drivers/timer/Kconfig | 7 ++ >>> drivers/timer/Makefile | 1 + >>> drivers/timer/imx-gpt-timer.c | 132 ++++++++++++++++++++++++++++++++++ >>> 3 files changed, 140 insertions(+) >>> create mode 100644 drivers/timer/imx-gpt-timer.c >>> >>> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig >>> index 80743a2551..ee81dfa776 100644 >>> --- a/drivers/timer/Kconfig >>> +++ b/drivers/timer/Kconfig >>> @@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER >>> Select this to enable support for Microchip 64-bit periodic >>> interval timer. >>> +config IMX_GPT_TIMER >>> + bool "NXP i.MX GPT timer support" >>> + depends on TIMER >>> + help >>> + Select this to enable support for the timer found on >>> + NXP i.MX devices. >>> + >>> endmenu >>> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile >>> index eb5c48cc6c..e214ba7268 100644 >>> --- a/drivers/timer/Makefile >>> +++ b/drivers/timer/Makefile >>> @@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER) += stm32_timer.o >>> obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o >>> obj-$(CONFIG_MTK_TIMER) += mtk_timer.o >>> obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o >>> +obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o >>> diff --git a/drivers/timer/imx-gpt-timer.c >>> b/drivers/timer/imx-gpt-timer.c >>> new file mode 100644 >>> index 0000000000..58c37db300 >>> --- /dev/null >>> +++ b/drivers/timer/imx-gpt-timer.c >>> @@ -0,0 +1,132 @@ >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Copyright (C) 2020 >>> + * Author(s): Giulio Benetti <giulio.benetti(a)benettiengineering.com> >>> + */ >>> + >>> +#include <common.h> >>> +#include <clk.h> >>> +#include <dm.h> >>> +#include <fdtdec.h> >>> +#include <timer.h> >>> +#include <dm/device_compat.h> >>> + >>> +#include <asm/io.h> >>> + >>> +#define GPT_CR_SWR 0x00008000 >>> +#define GPT_CR_CLKSRC 0x000001C0 >>> +#define GPT_CR_EN_24M 0x00004000 >>> +#define GPT_CR_EN 0x00000001 >>> +#define GPT_PR_PRESCALER 0x00000FFF >>> +#define GPT_PR_PRESCALER24M 0x0000F000 >> >> Here ^^^ and >> >>> +#define NO_CLOCK (0) >>> +#define IPG_CLK (1 << 6) >>> +#define IPG_CLK_HF (2 << 6) >>> +#define IPG_EXT (3 << 6) >>> +#define IPG_CLK_32K (4 << 6) >>> +#define IPG_CLK_24M (5 << 6) >> here you still have different tab numbers. Enable in your editor the >> option to show whitespaces and tabs, that way everything it easier. > I still don't exactly understand what you mean here. Should I press tab > 3 times exactly instead of making the values line up. You need to check using an editor with whitespaces and tabs options enabled and tabs set to 8 spaces how that code looks like. > In the commit log > it seems to change weirdly because of the '+' in front of the define. Here it is the same, this should be due to the editor you use for commit log. >>> + >>> +struct imx_gpt_timer_regs { >>> + u32 cr; >>> + u32 pr; >>> + u32 sr; >>> + u32 ir; >>> + u32 ocr1; >>> + u32 ocr2; >>> + u32 ocr3; >>> + u32 icr1; >>> + u32 icr2; >>> + u32 cnt; >>> +}; >>> + >>> +struct imx_gpt_timer_priv { >>> + struct imx_gpt_timer_regs *base; >>> +}; >>> + >>> +static u64 imx_gpt_timer_get_count(struct udevice *dev) >>> +{ >>> + struct imx_gpt_timer_priv *priv = dev_get_priv(dev); >>> + struct imx_gpt_timer_regs *regs = priv->base; >>> + >>> + return readl(&regs->cnt); >>> +} >>> + >>> +static int imx_gpt_timer_probe(struct udevice *dev) >>> +{ >>> + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); >>> + struct imx_gpt_timer_priv *priv = dev_get_priv(dev); >>> + struct imx_gpt_timer_regs *regs; >>> + struct clk clk; >>> + fdt_addr_t addr; >>> + u32 prescaler; >>> + u32 rate; >>> + int ret; >>> + >>> + addr = dev_read_addr(dev); >>> + if (addr == FDT_ADDR_T_NONE) >>> + return -EINVAL; >>> + >>> + priv->base = (struct imx_gpt_timer_regs *)addr; >>> + >>> + ret = clk_get_by_index(dev, 0, &clk); >>> + if (ret < 0) >>> + return ret; >>> + >>> + ret = clk_enable(&clk); >>> + if (ret) { >>> + dev_err(dev, "Failed to enable clock\n"); >>> + return ret; >>> + } >>> + >>> + regs = priv->base; >>> + >>> + /* Reset the timer */ >>> + setbits_le32(&regs->cr, GPT_CR_SWR); >>> + >>> + /* Wait for timer to finish reset */ >>> + while (readl(&regs->cr) & GPT_CR_SWR) >>> + ; >>> + >>> + /* Get timer clock rate */ >>> + rate = clk_get_rate(&clk); >> >> clk_get_rate() has a wrong description in include/clk.h saying: >> "@return clock rate in Hz, or -ve error code." >> >> This ^^^ is wrong. >> If you dig into drivers/clk/clk-uclass.c and look for clk_get_rate(), >> you will see that it returns 0 on error and > 0 if succesfull. >> >> I've just sent a patch for this: >> https://patchwork.ozlabs.org/project/uboot/patch/20210210173722.4823-1-giul… >> >> >>> + if ((int)rate <= 0) { >> >> This ^^^^ is a cast trying to solve the problem above but it's >> not correct. clk_get_rate() returns ulong, not int, so modify "int >> rate" into "ulong rate". > Ah this makes sense now. >> >>> + dev_err(dev, "Could not get clock rate...\n"); >>> + return -EINVAL; >>> + } >>> + /* Only support 24MHz clock */ >> >> Extend to /* Only support 24MHz crystal clock */ otherwise it seems >> that every 24Mhz clock is accepted and it's not that way. >> >> I don't know a sure way to be bounded to crystal clock, suggestions >> are welcome. >> >>> + if (rate != 24000000UL) { >>> + dev_err(dev, "Clock rate other than 24MHz not supported...\n"); >>> + return -EINVAL; >>> + } >>> + /* We set timer prescaler to obtain a 1MHz timer counter >>> frequency */ >>> + prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1; >> >> Here you should check against maximum value of PRESCALER(0xFFF), if >> prescaler is > 0xFFF then you have to return with error. >> >>> + writel(GPT_PR_PRESCALER & prescaler, &regs->pr); >>> + /* Set timer frequency to 1MHz */ >>> + uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; >>> + >>> + clrbits_le32(&regs->cr, GPT_CR_CLKSRC); >>> + setbits_le32(&regs->cr, IPG_CLK); >> >> Here IPG_CLK should be IPG_CLK_24M as discussed previously. > > The IPG_CLK_24M needs a different prescaler and a second enable bit. > This will completely bypass all other clock sources making the check for > the clock rate useless. Yes, in the operative way yes, you could also avoid passing clock source through dts, but this way we check that the right clock source is passed to dts, and that is the correct way to work I think. > It will also mean that even if we don't have a > correct clock source it will work at the correct timing. Yes if they provide 24Mhz. I wanted it to be like that at the moment, because a lot of imx SoCs setup GPT like that. Take a look here: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-imx/timer.… This way the imx6* and imx7 could add their .compatible to this driver in the future. If someone will need some specific tweaking then they would send a patch adding such new DT property, like using 32K source. But that comes next IMHO, otherwise we should describe entirely GPT peripheral but what we need at the moment is getting 1ms tick like lot of other imx SoCs already do. The other chance would be to treat all the clock sources possibilities, but, at least for me, to begin this is sufficient and can be improved later. > I changed it to use only the 24MHz clock and ignore all others, Ok > at some > point it would be nice to have it only as a backup clock if the ccm was > not configured. I don't understand what you mean with backup clock can you elaborate more? Thank you Best regards -- Giulio Benetti Benetti Engineering sas

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qemu arm: increasing log-level causes exception
by Zack Marvel 14 Feb '21

14 Feb '21

Hello, I wanted to observe some debug messages, so I increased the log level from 6 to 7. Otherwise, my configuration matches 'qemu_arm_defconfig'. This resulted in a PREFETCH fault. The backtrace is included below. My u-boot version is v2021.01. My compiler is arm-none-eabi-gcc 7.3.1 from Debian. I tested qemu 3.1.0 (from Debian) and 5.1.0 (which I built), invoked like this: qemu-system-arm -machine virt -cpu cortex-a15 -m 2G -bios u-boot/build.qemu_arm/u-boot.bin I think this is happening because the code has been relocated and the MMU enabled, but the functions pointed to by gd->cur_serial_dev->driver->ops still point to the code in flash: (gdb) p *((struct dm_serial_ops*)(gd->cur_serial_dev->driver->ops)) $3 = {setbrg = 0x4296c <pl01x_serial_setbrg>, getc = 0x42af0 <pl01x_serial_getc>, putc = 0x42b34 <pl01x_serial_putc>, pending = 0x42b68 <pl01x_serial_pending>, clear = 0x0 <v7_arch_cp15_set_l2aux_ctrl>, getconfig = 0x0 <v7_arch_cp15_set_l2aux_ctrl>, setconfig = 0x0 <v7_arch_cp15_set_l2aux_ctrl>, getinfo = 0x0 <v7_arch_cp15_set_l2aux_ctrl>} I was able to workaround this behavior by adding gd->cur_serial_dev = NULL; in board_init_r before the post-relocation initialization sequence is executed. Rearranging init_sequence_r so that log_init runs after serial_initialize works too. I would like to contribute a patch, but I require some guidance. Is there a better way to indicate that log messages should not be output until the driver has been reinitialized by board_init_r? Or is there a better initialization order? Thanks and best regards, Zack Marvel Backtrace: #0 pl01x_serial_putc (dev=0x401fe180, ch=105 'i') at ../drivers/serial/serial_pl01x.c:316 #1 0xbff73504 in _serial_putc (dev=dev@entry=0x401fe180, ch=<optimized out>) at ../drivers/serial/serial-uclass.c:187 #2 0xbff736a8 in _serial_puts (str=0xbedf0a05 "nitcall: 00017180 (relocated to bff48180)\n", dev=0x401fe180) at ../drivers/serial/serial-uclass.c:194 #3 serial_puts (str=<optimized out>) at ../drivers/serial/serial-uclass.c:271 #4 0xbffb0e30 in printf (fmt=0xbffd0c6a "%s%s") at ../lib/vsprintf.c:805 #5 0xbff58f24 in log_console_emit (ldev=<optimized out>, rec=0xbedf0c44) at ../common/log_console.c:39 #6 0xbff58cc4 in log_dispatch (rec=0xbedf0c3c) at ../common/log.c:218 #7 _log (cat=LOGC_NONE, level=LOGL_DEBUG, file=<optimized out>, line=<optimized out>, func=0xbffbcdb1 "initcall_run_list", fmt=0xbffc0ef3 "initcall: %p (relocated to %p)\n") at ../common/log.c:252 #8 0xbff48388 in initcall_run_list (init_sequence=0xbffe03a0) at ../include/initcall.h:39 #9 board_init_r (new_gd=<optimized out>, dest_addr=<optimized out>) at ../common/board_r.c:928 #10 0xbff327cc in ?? () at ../arch/arm/lib/crt0.S:167

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[PATCH] sunxi: support boot console on uart1 for sun8i
by Tobias Schramm 14 Feb '21

14 Feb '21

From: Tobias Schramm <t.schramm(a)manjaro.org> This commit adds support for using uart1 as boot console on sun8i. Signed-off-by: Tobias Schramm <t.schramm(a)manjaro.org> --- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/board.c | 4 ++++ include/configs/sunxi-common.h | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index de77bf638e..2969a530ae 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -190,6 +190,7 @@ enum sunxi_gpio_number { #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 +#define SUN8I_GPG_UART1 2 #define SUN6I_GPG_TWI3 2 #define SUN5I_GPG_UART1 4 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index ae6bc656d9..febec0ae03 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -144,6 +144,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPL(7), SUNXI_GPIO_PULL_UP); #else #error Unsupported console port number. Please fix pin mux settings in board.c #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 000f386470..19f0026888 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -251,6 +251,8 @@ extern int soft_i2c_gpio_scl; #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) #define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) +#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" #else #error Unsupported console port nr. Please fix stdout-path in sunxi-common.h. #endif -- 2.30.0

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[PATCHv5 1/6] common: SCP03 control (enable and provision of keys)
by Jorge Ramirez-Ortiz 13 Feb '21

13 Feb '21

This Trusted Application allows enabling SCP03 as well as provisioning the keys on TEE controlled secure element (ie, NXP SE050). All the information flowing on buses (ie I2C) between the processor and the secure element must be encrypted. Secure elements are pre-provisioned with a set of keys known to the user so that the secure channel protocol (encryption) can be enforced on the first boot. This situation is however unsafe since the keys are publically available. For example, in the case of the NXP SE050, these keys would be available in the OP-TEE source tree [2] and of course in the documentation corresponding to the part. To address that, users are required to rotate/provision those keys (ie, generate new keys and write them in the secure element's persistent memory). For information on SCP03, check the Global Platform HomePage and google for that term [1] [1] globalplatform.org [2] https://github.com/OP-TEE/optee_os/ check: core/drivers/crypto/se050/adaptors/utils/scp_config.c Signed-off-by: Jorge Ramirez-Ortiz <jorge(a)foundries.io> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- common/Kconfig | 8 ++++++ common/Makefile | 1 + common/scp03.c | 53 ++++++++++++++++++++++++++++++++++++ include/scp03.h | 21 ++++++++++++++ include/tee/optee_ta_scp03.h | 21 ++++++++++++++ 5 files changed, 104 insertions(+) create mode 100644 common/scp03.c create mode 100644 include/scp03.h create mode 100644 include/tee/optee_ta_scp03.h diff --git a/common/Kconfig b/common/Kconfig index 2bb3798f80..482f123534 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -588,6 +588,14 @@ config AVB_BUF_SIZE endif # AVB_VERIFY +config SCP03 + bool "Build SCP03 - Secure Channel Protocol O3 - controls" + depends on OPTEE || SANDBOX + depends on TEE + help + This option allows U-Boot to enable and or provision SCP03 on an OPTEE + controlled Secured Element. + config SPL_HASH bool # "Support hashing API (SHA1, SHA256, etc.)" help diff --git a/common/Makefile b/common/Makefile index daeea67cf2..215b8b26fd 100644 --- a/common/Makefile +++ b/common/Makefile @@ -137,3 +137,4 @@ obj-$(CONFIG_CMD_LOADB) += xyzModem.o obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_AVB_VERIFY) += avb_verify.o +obj-$(CONFIG_SCP03) += scp03.o diff --git a/common/scp03.c b/common/scp03.c new file mode 100644 index 0000000000..09ef7b5ba3 --- /dev/null +++ b/common/scp03.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021, Foundries.IO + * + */ + +#include <common.h> +#include <scp03.h> +#include <tee.h> +#include <tee/optee_ta_scp03.h> + +static int scp03_enable(bool provision) +{ + const struct tee_optee_ta_uuid uuid = PTA_SCP03_UUID; + struct tee_open_session_arg session; + struct tee_invoke_arg invoke; + struct tee_param param; + struct udevice *tee = NULL; + + tee = tee_find_device(tee, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&session, 0, sizeof(session)); + tee_optee_ta_uuid_to_octets(session.uuid, &uuid); + if (tee_open_session(tee, &session, 0, NULL)) + return -ENXIO; + + memset(&param, 0, sizeof(param)); + param.attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT; + param.u.value.a = provision; + + memset(&invoke, 0, sizeof(invoke)); + invoke.func = PTA_CMD_ENABLE_SCP03; + invoke.session = session.session; + + if (tee_invoke_func(tee, &invoke, 1, &param)) + return -EIO; + + tee_close_session(tee, session.session); + + return 0; +} + +int tee_enable_scp03(void) +{ + return scp03_enable(false); +} + +int tee_provision_scp03(void) +{ + return scp03_enable(true); +} diff --git a/include/scp03.h b/include/scp03.h new file mode 100644 index 0000000000..729667ccd1 --- /dev/null +++ b/include/scp03.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021, Foundries.IO + * + */ + +#ifndef _SCP03_H +#define _SCP03_H + +/* + * Requests to OPTEE to enable or provision the Secure Channel Protocol on its + * Secure Element + * + * If key provisioning is requested, OPTEE shall generate new SCP03 keys and + * write them to the Secure Element. + * + * Both functions return < 0 on error else 0. + */ +int tee_enable_scp03(void); +int tee_provision_scp03(void); +#endif /* _SCP03_H */ diff --git a/include/tee/optee_ta_scp03.h b/include/tee/optee_ta_scp03.h new file mode 100644 index 0000000000..13f9956d98 --- /dev/null +++ b/include/tee/optee_ta_scp03.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * (C) Copyright 2021, Foundries.IO + * + */ +#ifndef __TA_SCP03_H +#define __TA_SCP03_H + +#define PTA_SCP03_UUID { 0xbe0e5821, 0xe718, 0x4f77, \ + { 0xab, 0x3e, 0x8e, 0x6c, 0x73, 0xa9, 0xc7, 0x35 } } + +/* + * Enable Secure Channel Protocol functionality (SCP03) on the Secure Element. + * Setting the operation value to something different than NULL will trigger + * the SCP03 provisioning request. + * + * in params[0].a = operation + */ +#define PTA_CMD_ENABLE_SCP03 0 + +#endif /*__TA_SCP03_H*/ -- 2.30.0

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[PATCH 1/1] buildman: 'Thread' object has no attribute 'isAlive'
by Heinrich Schuchardt 13 Feb '21

13 Feb '21

The isAlive() method was deprecated in Python 3.8 and has been removed in Python 3.9. See https://bugs.python.org/issue37804. Use is_alive() instead. Since Python 2.6 is_alive() has been a synonym for isAlive(). So there should be no problems for users using elder Python 3 versions. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- tools/buildman/builder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index c93946842a..6f6d759329 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -1691,7 +1691,7 @@ class Builder: term = threading.Thread(target=self.queue.join) term.setDaemon(True) term.start() - while term.isAlive(): + while term.is_alive(): term.join(100) # Wait until we have processed all output -- 2.30.0

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[GIT] Pull request: u-boot-dfu (12.02.2021)
by Lukasz Majewski 12 Feb '21

12 Feb '21

Dear Marek, Please find this PR with fastboot improvement code rebased on top of u-boot-denx-usb tree. CI: https://dev.azure.com/lukma633/U-Boot/_build/results?buildId=28&view=results (There shall be at least one follow up PR with work done by Sean). Merge tag data/information: https://gitlab.denx.de/u-boot/custodians/u-boot-dfu/-/tags/u-boot-dfu-12Feb… The following changes since commit db8fb2ffc4f3f63b9005f676ab3879a06de6cdda: usb: dwc2: change compatible st,stm32mp1-hsotg to st,stm32mp15-hsotg (2021-02-10 22:23:35 +0100) are available in the Git repository at: u-boot-dfu/master for you to fetch changes up to a7d1b66d65972965ffbf002277bac99b0e290aee: fastboot: add UUU command UCmd and ACmd support (2021-02-11 22:54:11 +0100) ---------------------------------------------------------------- Heiko Schocher (1): fastboot: add UUU command UCmd and ACmd support Sean Anderson (10): mmc: sandbox: Add support for writing test: dm: Add test for fastboot mmc partition naming part: Give several functions more useful return values part: Support getting whole disk from part_get_info_by_dev_and_name_or_num part: Support string block devices in part_get_info_by_dev_and_name fastboot: Remove mmcpart argument from raw_part_get_info_by_name fastboot: Move part_get_info_by_name_or_alias after raw_part_get_info_by_name fastboot: Allow u-boot-style partitions doc: Rename k210 partitions anchor doc: Document partition specifications Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma(a)denx.de

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