February 2021 - U-Boot

[PATCH 0/4] arm: mvebu: turris_mox: Fix and enable PCIe devices
by Pali Rohár 26 Feb '21

26 Feb '21

This patch series fix PCIe on Armada 3720 and enable PCIe devices (USB and NVMe) on Turris MOX. Marek Behún (1): arm: mvebu: turris_mox: Enable NVMe support Pali Rohár (3): arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytes arm: mvebu: turris_mox: Enable CONFIG_PCI_PNP arm: mvebu: turris_mox: Enable CONFIG_USB_XHCI_PCI configs/turris_mox_defconfig | 3 ++- drivers/pci/pci-aardvark.c | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.20.1

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[PATCH 1/2] rng: iproc_rng200: Enable support for RPi4 armv7
by matthias.bgg＠kernel.org 26 Feb '21

26 Feb '21

From: Matthias Brugger <mbrugger(a)suse.com> On the RPi4 armv7 build we have the situationt that we use physical addresses of 64 bit, while the virtual addresses are 32 bit. Remap the base address in this scenario via map_physmem(). Signed-off-by: Matthias Brugger <mbrugger(a)suse.com> --- drivers/rng/iproc_rng200.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/rng/iproc_rng200.c b/drivers/rng/iproc_rng200.c index 1126bbd797..85ac15bf9c 100644 --- a/drivers/rng/iproc_rng200.c +++ b/drivers/rng/iproc_rng200.c @@ -34,12 +34,12 @@ #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF struct iproc_rng200_plat { - fdt_addr_t base; + void __iomem *base; }; static void iproc_rng200_enable(struct iproc_rng200_plat *pdata, bool enable) { - fdt_addr_t rng_base = pdata->base; + void __iomem *rng_base = pdata->base; u32 val; val = readl(rng_base + RNG_CTRL_OFFSET); @@ -54,7 +54,7 @@ static void iproc_rng200_enable(struct iproc_rng200_plat *pdata, bool enable) static void iproc_rng200_restart(struct iproc_rng200_plat *pdata) { - fdt_addr_t rng_base = pdata->base; + void __iomem *rng_base = pdata->base; u32 val; iproc_rng200_enable(pdata, false); @@ -156,7 +156,7 @@ static int iproc_rng200_of_to_plat(struct udevice *dev) { struct iproc_rng200_plat *pdata = dev_get_plat(dev); - pdata->base = dev_read_addr(dev); + pdata->base = devfdt_map_physmem(dev, sizeof(void *)); if (!pdata->base) return -ENODEV; -- 2.30.0

1 1

[PATCH v1 4/7] write WPEN bit for SST26* devices when locking
by Bernhard Kirchen 26 Feb '21

26 Feb '21

"sf protect lock" did only protect against accidental writes by software. it did not lock down the config or block-protection registers if the WP# pin was deasserted. hardware write protection was never enabled for these devices. this change implements setting the WPEN bit and clearing the IOC bit in SST26* devices' config register if any block is protected by "sf protect lock" command, thus enabling hardware write protection. this behavior is similar to the "sf protect lock" implementation for Micron (and compatible) chips. Signed-off-by: Bernhard Kirchen <bernhard.kirchen(a)mbconnectline.com> --- drivers/mtd/spi/spi-nor-core.c | 64 ++++++++++++++++++++++++++++++++-- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 050aeac3fa..10c01cf20e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -185,7 +185,9 @@ static int read_fsr(struct spi_nor *nor) * location. Return the configuration register value. * Returns negative if error occurred. */ -#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +#if defined(CONFIG_SPI_FLASH_SPANSION) || \ + defined(CONFIG_SPI_FLASH_WINBOND) || \ + defined(CONFIG_SPI_FLASH_SST) static int read_cr(struct spi_nor *nor) { int ret; @@ -972,6 +974,8 @@ read_err: #define SST26_MAX_BPR_REG_LEN (18 + 1) #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K) +static int write_cr(struct spi_nor *nor, u8 value); + enum lock_ctl { SST26_CTL_LOCK, SST26_CTL_UNLOCK, @@ -994,6 +998,35 @@ static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) return false; } +static int sst26_hardware_write_protection(struct spi_nor *nor, bool lock) +{ + int ret; + u8 cr_val; + + cr_val = read_cr(nor); + if (cr_val < 0) { + dev_err(nor->dev, "fail to read config register value\n"); + return cr_val; + } + + cr_val &= ~CR_WPEN; + + if (lock) { + // disallow further writes if WP# pin is not asserted. + cr_val |= CR_WPEN; + // force quad SPI disabled as otherwise WP# pin works as data line. + cr_val &= ~CR_QUAD_EN_SPAN; + } + + ret = write_cr(nor, cr_val); + if (ret < 0) { + dev_err(nor->dev, "fail to configure WP# pin (hardware write protection)\n"); + return ret; + } + + return 0; +} + /* * Lock, unlock or check lock status of the flash region of the flash (depending * on the lock_ctl value) @@ -1101,6 +1134,14 @@ static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lo return ret; } + // enable hardware write protection iff any protection bit is set + for (i = 0; i < bpr_size; ++i) + if (bpr_buff[i] != 0) + break; + ret = sst26_hardware_write_protection(nor, i < bpr_size); + if (ret < 0) + return ret; + // ignore return value. even if write disable failed, the actual task // (write block protecton register) was completed successfully. write_disable(nor); @@ -1339,7 +1380,9 @@ static int macronix_quad_enable(struct spi_nor *nor) } #endif -#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +#if defined(CONFIG_SPI_FLASH_SPANSION) || \ + defined(CONFIG_SPI_FLASH_WINBOND) || \ + defined(CONFIG_SPI_FLASH_SST) /* * Write status Register and configuration register with 2 bytes * The first byte will be written to the status register, while the @@ -1369,6 +1412,23 @@ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) return 0; } +static int write_cr(struct spi_nor *nor, u8 value) +{ + int ret; + u8 sr_cr[2]; + + ret = read_sr(nor); + if (ret < 0) + return ret; + + sr_cr[0] = ret; + sr_cr[1] = value; + + return write_sr_cr(nor, sr_cr); +} +#endif + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /** * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. * @nor: pointer to a 'struct spi_nor' diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 4a8e19ee4f..ee5a59cf0a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -151,6 +151,7 @@ /* Configuration Register bits. */ #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ +#define CR_WPEN BIT(7) /* SST26* Write-Protection Pin (WP#) Enable */ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) -- 2.29.2

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[PATCH 1/2] spi: nxp_fspi: Fix error reporting
by Adam Ford 26 Feb '21

26 Feb '21

On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the rate the clock was able to set. When checking for errors, it only checks that it is not NULL. Since positive numbers are not errors, only check for negative numbers when handling errors. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 006dd04b9e..d74561578a 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -815,7 +815,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) /* the default frequency, we will change it later if necessary. */ ret = clk_set_rate(&f->clk, 20000000); - if (ret) + if (ret < 0) return ret; ret = nxp_fspi_clk_prep_enable(f); @@ -906,7 +906,7 @@ static int nxp_fspi_set_speed(struct udevice *bus, uint speed) nxp_fspi_clk_disable_unprep(f); ret = clk_set_rate(&f->clk, speed); - if (ret) + if (ret < 0) return ret; ret = nxp_fspi_clk_prep_enable(f); -- 2.25.1

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[PATCH] cmd: mmc: check whether bootbus's arguments is valid or not
by Jaehoon Chung 26 Feb '21

26 Feb '21

According to Specification, each bit have valid value. But it doesn't check whether arguments is valid or not. It has potential bug with arguments passed by wrong value. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- cmd/mmc.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index cb6b59f36a43..f9cb3fc21da0 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -735,8 +735,45 @@ static int do_mmc_bootbus(struct cmd_tbl *cmdtp, int flag, return CMD_RET_FAILURE; } + /* + * BOOT_BUS_CONDITIONS[177] + * BOOT_MODE[4:3] + * 0x0 : Use SDR + Backward compatible timing in boot operation + * 0x1 : Use SDR + High Speed Timing in boot operation mode + * 0x2 : Use DDR in boot operation + * RESET_BOOT_BUS_CONDITIONS + * 0x0 : Reset bus width to x1, SDR, Backward compatible + * 0x1 : Retain BOOT_BUS_WIDTH and BOOT_MODE + * BOOT_BUS_WIDTH + * 0x0 : x1(sdr) or x4 (ddr) buswidth + * 0x1 : x4(sdr/ddr) buswith + * 0x2 : x8(sdr/ddr) buswith + * + */ + if (width >= 0x3) { + printf("boot_bus_width %d is invalid\n", width); + return CMD_RET_FAILURE; + } + + if (reset >= 0x2) { + printf("reset_boot_bus_width %d is invalid\n", reset); + return CMD_RET_FAILURE; + } + + if (mode >= 0x3) { + printf("reset_boot_bus_width %d is invalid\n", mode); + return CMD_RET_FAILURE; + } + /* acknowledge to be sent during boot operation */ - return mmc_set_boot_bus_width(mmc, width, reset, mode); + if (mmc_set_boot_bus_width(mmc, width, reset, mode)) { + puts("BOOT_BUS_WIDTH is failed to change.\n"); + return CMD_RET_FAILURE; + } + + printf("Set to BOOT_BUS_WIDTH = 0x%x, RESET = 0x%x, BOOT_MODE = 0x%x\n", + width, reset, mode); + return CMD_RET_SUCCESS; } static int do_mmc_boot_resize(struct cmd_tbl *cmdtp, int flag, -- 2.29.0

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[PATCH u-boot-marvell 1/4] rtc: add armada38x driver
by Marek Behún 26 Feb '21

26 Feb '21

Add RTC driver for Armada 38x, based on Linux' driver. For now implement only `marvell,armada-380-rtc` compatible. Signed-off-by: Marek Behún <marek.behun(a)nic.cz> Cc: Pali Rohár <pali(a)kernel.org> Cc: Stefan Roese <sr(a)denx.de> Cc: Baruch Siach <baruch(a)tkos.co.il> Cc: Chris Packham <judge.packham(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/rtc/Kconfig | 7 ++ drivers/rtc/Makefile | 1 + drivers/rtc/armada38x.c | 185 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/rtc/armada38x.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index aa6d90158c..dafba35279 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -38,6 +38,13 @@ config RTC_ENABLE_32KHZ_OUTPUT Some real-time clocks support the output of 32kHz square waves (such as ds3231), the config symbol choose Real Time Clock device 32Khz output feature. +config RTC_ARMADA38X + bool "Enable Armada 38x Marvell SoC RTC" + depends on DM_RTC && ARCH_MVEBU + help + This adds support for the in-chip RTC that can be found in the + Armada 38x Marvell's SoC devices. + config RTC_PCF2127 bool "Enable PCF2127 driver" depends on DM_RTC diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 6a45a9c874..15609e7b18 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_RTC) += rtc-uclass.o obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-y += rtc-lib.o +obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o obj-$(CONFIG_RTC_DS1302) += ds1302.o obj-$(CONFIG_RTC_DS1306) += ds1306.o diff --git a/drivers/rtc/armada38x.c b/drivers/rtc/armada38x.c new file mode 100644 index 0000000000..88dc9977c6 --- /dev/null +++ b/drivers/rtc/armada38x.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RTC driver for the Armada 38x Marvell SoCs + * + * Copyright (C) 2021 Marek Behun <marek.behun(a)nic.cz> + * + * Based on Linux' driver by Gregory Clement and Marvell + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <linux/delay.h> +#include <rtc.h> + +#define RTC_STATUS 0x0 +#define RTC_TIME 0xC +#define RTC_CONF_TEST 0x1C + +/* Armada38x SoC registers */ +#define RTC_38X_BRIDGE_TIMING_CTL 0x0 +#define RTC_38X_PERIOD_OFFS 0 +#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS) +#define RTC_38X_READ_DELAY_OFFS 26 +#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS) + +#define SAMPLE_NR 100 + +struct armada38x_rtc { + void __iomem *regs; + void __iomem *regs_soc; +}; + +/* + * According to Erratum RES-3124064 we have to do some configuration in MBUS. + * To read an RTC register we need to read it 100 times and return the most + * frequent value. + * To write an RTC register we need to write 2x zero into STATUS register, + * followed by the proper write. Linux adds an 5 us delay after this, so we do + * it here as well. + */ +static void update_38x_mbus_timing_params(struct armada38x_rtc *rtc) +{ + u32 reg; + + reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); + reg &= ~RTC_38X_PERIOD_MASK; + reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */ + reg &= ~RTC_38X_READ_DELAY_MASK; + reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */ + writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); +} + +static void armada38x_rtc_write(u32 val, struct armada38x_rtc *rtc, u8 reg) +{ + writel(0, rtc->regs + RTC_STATUS); + writel(0, rtc->regs + RTC_STATUS); + writel(val, rtc->regs + reg); + udelay(5); +} + +static u32 armada38x_rtc_read(struct armada38x_rtc *rtc, u8 reg) +{ + u8 counts[SAMPLE_NR], max_idx; + u32 samples[SAMPLE_NR], max; + int i, j, last; + + for (i = 0, last = 0; i < SAMPLE_NR; ++i) { + u32 sample = readl(rtc->regs + reg); + + /* find if this value was already read */ + for (j = 0; j < last; ++j) { + if (samples[j] == sample) + break; + } + + if (j < last) { + /* if yes, increment count */ + ++counts[j]; + } else { + /* if not, add */ + samples[last] = sample; + counts[last] = 1; + ++last; + } + } + + /* finally find the sample that was read the most */ + max = 0; + max_idx = 0; + + for (i = 0; i < last; ++i) { + if (counts[i] > max) { + max = counts[i]; + max_idx = i; + } + } + + return samples[max_idx]; +} + +static int armada38x_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + u32 time; + + time = armada38x_rtc_read(rtc, RTC_TIME); + + rtc_to_tm(time, tm); + + return 0; +} + +static int armada38x_rtc_reset(struct udevice *dev) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + u32 reg; + + reg = armada38x_rtc_read(rtc, RTC_CONF_TEST); + + if (reg & 0xff) { + armada38x_rtc_write(0, rtc, RTC_CONF_TEST); + mdelay(500); + armada38x_rtc_write(0, rtc, RTC_TIME); + armada38x_rtc_write(BIT(0) | BIT(1), 0, RTC_STATUS); + } + + return 0; +} + +static int armada38x_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + unsigned long time; + + time = rtc_mktime(tm); + + if (time > U32_MAX) + printf("%s: requested time to set will overflow\n", dev->name); + + armada38x_rtc_reset(dev); + armada38x_rtc_write(time, rtc, RTC_TIME); + + return 0; +} + +static int armada38x_probe(struct udevice *dev) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + + rtc->regs = dev_remap_addr_name(dev, "rtc"); + if (!rtc->regs) + goto err; + + rtc->regs_soc = dev_remap_addr_name(dev, "rtc-soc"); + if (!rtc->regs_soc) + goto err; + + update_38x_mbus_timing_params(rtc); + + return 0; +err: + printf("%s: io address missing\n", dev->name); + return -ENODEV; +} + +static const struct rtc_ops armada38x_rtc_ops = { + .get = armada38x_rtc_get, + .set = armada38x_rtc_set, + .reset = armada38x_rtc_reset, +}; + +static const struct udevice_id armada38x_rtc_ids[] = { + { .compatible = "marvell,armada-380-rtc", .data = 0 }, + { } +}; + +U_BOOT_DRIVER(rtc_armada38x) = { + .name = "rtc-armada38x", + .id = UCLASS_RTC, + .of_match = armada38x_rtc_ids, + .probe = armada38x_probe, + .priv_auto = sizeof(struct armada38x_rtc), + .ops = &armada38x_rtc_ops, +}; -- 2.26.2

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[PATCH v1 3/7] SST26* locking: need to enable write
by Bernhard Kirchen 26 Feb '21

26 Feb '21

prior to using the WBPR (write block protection register) command to write new block protection register values, the WREN command must be sent. otherwise the new values are not applied. Signed-off-by: Bernhard Kirchen <bernhard.kirchen(a)mbconnectline.com> --- drivers/mtd/spi/spi-nor-core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e16b0e1462..050aeac3fa 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1091,12 +1091,20 @@ static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lo if (ctl == SST26_CTL_CHECK) return 0; + ret = write_enable(nor); + if (ret < 0) + return ret; + ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size); if (ret < 0) { dev_err(nor->dev, "fail to write block-protection register\n"); return ret; } + // ignore return value. even if write disable failed, the actual task + // (write block protecton register) was completed successfully. + write_disable(nor); + return 0; } -- 2.29.2

2 1

[PATCH v1 0/7] fix and improve Micron/SST26* SPI NOR protection handling
by Bernhard Kirchen 26 Feb '21

26 Feb '21

these patches improve the existing SPI NOR flash protection features by enabling hardware write protection where applicable, by fixing bugs, and by providing more information on the status of protection. this shall make using the protection feature more user-friendly and help meeting user expectations. Bernhard Kirchen (7): command sf: help text format sf protect: warn about failed (un)lock operation SST26* locking: need to enable write write WPEN bit for SST26* devices when locking sf protect (un)lock for SST26*: test BPR values fix sst26_process_bpr check provide "sf protect check" command cmd/sf.c | 74 ++++++++----- drivers/mtd/spi/spi-nor-core.c | 186 ++++++++++++++++++++++++++++----- include/linux/mtd/spi-nor.h | 18 +++- include/spi_flash.h | 8 ++ 4 files changed, 232 insertions(+), 54 deletions(-) -- 2.29.2

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[PATCH 0/1] Add flash protection support for Winbond's w25q128
by Su Baocheng 26 Feb '21

26 Feb '21

From: Su Baocheng <baocheng_su(a)siemens.com> According to datasheets, all 3 types of w25q128 support ST Micro-like flash protection that using BP{0-2}/TB bits in status register. Su Baocheng (1): mtd: spi-nor-ids: Add support of flash protection to w25q128 drivers/mtd/spi/spi-nor-ids.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.25.1

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[PATCH] mtd: spi-nor.h: Change spaces to tabs
by Bin Meng 26 Feb '21

26 Feb '21

U-Boot coding convention prefers tabs over spaces. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- include/linux/mtd/spi-nor.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 233fdc341a..988c1bd0c1 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -48,13 +48,13 @@ #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ -#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ -#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ +#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */ +#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */ #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ -#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ -#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ +#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */ +#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ @@ -75,13 +75,13 @@ #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ -#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ -#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ +#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */ +#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */ #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */ -#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ -#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ +#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */ +#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */ #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */ #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ @@ -122,8 +122,8 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ /* Used for Micron flashes only. */ -#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ -#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ +#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ +#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ -- 2.25.1

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