February 2021 - U-Boot

[PATCH] ARM: stm32: Add USB host boot support
by Marek Vasut 26 Feb '21

26 Feb '21

Add support for booting from USB pen drive, since USB host port is available on the STM32MP1. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- include/configs/stm32mp1.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index c5539285af1..36e400453ea 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -102,11 +102,18 @@ #define BOOT_TARGET_UBIFS(func) #endif +#ifdef CONFIG_USB +#define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_USB(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC1(func) \ BOOT_TARGET_UBIFS(func) \ BOOT_TARGET_MMC0(func) \ BOOT_TARGET_MMC2(func) \ + BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) /* -- 2.30.0

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[PATCH v2] usb: gadget: dwc2_udc_otg: Fix dwc2_gadget_start() and usb_gadget_register_driver()
by Patrice Chotard 26 Feb '21

26 Feb '21

Since commit 8745b9ebccae ("usb: gadget: add super speed support") ums was no more functional on platform which use dwc2_udc_otg driver. This was due to a too restrictive test which checked that the gadget driver speed was either FS or HS. So all gadget driver with max speed set to speed higher than HS (SS in case of composite gadget driver in our case) are not allowed, which is wrong. Update the speed test in usb_gadget_register_driver() and in dwc2_gadget_start() to allow all gadget driver speed equal or higher than FS. Tested on stm32mp157c-ev1 board. Fixes: c791c8431c34 ("usb: dwc2: convert driver to DM_USB_GADGET") Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- Changes in v2: - update gadget driver speed test in usb_gadget_register_driver() and in dwc2_gadget_start() instead of removing it completely. drivers/usb/gadget/dwc2_udc_otg.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index ecac80fc11..2f31814442 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -248,9 +248,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name"); - if (!driver - || (driver->speed != USB_SPEED_FULL - && driver->speed != USB_SPEED_HIGH) + if (!driver || driver->speed < USB_SPEED_FULL || !driver->bind || !driver->disconnect || !driver->setup) return -EINVAL; if (!dev) @@ -320,9 +318,7 @@ static int dwc2_gadget_start(struct usb_gadget *g, debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name"); - if (!driver || - (driver->speed != USB_SPEED_FULL && - driver->speed != USB_SPEED_HIGH) || + if (!driver || driver->speed < USB_SPEED_FULL || !driver->bind || !driver->disconnect || !driver->setup) return -EINVAL; -- 2.17.1

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[PATCH] serial: ns16550: Correct the base address type
by Bin Meng 26 Feb '21

26 Feb '21

Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce62190b7 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/serial/ns16550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 65c6db0..da903c1 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -482,7 +482,7 @@ static int ns16550_serial_getinfo(struct udevice *dev, return 0; } -static int ns16550_serial_assign_base(struct ns16550_plat *plat, ulong base) +static int ns16550_serial_assign_base(struct ns16550_plat *plat, fdt_addr_t base) { if (base == FDT_ADDR_T_NONE) return -EINVAL; -- 2.7.4

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[PATCH] spi: Update speed/mode on change
by Marek Vasut 26 Feb '21

26 Feb '21

The spi_get_bus_and_cs() may be called on the same bus and chipselect with different frequency or mode. This is valid usecase, but the code fails to notify the controller of such a configuration change. Call spi_set_speed_mode() in case bus frequency or bus mode changed to let the controller update the configuration. The problem can easily be triggered using the sspi command: => sspi 0:0@1000 => sspi 0:0@2000 Without this patch, both transfers happen at 1000 Hz. With this patch, the later transfer happens correctly at 2000 Hz. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Patrick Delaunay <patrick.delaunay(a)st.com> --- drivers/spi/spi-uclass.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 7155d4aebd6..96c9a83e761 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -405,12 +405,22 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, goto err; } + /* In case bus frequency or mode changed, update it. */ + if ((speed && slave->speed && slave->speed != speed) || + (plat->mode != mode)) { + ret = spi_set_speed_mode(bus, speed, mode); + if (ret) + goto err_speed_mode; + } + *busp = bus; *devp = slave; log_debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp); return 0; +err_speed_mode: + spi_claim_bus(slave); err: log_debug("%s: Error path, created=%d, device '%s'\n", __func__, created, dev->name); -- 2.30.0

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[PATCH 0/2] pinctrl: at91-pio4: add support for slew-rate
by Claudiu Beznea 26 Feb '21

26 Feb '21

Hi, This series adds support for slew rate on AT91 PIO4 driver. The support is enabled on SAMA7G5. Thank you, Claudiu Beznea Claudiu Beznea (2): dt-bindings: pinctrl: at91-pio4: add slew-rate pinctrl: at91-pio4: add support for slew-rate arch/arm/mach-at91/include/mach/atmel_pio4.h | 1 + .../pinctrl/atmel,at91-pio4-pinctrl.txt | 7 +++--- drivers/pinctrl/pinctrl-at91-pio4.c | 26 +++++++++++++++++++--- 3 files changed, 28 insertions(+), 6 deletions(-) -- 2.7.4

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[PATCH] configs: stm32mp1: enable uefi related commands
by Ilias Apalodimas 26 Feb '21

26 Feb '21

The board can boot with UEFI. With the latest changes in U-Boot's EFI subsystem we also have support for EFI runtime variables, without SetVariable support. We can also store the EFI variables in a file on the ESP partition and preserve them across reboots. The env and efidebug commands are missing in order to configure EFI variables and the efibootmgr though. Since U-Boot's default config enables other EFI related commands (e.g bootefi), let's add the env related and efidebug commands and allow users to do that Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- configs/stm32mp15_trusted_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index da31b74cdeb6..107041119f1d 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PROMPT="STM32MP> " CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_ADC=y @@ -32,6 +33,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y @@ -144,4 +146,5 @@ CONFIG_BMP_32BPP=y CONFIG_WDT=y CONFIG_WDT_STM32MP=y CONFIG_ERRNO_STR=y +# CONFIG_HEXDUMP is not set CONFIG_FDT_FIXUP_PARTITIONS=y -- 2.30.1

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[PATCH u-boot-marvell v2 00/18] Upgrade A38x DDR3 training to version 14.0.0
by Marek Behún 26 Feb '21

26 Feb '21

Hi Stefan, this is v2 of series that syncs drivers/ddr/marvell/a38x/ with the mv-ddr-devel branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. I have tested how the SPL image increases for all a38x boards. Here are sizes of spl/u-boot-spl.bin before applying this series (in bytes, hexadecimal), by how much these files are increased after applying this series (in bytes, decimal). before inc ------ --- clearfog 0x1f9c9 28 controlcenterdc 0x2263c 108 db-88f6820-amc 0x241d0 108 SPL too big (before and after) db-88f6820-gp 0x23c14 108 helios4 0x1f68d 28 turris_omnia 0x1c932 36 x530 0x249ed 108 SPL too big (before and after) As can be seen, these patches do not increase the size of SPL much, and the only boards where SPL is too big after the series have the same problem even before applying this series. For these boards I recommend increasing in include/configs/*.h CONFIG_SPL_SIZE from (140 << 10) to (160 << 10) and in configs/*_defconfig CONFIG_SYS_SPI_U_BOOT_OFFS from 0x24000 to 0x29000 Changes from v1: - original author names are now in the From headers - added Chris' Tested-by Marek Alex Leibovich (2): ddr: marvell: a38x: add ddr32 support ddr: marvell: a38x: add ddr 32bit ECC support Baruch Siach (1): ddr: marvell: a38x: allow board specific ODT configuration Marek Behún (7): ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import header change from upstream ddr: marvell: a38x: import code change from upstream ddr: marvell: a38x: bump version to 14.0.0 ddr: marvell: a38x: fix comment in conditional macro Moti Buskila (7): ddr: marvell: a38x: fix write leveling suplementary algo ddr: marvell: a38x: fix 32bit ddr: marvell: a38x: fix memory size calculation using 32bit bus width ddr: marvell: a38x: add 16Gbit memory devices support ddr: marvell: a38x: add support for twin-die combined memory device ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit ddr: marvell: a38x: fix memory cs size function heaterC (1): ddr: marvell: a38x: enum mv_ddr_twin_die: change order board/CZ.NIC/turris_omnia/turris_omnia.c | 2 ++ board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 1 + board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 1 + board/alliedtelesis/x530/x530.c | 1 + board/gdsys/a38x/controlcenterdc.c | 1 + board/kobol/helios4/helios4.c | 1 + board/solidrun/clearfog/clearfog.c | 1 + drivers/ddr/marvell/a38x/ddr3_init.c | 5 ++++ drivers/ddr/marvell/a38x/ddr3_training.c | 5 +++- drivers/ddr/marvell/a38x/ddr3_training_db.c | 3 +++ .../ddr/marvell/a38x/ddr3_training_ip_def.h | 2 ++ .../marvell/a38x/ddr3_training_ip_engine.c | 5 +++- drivers/ddr/marvell/a38x/ddr_topology_def.h | 23 ++++++++++++++++++- .../ddr/marvell/a38x/mv_ddr_build_message.c | 2 +- drivers/ddr/marvell/a38x/mv_ddr_plat.c | 9 ++++++-- drivers/ddr/marvell/a38x/mv_ddr_topology.c | 14 ++++++++--- drivers/ddr/marvell/a38x/mv_ddr_topology.h | 2 ++ drivers/ddr/marvell/a38x/xor.c | 6 ++--- 18 files changed, 72 insertions(+), 12 deletions(-) -- 2.26.2

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[RFC PATCH] doc: mmc man-page
by Jaehoon Chung 26 Feb '21

26 Feb '21

Provide a man-pages for the mmc command. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- doc/usage/mmc.rst | 149 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100644 doc/usage/mmc.rst diff --git a/doc/usage/mmc.rst b/doc/usage/mmc.rst new file mode 100644 index 000000000000..30fee447d409 --- /dev/null +++ b/doc/usage/mmc.rst @@ -0,0 +1,149 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +mmc command +============ + +Synopsis +-------- + +:: + + mmc info + mmc read addr blk# cnt + mmc write addr blk# cnt + mmc erase blk# cnt + mmc rescan + mmc part + mmc dev [dev] [part] + mmc list + mmc wp + mmc bootbus <dev> <boot_bus_width> <reset_boot_bus_width> <boot_mode> + mmc bootpart-resize <dev> <dev part size MB> <RPMB part size MB> + mmc partconf <dev> [boot_ack boot_partition partition_access] + mmc rst-function <dev> <value> + +Description +----------- + +The mmc command is used to control MMC(eMMC/SD) device + +The *mmc info* displays information (Manufacturer ID, OEM, Name, Bus Speed, Mode, ...) of MMC device + +The *mmc read* command reads raw data to memory address from MMC device with block offset and count + +The *mmc write* write raw data to MMC device from memory address with block offset and count + addr - memory address + + blk# - start block offset + + cnt - block count + +The *mmc erase* erases MMC device from block offset until count + blk# - start block offset + + cnt - block count + +The *mmc rescan* scans the available MMC device + +The *mmc part* displays the list available partition on current mmc device + +The *mmc dev* show or set current mmc device + [dev] + device number to change + [part] + partition number to change + +The *mmc list* displays the list avaiable devices + +The *mmc wp* enables "power on write protect" function about boot partitions + +The *mmc bootbus* sets the BOOT_BUS_WIDTH feild + BOOTU_BUS_WIDTH[177] is one of EXT_CSD register. (*Refer to eMMC specification*) + +The *mmc-bootpart-resize* changes sizes of boot and RPMB partition + dev - device number + + boot part size MB - Size to change boot partition + + RPMB part size MB - Size to chagne RPMB partition + +The *mmc rst-function* change the RST_n_FUNCTION filed + **WARNING**: This is a write-once filed. (*Refer to eMMC specification*) + +Example +------- + +The *mmc info* command displays device's capabilities: +:: + + => mmc info + Device: EXYNOS DWMMC + Manufacturer ID: 45 + OEM: 100 + Name: SDW16 + Bus Speed: 52000000 + Mode: MMC DDR52 (52MHz) + Rd Block Len: 512 + MMC version 5.0 + High Capacity: Yes + Capacity: 14.7 GiB + Bus Width: 8-bit DDR + Erase Group Size: 512 KiB + HC WP Group Size: 8 MiB + User Capacity: 14.7 GiB WRREL + Boot Capacity: 4 MiB ENH + RPMB Capacity: 4 MiB ENH + Boot area 0 is not write protected + Boot area 1 is not write protected + +The raw data can be read/written via *mmc read/write* command: +:: + + => mmc read 0x40000000 0x5000 0x100 + MMC read: dev # 0, block # 20480, count 256 ... 256 blocks read: OK + + => mmc write 0x40000000 0x5000 0x10 + MMC write: dev # 0, block # 20480, count 256 ... 256 blocks written: OK + +The partition list can be shown via *mmc part* command: +:: + + => mmc part + Partition Map for MMC device 0 -- Partition Type: DOS + + Part Start Sector Num Sectors UUID Type + 1 8192 131072 dff8751a-01 0e Boot + 2 139264 6291456 dff8751a-02 83 + 3 6430720 1048576 dff8751a-03 83 + 4 7479296 23298048 dff8751a-04 05 Extd + 5 7481344 307200 dff8751a-05 83 + 6 7790592 65536 dff8751a-06 83 + 7 7858176 16384 dff8751a-07 83 + 8 7876608 22900736 dff8751a-08 83 + +The current device can be shown or set via *mmc dev* command: +:: + + => mmc dev + switch to partitions #0, OK + mmc0(part0) is current device + => mmc dev 2 0 + switch to partitions #0, OK + mmc2 is current device + +The list of available devices can be shown via *mmc list* command: +:: + + => mmc list + mmc list + EXYNOS DWMMC: 0 (eMMC) + EXYNOS DWMMC: 2 (SD) + +Configuration +------------- + +The mmc command is only avaialble if CONFIG_CMD_MMC=y. +Some commands need to enable more configuration. + +* write / erase - CONFIG_MMC_WRITE +* bootbus - CONFIG_SUPPORT_EMMC_BOOT=y -- 2.29.0

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[PATCH u-boot-marvell] ARM: dts: armada-385-turris-omnia: rename node in -u-boot.dtsi file
by Marek Behún 26 Feb '21

26 Feb '21

The SPI NOR flash node name in main device tree for Turris Omnia is called `spi-nor@0`. Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0 so that U-Boot does not try to probe the same SPI NOR device multiple times. Signed-off-by: Marek Behún <marek.behun(a)nic.cz> Cc: Stefan Roese <sr(a)denx.de> --- arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi index 1b46797583..af0655daaa 100644 --- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -41,10 +41,7 @@ &spi0 { u-boot,dm-pre-reloc; - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; + spi-nor@0 { u-boot,dm-pre-reloc; }; }; -- 2.26.2

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[PATCH u-boot-marvell 0/5] pci_mvebu changes
by Marek Behún 26 Feb '21

26 Feb '21

Hi Stefan, this patchset continues to address the issue you tried to solve with commit "pci: pci_mvebu: Disable config access to PCI host bridge ports". Some code refactoring is done here so that the code looks more sane and the underlying information is documenter. The last patch changes the local device (which presents itself as a "Memory controller" to device number 1, so that the pci command in U-Boot lists the real PCIe card as device 0, as Linux does. Marek Marek Behún (5): pci: pci_mvebu: use dev_seq instead of static variable pci: pci_mvebu: cosmetic fix pci: pci_mvebu: debug rd/wr config as other drivers do pci: pci_mvebu: refactor validation of addresses for config access pci: pci_mvebu: set local dev to number 1 drivers/pci/pci_mvebu.c | 76 ++++++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 36 deletions(-) -- 2.26.2

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