October 2021 - U-Boot

[PATCH] rockchip: Add initial support for the PinePhone Pro
by Martijn Braam 24 Dec '21

24 Dec '21

This is a new device by PINE64 that's very similar to the Pinebook Pro that's already supported. Specification: - Rockchip RK3399 - 4GB Dual-Channel LPDDR4 - 128GB eMMC - mSD card slot - AP6255 for 802.11ac WiFi and Bluetooth - 6 inch 720*1440 DSI display - Quectel EG25g usb modem - Type-C port with alt-mode display (DP 1.2) and PD charging. Signed-off-by: Martijn Braam <martijn(a)brixit.nl> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++ arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinephone-pro-rk3399/Kconfig | 15 + board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 + board/pine64/pinephone-pro-rk3399/Makefile | 1 + .../pinephone-pro-rk3399.c | 57 ++ configs/pinephone-pro-rk3399_defconfig | 92 ++++ include/configs/pinephone-pro-rk3399.h | 23 + 10 files changed, 769 insertions(+) create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c create mode 100644 configs/pinephone-pro-rk3399_defconfig create mode 100644 include/configs/pinephone-pro-rk3399.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ed3d360bb1..3206370226 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-r4s.dtb \ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ + rk3399-pinephone-pro.dtb \ rk3399-puma-haikou.dtb \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi new file mode 100644 index 0000000000..9d44db5978 --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com> + * Copyright (C) 2021 Martijn Braam <martijn at brixit.nl> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + aliases { + spi0 = &spi1; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; + + config { + u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&rk818 { + u-boot,dm-pre-reloc; +}; + +&rng { + status = "okay"; +}; + +&sdhci { + max-frequency = <25000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + max-frequency = <20000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts new file mode 100644 index 0000000000..3fe1845ced --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro.dts @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Martijn Braam <martijn(a)brixit.nl> + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Pine64 PinePhone Pro"; + compatible = "pine64,pinephone-pro", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + }; + + /* Power tree */ + /* Root power source */ + vcc_sysin: vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + }; + + /* Main 3.3v supply */ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sysin>; + vcc2-supply = <&vcc_sysin>; + vcc3-supply = <&vcc_sysin>; + vcc4-supply = <&vcc_sysin>; + vcc6-supply = <&vcc_sysin>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc_sysin>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_cpu_l: DCDC_REG1 { + regulator-name = "vdd_cpu_1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_center: DCDC_REG2 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca3v0_codec: LDO_REG1 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_codec: LDO_REG3 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_power_on: LDO_REG4 { + regulator-name = "vcc_power_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_3v0: LDO_REG5 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_dvp: LDO_REG7 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s3: LDO_REG8 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_s0: SWITCH_REG { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + status = "okay"; + }; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + work_led_pin: work-led-pin { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_perst: pcie-perst { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdcard { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + vmmc-supply = <&vcc3v3_s3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 17628f9171..3ba603ca80 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, 1920*1080 screen and all the usual laptop features. +config TARGET_PINEPHONE_PRO_RK3399 + bool "PinePhone Pro" + help + PinePhone Pro is a phone based on the Rockchip rk3399 SoC + with 4Gb RAM, onboard eMMC, USB-C, a headphone jack, + 720x1440 screen and an external Quectel USB modem. + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help @@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" +source "board/pine64/pinephone-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig new file mode 100644 index 0000000000..13d6465ae6 --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PINEPHONE_PRO_RK3399 + +config SYS_BOARD + default "pinephone-pro-rk3399" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "pinephone-pro-rk3399" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + +endif diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS new file mode 100644 index 0000000000..9ca4fc4cbe --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS @@ -0,0 +1,8 @@ +PINEPHONE_PRO +M: Martijn Braam <martijn(a)brixit.nl> +S: Maintained +F: board/pine64/rk3399-pinephone-pro/ +F: include/configs/rk3399-pinephone-pro.h +F: arch/arm/dts/rk3399-pinephone-pro.dts +F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +F: configs/pinephone-pro-rk3399_defconfig diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile new file mode 100644 index 0000000000..8d9203053e --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/Makefile @@ -0,0 +1 @@ +obj-y += pinephone-pro-rk3399.o diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c new file mode 100644 index 0000000000..8efeb6ea3d --- /dev/null +++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Vasily Khoruzhick <anarsoul(a)gmail.com> + * (C) Copyright 2021 Martijn Braam <martijn(a)brixit.nl> + */ + +#include <common.h> +#include <dm.h> +#include <init.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/misc.h> + +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define PMUGRF_CON0_VSEL_SHIFT 8 + +#ifdef CONFIG_MISC_INIT_R +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = + syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + + /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ + rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + setup_iodomain(); + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + + return ret; +} + +#endif diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig new file mode 100644 index 0000000000..2cf80f7d35 --- /dev/null +++ b/configs/pinephone-pro-rk3399_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_PINEPHONE_PRO_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro" +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEYBOARD=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_EDP=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h new file mode 100644 index 0000000000..fefa793fdd --- /dev/null +++ b/include/configs/pinephone-pro-rk3399.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd + * Copyright (C) 2020 Peter Robinson <pbrobinson at gmail.com> + * Copyright (C) 2021 Martijn Braam <martijn(a)brixit.nl> + */ + +#ifndef __PINEPHONE_PRO_RK3399_H +#define __PINEPHONE_PRO_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +#endif -- 2.33.1

5 5

[PATCH] engicam: Rename board dir, px30_core to px30
by Jagan Teki 24 Dec '21

24 Dec '21

Engicam hardware design solutions are based on System On Modules(SoM) with various SoCs like i.MX6, i.MX8 and PX30 etc. The current directory structure uses the simplest way to understand these designs by listing each of these SoC in board/engicam/SoC and inside SoC directory has SoM file name as a board file name. Right now all of the SoC's follow a similar approach except px30. So rename px30_core to px30. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Note: This patch is on top of https://patchwork.ozlabs.org/project/uboot/cover/20210804090551.90819-1-jag… arch/arm/mach-rockchip/px30/Kconfig | 2 +- board/engicam/{px30_core => px30}/Kconfig | 2 +- board/engicam/{px30_core => px30}/MAINTAINERS | 0 board/engicam/{px30_core => px30}/Makefile | 0 board/engicam/{px30_core => px30}/px30_core.c | 0 5 files changed, 2 insertions(+), 2 deletions(-) rename board/engicam/{px30_core => px30}/Kconfig (90%) rename board/engicam/{px30_core => px30}/MAINTAINERS (100%) rename board/engicam/{px30_core => px30}/Makefile (100%) rename board/engicam/{px30_core => px30}/px30_core.c (100%) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 98e09019a2..7b9b380dfa 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -68,7 +68,7 @@ config DEBUG_UART_CHANNEL For using the UART for early debugging the route to use needs to be declared (0 or 1). -source "board/engicam/px30_core/Kconfig" +source "board/engicam/px30/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30/Kconfig similarity index 90% rename from board/engicam/px30_core/Kconfig rename to board/engicam/px30/Kconfig index a03be78369..10a7ec203f 100644 --- a/board/engicam/px30_core/Kconfig +++ b/board/engicam/px30/Kconfig @@ -1,7 +1,7 @@ if TARGET_PX30_CORE config SYS_BOARD - default "px30_core" + default "px30" config SYS_VENDOR default "engicam" diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30/MAINTAINERS similarity index 100% rename from board/engicam/px30_core/MAINTAINERS rename to board/engicam/px30/MAINTAINERS diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30/Makefile similarity index 100% rename from board/engicam/px30_core/Makefile rename to board/engicam/px30/Makefile diff --git a/board/engicam/px30_core/px30_core.c b/board/engicam/px30/px30_core.c similarity index 100% rename from board/engicam/px30_core/px30_core.c rename to board/engicam/px30/px30_core.c -- 2.25.1

2 1

Re: Broken arc toolchain
by Alexey Brodkin 18 Dec '21

18 Dec '21

Hi Tom and Simon, So there're a couple of things involved indeed. 1. As Tom correctly mentioned we used to use SNSP pre-built tools for ARC in TravisCI previously. And frankly the reason was we needed something GCC 8.x based while on some other arches such a new GCC triggered extra problems, see https://lists.denx.de/pipermail/u-boot/2018-May/329577.html. So I updated ARC pre-built versions and we kept using it. 2. Now, that particular "mcpu" was never added into upstream GCC because we wanted to re-implement it a bit nicer, thus any up-to-date vanilla GCC won't accept it as opposed to tools built from SNPS' GCC port [which has it https://github.com/foss-for-synopsys-dwc-arc-processors/gcc/commit/84a3ee38…]. 3. IIRC "-mcpu=hs4x_rel31" is basically an umbrella option for some options combination based on generic "-mcpu=hs4x" so we may probably update HSDK-4xD flags to be buildable by vanialla GGC. But anyways the simples short-term solution is to use our pre-built tools, latest of which are avaialble here https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/…. And for U-Boot elf32 version is what I would suggest to use, so please use https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/…. Moreover since by default for ARC we use U-Boot built-in libgcc the same one little-endian toolchain might be safely used for building our big-endian configs equally well. If more info or actions needed, please let me know. -Alexey ________________________________ From: Tom Rini Sent: Saturday, July 10, 2021 11:22 PM To: Simon Glass Cc: U-Boot Mailing List; Alexey Brodkin; Eugeniy Paltsev Subject: Re: Broken arc toolchain On Sat, Jul 10, 2021 at 02:11:30PM -0600, Simon Glass wrote: > Hi, > > I see this: > > $ buildman --fetch-arch arc > > Downloading toolchain for arch 'arc' > Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/ > Downloading: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/9.2.0/x86_64-gc… > Unpacking to: /home/sglass/.buildman-toolchains > Testing > - looking in > '/home/sglass/.buildman-toolchains/gcc-9.2.0-nolibc/arc-linux/.' > - looking in > '/home/sglass/.buildman-toolchains/gcc-9.2.0-nolibc/arc-linux/bin' > - found > '/home/sglass/.buildman-toolchains/gcc-9.2.0-nolibc/arc-linux/bin/arc-linux-gcc' > - looking in > '/home/sglass/.buildman-toolchains/gcc-9.2.0-nolibc/arc-linux/usr/bin' > Tool chain test: OK, arch='arc', priority 5 > > $ buildman -A hsdk_4xd > /home/sglass/.buildman-toolchains/gcc-9.2.0-nolibc/arc-linux/bin/arc-linux- > $ buildman hsdk_4xd > ... > arc-linux-gcc: error: unrecognized argument in option '-mcpu=hs4x_rel31 > > > Do you have any thoughts on what is wrong, please? There's two parts. The first part is I keep forgetting to update buildman to fetch the latest toolchains from kernel.org, it should be grabbing 11.1.0 now, not 9.2.0. The second part is that arc, nds32 and xtensa have non-standard toolchain locations, see tools/docker/Dockerfile for where to fetch. -- Tom

2 1

[PATCH v5 00/29] image: Reduce #ifdefs and ad-hoc defines in image code (Part B)
by Simon Glass 17 Dec '21

17 Dec '21

Much of the image-handling code predates the introduction of Kconfig and has quite a few #ifdefs in it. It also uses its own IMAGE_... defines to help reduce the #ifdefs, which is unnecessary now that we can use IS_ENABLED() et al. The image code is also where quite a bit of code is shared with the host tools. At present this uses a lot of checks of USE_HOSTCC. This series introduces more 'tools' Kconfig options and a way to use CONFIG_IS_ENABLED() to check them. This works in a similar way to SPL, so CONFIG_IS_ENABLED(FIT) will evaluate to true on the host build (USE_HOSTCC) if CONFIG_TOOLS_FIT is enabled. This allows quite a bit of clean-up of the image.h header file and many of the image C files. The 'tools' Kconfig options should help to solve a more general problem in that we mostly want the host tools to build with all features enabled, no matter which features the 'target' build actually uses. This is a pain to arrange at present, but with 'host' Kconfigs, we can just define them all to y. There are cases where the host tools do not have features which are present on the target, for example environment and physical addressing. To help with this, some of the core image code is split out into image-board.c and image-host.c files. Even with these changes, some #ifdefs remain (down from about 100 to about 40 in common/image*). But the code is somewhat easier to follow and there are fewer build paths. Note: The original version of this series met with resistance and resulted in another series that went in first. That did make some improvements but the fundamental problem of sharing code with tools remains. It seems like a good time to get this one in, before further refactoring happens. It was a significant effort to rebase this series on -next and I hope not to do it again. This series is available at u-boot-dm/host-working Changes in v5: - Add a new patch to rename host_build() to tools_build() - Add new patch to bring back SPL_ versions of SHA - Avoid preprocessor in a few more places - Drop I_WANT_MD5 - Drop changes to tools/Makefile since they already use TOOLS_ Kconfigs - Drop rd_load since it is not used - Fix up tools/Makefile to have the correct condition - Rebase to next - Update commit message - Update commit message to indicate that the code is in a separate file - Use TOOLS_ instead of HOST_ Changes in v2: - Add SPL_ Kconfigs also, since otherwise hashing algorithms drop from SPL - All patches rebased to -next - Consider selecting a raw FDT to be success - Correct comment about USE_HOSTCC being undefined in CONFIG_VAL() - Correct logic for the non-FIT case - Drop unnecessary setting of rd_len, etc. - Fix up comment to put an underscore after every CONFIG Simon Glass (29): compiler: Rename host_build() to tools_build() kconfig: Add tools support to CONFIG_IS_ENABLED() image: Add Kconfig options for FIT in the tools build spl: cypto: Bring back SPL_ versions of SHA hash: Use Kconfig to enable hashing in host tools and SPL hash: Drop some #ifdefs in hash.c image: Drop IMAGE_ENABLE_FIT image: Drop IMAGE_ENABLE_OF_LIBFDT image: Use Kconfig to enable CONFIG_FIT_VERBOSE on host image: Use Kconfig to enable FIT_RSASSA_PSS on host image: Use the correct checks for CRC32 image: Drop IMAGE_BOOT_GET_CMDLINE image: Drop IMAGE_OF_BOARD_SETUP image: Drop IMAGE_OF_SYSTEM_SETUP image: Drop IMAGE_ENABLE_IGNORE efi: Correct dependency on FIT_SIGNATURE image: Drop IMAGE_ENABLE_SIGN/VERIFY defines image: Drop IMAGE_ENABLE_EN/DECRYPT defines image: Tidy up fit_unsupported_reset() image: Drop unnecessary #ifdefs from image.h image: Drop #ifdefs for fit_print_contents() image: Drop most #ifdefs in image-board.c image: Reduce variable scope in boot_get_ramdisk() image: Split up boot_get_ramdisk() image: Remove #ifdefs from select_ramdisk() image: Remove some #ifdefs from image-fit and image-fit-sig image: Reduce variable scope in boot_get_fdt() image: Split up boot_get_fdt() image: Remove #ifdefs from select_fdt() arch/arc/lib/bootm.c | 2 +- arch/arm/lib/bootm.c | 4 +- arch/arm/mach-imx/hab.c | 2 +- arch/microblaze/lib/bootm.c | 2 +- arch/nds32/lib/bootm.c | 4 +- arch/riscv/lib/bootm.c | 4 +- board/synopsys/hsdk/hsdk.c | 2 +- common/Kconfig.boot | 10 + common/bootm.c | 14 +- common/bootm_os.c | 8 + common/hash.c | 108 +++++----- common/image-board.c | 359 +++++++++++++++++---------------- common/image-cipher.c | 6 +- common/image-fdt.c | 275 +++++++++++++------------ common/image-fit-sig.c | 7 +- common/image-fit.c | 36 ++-- common/image.c | 14 +- common/spl/Kconfig | 13 +- include/compiler.h | 5 +- include/fdt_support.h | 2 +- include/image.h | 127 ++---------- include/linux/kconfig.h | 13 +- include/u-boot/aes.h | 8 +- include/u-boot/hash-checksum.h | 5 +- include/u-boot/rsa.h | 2 - lib/Kconfig | 66 +++++- lib/Makefile | 4 +- lib/efi_loader/Kconfig | 2 +- lib/hash-checksum.c | 2 +- lib/lmb.c | 2 +- lib/rsa/rsa-sign.c | 5 +- lib/rsa/rsa-verify.c | 16 +- tools/Kconfig | 92 +++++++++ tools/Makefile | 2 +- tools/image-host.c | 6 +- 35 files changed, 675 insertions(+), 554 deletions(-) -- 2.33.0.685.g46640cef36-goog

5 89

[PATCH 0/5] board: mediatek: pumpkin: add fastboot support
by Fabien Parent 16 Dec '21

16 Dec '21

This series adds USB/Fastboot support on MT8516 Pumpkin board. Fabien Parent (5): arm: dts: mt8516: add support for USB arm: dts: mt8516-pumpkin: enable usb port board: mediatek: pumpkin: initialize usb device configs: pumpkin: enable USB gadget configs: pumpkin: enable fastboot arch/arm/dts/mt8516-pumpkin.dts | 10 ++++++++++ arch/arm/dts/mt8516.dtsi | 14 ++++++++++++++ board/mediatek/pumpkin/pumpkin.c | 17 +++++++++++++++++ configs/pumpkin_defconfig | 15 ++++++++++++++- 4 files changed, 55 insertions(+), 1 deletion(-) -- 2.28.0

3 12

[PATCH] clk: fix clk_get_rate() documentation
by Giulio Benetti 15 Dec '21

15 Dec '21

clk_get_rate() can't and doesn't return -ve on error, it actually returns 0 on error or a value greater than 0 on success. So let's fix its documentation. Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- include/clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/clk.h b/include/clk.h index ca6b85fa6f..a833d6a27b 100644 --- a/include/clk.h +++ b/include/clk.h @@ -344,7 +344,7 @@ int clk_free(struct clk *clk); * * @clk: A clock struct that was previously successfully requested by * clk_request/get_by_*(). - * @return clock rate in Hz, or -ve error code. + * @return clock rate in Hz on success, or 0 on error. */ ulong clk_get_rate(struct clk *clk); -- 2.25.1

5 15

[PATCH v3] sunxi: h3: enable clock support for r_pio gpios
by Manuel Dipolt 08 Dec '21

08 Dec '21

This patch enables clock for the r_pio gpios for the h3 r_pio is required to access gpios from port L readout or setting of gpio PL10 (for example to control a led): => gpio input PL10 gpio: pin PL10 (gpio 298) value is 0 => gpio set PL10 gpio: pin PL10 (gpio 298) value is 1 before: => gpio input PL10 gpio: pin PL10 (gpio 298) value is 0 => gpio set PL10 gpio: pin PL10 (gpio 298) value is 1 Warning: value of pin is still 0 Signed-off-by: Manuel Dipolt <manuel.dipolt(a)robart.cc> --- drivers/gpio/sunxi_gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index cdbc40d48f..0185eda70d 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -14,6 +14,7 @@ #include <errno.h> #include <fdtdec.h> #include <malloc.h> +#include <clk.h> #include <asm/io.h> #include <asm/gpio.h> #include <dm/device-internal.h> @@ -245,6 +246,13 @@ static int gpio_sunxi_probe(struct udevice *dev) { struct sunxi_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk gate_clk; + int ret; + + ret = clk_get_by_name(dev, "apb", &gate_clk); + + if (!ret) + clk_enable(&gate_clk); /* Tell the uclass how many GPIOs we have */ if (plat) { -- 2.20.1

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[PATCH 0/3] dtoc: Improve support for 'ranges' property
by Simon Glass 07 Dec '21

07 Dec '21

An empty ranges property confuses dtoc at present and it dies with an error. This series fixes this and a few related things. Simon Glass (3): dtoc: Rename is_wider_than() to reduce confusion dtoc: Fix widening an int array to an int dtoc: Support widening a bool value arch/sandbox/dts/sandbox.dtsi | 2 ++ test/dm/of_platdata.c | 7 ++--- tools/dtoc/fdt.py | 40 +++++++++++++++++++--------- tools/dtoc/test/dtoc_test_simple.dts | 2 ++ tools/dtoc/test_dtoc.py | 9 ++++--- tools/dtoc/test_fdt.py | 29 +++++++++++++++++--- 6 files changed, 68 insertions(+), 21 deletions(-) -- 2.32.0.432.gabb21c7263-goog

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[PATCH v2 1/3] phy-sun4i-usb: Fix sun8i_r40_cfg
by qianfanguijin＠163.com 07 Dec '21

07 Dec '21

From: qianfan Zhao <qianfanguijin(a)163.com> the r40 has the same configurations with a33, disable enable_pmu_unk1 and phy0_dual_route feature. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- drivers/phy/allwinner/phy-sun4i-usb.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 5723c98032..5ea05a207d 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -589,8 +589,6 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, - .phy0_dual_route = true, }; static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { -- 2.17.1

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[PATCH v2 3/6] clk: sunxi: v3s: fix tabs / spaces
by Andreas Rehn 07 Dec '21

07 Dec '21

align CLK_USB_PHY0 with tabs Signed-off-by: Andreas Rehn <rehn.andreas86(a)gmail.com> --- drivers/clk/sunxi/clk_v3s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 55fc597043..bc6b7b4870 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -29,7 +29,7 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_SPI0] = GATE(0x0a0, BIT(31)), - [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), }; static struct ccu_reset v3s_resets[] = { -- 2.25.1

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