October 2021 - U-Boot

[PATCH 01/14] rk3308: Remove unused NAND defines
by Tom Rini 06 Oct '21

06 Oct '21

These platforms do not currently enable NAND, remove these references. Cc: Kever Yang <kever.yang(a)rock-chips.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- Please note that this file isn't listed in any MAINTAINERS file, but should be, thanks! --- include/configs/rk3308_common.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index edaf78a6e81a..496f4628d34f 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -9,11 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) #define CONFIG_SPL_MAX_SIZE 0x20000 #define CONFIG_SPL_BSS_START_ADDR 0x00400000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 -- 2.17.1

1 27

[PATCH] lib: rsa: fix dependency for SPL_RSA_VERIFY
by Oleksandr Suvorov 06 Oct '21

06 Oct '21

SPL_RSA_VERIFY requires SPL_RSA to be enabled. Add correct dependency. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov(a)foundries.io> --- lib/rsa/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index a90d67e5a87..cf802a6d40a 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -20,6 +20,7 @@ config SPL_RSA config SPL_RSA_VERIFY bool + depends on SPL_RSA help Add RSA signature verification support in SPL. -- 2.31.1

2 1

[PATCH] acpi: Use U-Boot version for OEM_REVISION
by Pali Rohár 06 Oct '21

06 Oct '21

OEM_REVISION is 32-bit unsigned number. It should be increased only when changing software version. Therefore it should not depend on build time. Change calculation to use U-Boot version numbers and set this revision to date number. Prior this change OEM_REVISION was calculated from build date and stored in the same format. After this change macro U_BOOT_BUILD_DATE is not used in other files so remove it from global autogenerated files and also from Makefile. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- This patch depends on similar patch for BIOS Release Date which is here: http://patchwork.ozlabs.org/project/uboot/patch/20210422160957.26936-1-pali… --- Makefile | 2 -- doc/develop/version.rst | 1 - lib/acpi/acpi_table.c | 18 +++++++++++++++++- test/dm/acpi.c | 20 ++++++++++++++------ 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index 2047081a0739..6dd7d140cfa4 100644 --- a/Makefile +++ b/Makefile @@ -1903,7 +1903,6 @@ define filechk_timestamp.h LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ - LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \ else \ return 42; \ @@ -1912,7 +1911,6 @@ define filechk_timestamp.h LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \ LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ - LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \ fi) endef diff --git a/doc/develop/version.rst b/doc/develop/version.rst index 066901bcd2d9..3f2b07cd2261 100644 --- a/doc/develop/version.rst +++ b/doc/develop/version.rst @@ -84,7 +84,6 @@ fields. For example:: #define U_BOOT_DATE "Jan 06 2021" (US format only) #define U_BOOT_TIME "08:50:36" (24-hour clock) #define U_BOOT_TZ "-0700" (Time zone in hours) - #define U_BOOT_BUILD_DATE 0x20210106 (hex yyyymmdd format) #define U_BOOT_EPOCH 1609948236 The Epoch is the number of seconds since midnight on 1/1/70. You can convert diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 2f0774178412..e2f1dc0fc08f 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -16,6 +16,22 @@ #include <asm/global_data.h> #include <dm/acpi.h> +/* + * OEM_REVISION is 32-bit unsigned number. It should be increased only when + * changing software version. Therefore it should not depend on build time. + * U-Boot calculates it from U-Boot version and represent it in hexadecimal + * notation. As U-Boot version is in form year.month set low 8 bits to 0x01 + * to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to + * value 0x20210401. + */ +#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ + (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ + (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ + ((U_BOOT_VERSION_NUM % 10) << 16) | \ + (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ + ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ + 0x01) + int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) { struct acpi_table_header *header = &dmar->header; @@ -100,7 +116,7 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature) memcpy(header->signature, signature, 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); - header->oem_revision = U_BOOT_BUILD_DATE; + header->oem_revision = OEM_REVISION; memcpy(header->aslc_id, ASLC_ID, 4); } diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 2edab7be5445..92901f4c7cc4 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -25,6 +25,14 @@ #define BUF_SIZE 4096 +#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ + (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ + (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ + ((U_BOOT_VERSION_NUM % 10) << 16) | \ + (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ + ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ + 0x01) + /** * struct testacpi_plat - Platform data for the test ACPI device * @@ -218,7 +226,7 @@ static int dm_test_acpi_fill_header(struct unit_test_state *uts) ut_asserteq_mem(OEM_ID, hdr.oem_id, sizeof(hdr.oem_id)); ut_asserteq_mem(OEM_TABLE_ID, hdr.oem_table_id, sizeof(hdr.oem_table_id)); - ut_asserteq(U_BOOT_BUILD_DATE, hdr.oem_revision); + ut_asserteq(OEM_REVISION, hdr.oem_revision); ut_asserteq_mem(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id)); ut_asserteq(0x44, hdr.aslc_revision); @@ -365,20 +373,20 @@ static int dm_test_acpi_cmd_list(struct unit_test_state *uts) addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16); ut_assert_nextline("RSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_table_header) + - 3 * sizeof(u32), U_BOOT_BUILD_DATE); + 3 * sizeof(u32), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16); ut_assert_nextline("XSDT %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_table_header) + - 3 * sizeof(u64), U_BOOT_BUILD_DATE); + 3 * sizeof(u64), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64); ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", - addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + addr, sizeof(struct acpi_dmar), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", - addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + addr, sizeof(struct acpi_dmar), OEM_REVISION); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); ut_assert_nextline("DMAR %08lx %06zx (v01 U-BOOT U-BOOTBL %x INTL 0)", - addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); + addr, sizeof(struct acpi_dmar), OEM_REVISION); ut_assert_console_end(); return 0; -- 2.20.1

3 6

[PATCH] stv0991: remove specific CONFIG_STV0991 configs
by Patrick Delaunay 06 Oct '21

06 Oct '21

Remove the following STV0991 specific configs: - CONFIG_STV0991 (never used) - CONFIG_STV0991_HZ (replaced by generic CONFIG_SYS_HZ) - CONFIG_STV0991_HZ_CLOCK (replaced by generic CONFIG_SYS_HZ_CLOCK) This patch allows to reduce the file config_whitelist.txt. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/cpu/armv7/stv0991/timer.c | 6 +++--- arch/arm/include/asm/arch-stv0991/stv0991_gpt.h | 4 ++-- scripts/config_whitelist.txt | 3 --- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c index 07033acb5c..67764ccf66 100644 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ) +#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -67,7 +67,7 @@ void __udelay(unsigned long usec) { ulong tmo; ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100); + ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); ulong rndoff; rndoff = (usec % 10) ? 1 : 0; @@ -110,5 +110,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - return CONFIG_STV0991_HZ; + return CONFIG_SYS_HZ; } diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index cd27472ad7..f1d5667c32 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -36,7 +36,7 @@ struct gpt_regs *const gpt1_regs_ptr = #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_STV0991_HZ 1000 -#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 61ae682dcd..58f4b02f60 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1303,9 +1303,6 @@ CONFIG_STANDALONE_LOAD_ADDR CONFIG_STATIC_BOARD_REV CONFIG_STD_DEVICES_SETTINGS CONFIG_STM32_FLASH -CONFIG_STV0991 -CONFIG_STV0991_HZ -CONFIG_STV0991_HZ_CLOCK CONFIG_SXNI855T CONFIG_SYSFS CONFIG_SYSMGR_ISWGRP_HANDOFF -- 2.25.1

2 1

[PATCH v2] pwm: Add driver for cadence TTC
by Michal Simek 06 Oct '21

06 Oct '21

TTC has three modes of operations. Timer, PWM and input counters. There is already driver for timer under CADENCE_TTC_TIMER which is used for ZynqMP R5 configuration. This driver is targeting PWM which is for example configuration which can be used for fan control. The driver has been tested on Xilinx Kria SOM platform where fan is connected to one PL pin. When TTC output is connected via EMIO to PL pin TTC pwm can be configured and tested for example like this: pwm config 0 0 10000 1200 pwm enable 0 0 pwm config 0 0 10000 1400 pwm config 0 0 10000 1600 Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Detect pwm-cells property for PWM driver - Fix all macro names - Use BIT and GENMASK macros - Introduce TTC_REG macro for reg offsets - Use FIELD_PREP - Move cadence_ttc_pwm_of_to_plat() below probe - Introduce struct cadence_ttc_pwm_plat - Read timer-width from DT - Use NSEC_PER_SEC macro - Use clock_ctrl variable instead of x - all reported by Sean MAINTAINERS | 1 + drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cadence-ttc.c | 247 ++++++++++++++++++++++++++++++++++ 4 files changed, 256 insertions(+) create mode 100644 drivers/pwm/pwm-cadence-ttc.c diff --git a/MAINTAINERS b/MAINTAINERS index 4cf0c33c5d58..889813382249 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,6 +600,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/pwm/pwm-cadence-ttc.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cf7f4c6840ce..176e703c8fbb 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,6 +9,13 @@ config DM_PWM frequency/period can be controlled along with the proportion of that time that the signal is high. +config PWM_CADENCE_TTC + bool "Enable support for the Cadence TTC PWM" + depends on DM_PWM && !CADENCE_TTC_TIMER + help + Cadence TTC can be configured as timer which is done via + CONFIG_CADENCE_TTC_TIMER or as PWM. This is covering only PWM now. + config PWM_CROS_EC bool "Enable support for the Chrome OS EC PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 10d244bfb79d..abf5af41d2cc 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o +obj-$(CONFIG_PWM_CADENCE_TTC) += pwm-cadence-ttc.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c new file mode 100644 index 000000000000..99aaaa6a8ab6 --- /dev/null +++ b/drivers/pwm/pwm-cadence-ttc.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 Xilinx, Inc. Michal Simek + */ + +#include <clk.h> +#include <common.h> +#include <div64.h> +#include <dm.h> +#include <log.h> +#include <pwm.h> +#include <asm/io.h> +#include <log.h> +#include <div64.h> +#include <linux/bitfield.h> +#include <linux/math64.h> +#include <linux/log2.h> +#include <dm/device_compat.h> + +#define CLOCK_CONTROL 0 +#define COUNTER_CONTROL 0xc +#define INTERVAL_COUNTER 0x24 +#define MATCH_1_COUNTER 0x30 + +#define CLK_FALLING_EDGE BIT(6) +#define CLK_SRC_EXTERNAL BIT(5) +#define CLK_PRESCALE_MASK GENMASK(4, 1) +#define CLK_PRESCALE_ENABLE BIT(0) + +#define COUNTER_WAVE_POL BIT(6) +#define COUNTER_WAVE_DISABLE BIT(5) +#define COUNTER_RESET BIT(4) +#define COUNTER_MATCH_ENABLE BIT(3) +#define COUNTER_DECREMENT_ENABLE BIT(2) +#define COUNTER_INTERVAL_ENABLE BIT(1) +#define COUNTER_COUNTING_DISABLE BIT(0) + +#define NSEC_PER_SEC 1000000000L + +#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32)) +#define TTC_CLOCK_CONTROL(reg, channel) \ + TTC_REG((reg) + CLOCK_CONTROL, (channel)) +#define TTC_COUNTER_CONTROL(reg, channel) \ + TTC_REG((reg) + COUNTER_CONTROL, (channel)) +#define TTC_INTERVAL_COUNTER(reg, channel) \ + TTC_REG((reg) + INTERVAL_COUNTER, (channel)) +#define TTC_MATCH_1_COUNTER(reg, channel) \ + TTC_REG((reg) + MATCH_1_COUNTER, (channel)) + +struct cadence_ttc_pwm_plat { + u8 *regs; + u32 timer_mask; +}; + +struct cadence_ttc_pwm_priv { + u8 *regs; + u32 timer_mask; + unsigned long frequency; + bool invert[2]; +}; + +static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + priv->invert[channel] = polarity; + + dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity); + + return 0; +} + +static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + u32 counter_ctrl, clock_ctrl; + int period_clocks, duty_clocks, prescaler; + + dev_dbg(dev, "channel %d, duty %d/ period %d ns\n", channel, + duty_ns, period_ns); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + /* Make sure counter is stopped */ + counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel)); + setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_COUNTING_DISABLE); + + /* Calculate period, prescaler and set clock control register */ + period_clocks = div64_u64(((int64_t)period_ns * priv->frequency), + NSEC_PER_SEC); + + prescaler = ilog2(period_clocks) + 1 - 16; + if (prescaler < 0) + prescaler = 0; + + clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel)); + + if (!prescaler) { + clock_ctrl &= ~(CLK_PRESCALE_ENABLE | CLK_PRESCALE_MASK); + } else { + clock_ctrl &= ~CLK_PRESCALE_MASK; + clock_ctrl |= CLK_PRESCALE_ENABLE; + clock_ctrl |= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1); + }; + + /* External source is not handled by this driver now */ + clock_ctrl &= ~CLK_SRC_EXTERNAL; + + writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel)); + + /* Calculate interval and set counter control value */ + duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency), + NSEC_PER_SEC); + + writel((period_clocks >> prescaler) & priv->timer_mask, + TTC_INTERVAL_COUNTER(priv->regs, channel)); + writel((duty_clocks >> prescaler) & priv->timer_mask, + TTC_MATCH_1_COUNTER(priv->regs, channel)); + + /* Restore/reset counter */ + counter_ctrl &= ~COUNTER_DECREMENT_ENABLE; + counter_ctrl |= COUNTER_INTERVAL_ENABLE | + COUNTER_RESET | + COUNTER_MATCH_ENABLE; + + if (priv->invert[channel]) + counter_ctrl |= COUNTER_WAVE_POL; + else + counter_ctrl &= ~COUNTER_WAVE_POL; + + writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel)); + + dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks, + period_clocks, prescaler); + + return 0; +}; + +static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel, + bool enable) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel); + + if (enable) { + clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_COUNTING_DISABLE | + COUNTER_WAVE_DISABLE); + setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_RESET); + } else { + setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel), + COUNTER_COUNTING_DISABLE | + COUNTER_WAVE_DISABLE); + } + + return 0; +}; + +static int cadence_ttc_pwm_probe(struct udevice *dev) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev); + struct clk clk; + int ret; + + priv->regs = plat->regs; + priv->timer_mask = plat->timer_mask; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + priv->frequency = clk_get_rate(&clk); + if (IS_ERR_VALUE(priv->frequency)) { + dev_err(dev, "failed to get rate\n"); + return priv->frequency; + } + dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency); + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + return 0; +} + +static int cadence_ttc_pwm_of_to_plat(struct udevice *dev) +{ + struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev); + const char *cells; + u32 timer_width; + + cells = dev_read_prop(dev, "#pwm-cells", NULL); + if (!cells) + return -EINVAL; + + plat->regs = dev_read_addr_ptr(dev); + + timer_width = dev_read_u32_default(dev, "timer-width", 16); + plat->timer_mask = GENMASK(timer_width - 1, 0); + + return 0; +} + +static const struct pwm_ops cadence_ttc_pwm_ops = { + .set_invert = cadence_ttc_pwm_set_invert, + .set_config = cadence_ttc_pwm_set_config, + .set_enable = cadence_ttc_pwm_set_enable, +}; + +static const struct udevice_id cadence_ttc_pwm_ids[] = { + { .compatible = "cdns,ttc" }, + { } +}; + +U_BOOT_DRIVER(cadence_ttc_pwm) = { + .name = "cadence_ttc_pwm", + .id = UCLASS_PWM, + .of_match = cadence_ttc_pwm_ids, + .ops = &cadence_ttc_pwm_ops, + .of_to_plat = cadence_ttc_pwm_of_to_plat, + .probe = cadence_ttc_pwm_probe, + .priv_auto = sizeof(struct cadence_ttc_pwm_priv), + .plat_auto = sizeof(struct cadence_ttc_pwm_plat), +}; -- 2.33.0

2 2

[PATCH] efi_loader: don't load shims MOK database from file
by Heinrich Schuchardt 06 Oct '21

06 Oct '21

When using a file to store UEFI variables we must make sure that secure boot related variables are not loaded from this file. With commit 9ef82e29478c ("efi_loader: don't load signature database from file") this has already been implemented for variables defined in the UEFI specification. As most Linux distributions use Shim we should do the same for Shim's MOK database. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- lib/efi_loader/efi_var_file.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index c7c6805ed0..76a2ff9e41 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -19,6 +19,13 @@ #define PART_STR_LEN 10 +/* GUID used by Shim to store the MOK database */ +#define SHIM_LOCK_GUID \ + EFI_GUID(0x605dab50, 0xe046, 0x4300, \ + 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23) + +static const efi_guid_t shim_lock_guid = SHIM_LOCK_GUID; + /** * efi_set_blk_dev_to_system_partition() - select EFI system partition * @@ -175,6 +182,7 @@ efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) if (!safe && (efi_auth_var_get_type(var->name, &var->guid) != EFI_AUTH_VAR_NONE || + !guidcmp(&var->guid, &shim_lock_guid) || !(var->attr & EFI_VARIABLE_NON_VOLATILE))) continue; if (!var->length) -- 2.32.0

1 0

[PATCH v5 0/5] env: Allow environment in text files
by Simon Glass 06 Oct '21

06 Oct '21

One barrier to completing the 7-year-long Kconfig migration is that the default environment is implemented using ad-hoc CONFIG options. At present U-Boot environment variables, and thus scripts, are defined by CONFIG_EXTRA_ENV_SETTINGS. It is not really feasible to move the environment to Kconfig as it is hundreds of lines of text in some cases. Even considering the current situation, it is painful to add large amounts of text to the config-header file and dealing with quoting and newlines is harder than it should be. It would be better if we could just type the script into a text file and have it included by U-Boot. Add a feature that brings in a .env file associated with the board config, if present. To use it, create a file in a board/<vendor>/env directory called <board>.env (or common.env if you want the same environment for all boards). The environment variables should be of the form "var=value". Values can extend to multiple lines. This series converts the existing environment documentation to rST and updates it to explain how to use this. Note: this series was originally sent eight years ago: https://patchwork.ozlabs.org/project/uboot/patch/1382763695-2849-4-git-send… It has been updated to work with Kconfig, etc. Some review comments in that patch were infeasible so I have not addressed them. I would like this series to be considered independently, on its merits. Rather than deal with the complexity of rewriting the distro-boot script, this is disabled for sandbox. The forthcoming bootmethod approach should provide the same functionality without needing the complex scripting in the environment. Migration needs more thought, although it can be done later. It may be possible to do migrate automatically, using buildman to extract the built-in environmnent from the ELF file. This would produce a pretty ugly conversion though, since it would drop all the intermediate variables used to create the environment. Better would be to parse the config.h file, figure out the components of CONFIG_EXTRA_ENV_SETTINGS then output these as separate pieces in the file. It is not clear how easy that would be, nor whether the result would be very pretty. Also the __stringify() macro needs to be handled somehow. This series is available at u-boot-dm/env-working Comments welcome. Changes in v5: - Minor updates as suggested by Wolfgang - Explain how to include the common.env file - Explain why variables starting with _ , and / are not supported - Expand the definition of how to declare an environment variable - Explain what happens to empty variables - Update maintainer Changes in v4: - Add new patch to move environment documentation to rST - Move this from being part of configuring U-Boot to part of building it - Don't put the environment in autoconf.mk as it is not needed - Add documentation in rST format instead of README - Drop mention of import/export - Update awk script to ignore blank lines, as generated by clang - Add documentation in rST format instead of README - Move use of += to this patch - Explain that environment variables may not end in + Changes in v3: - Adjust Makefile to generate the .inc and .h files in separate fules - Add more detail in the README about the format of .env files - Improve the comment about " in the awk script - Correctly terminate environment files with \n - Define __UBOOT_CONFIG__ when collecting environment files - Add new patch to use a text-based environment for sandbox Changes in v2: - Move .env file from include/configs to board/ - Use awk script to process environment since it is much easier on the brain - Add information and updated example script to README - Add dependency rule so that the environment is rebuilt when it changes - Add separate patch to enable C preprocessor for environment files - Enable var+=value form to simplify composing variables in multiple steps Simon Glass (5): sandbox: Drop distro_boot doc: Move environment documentation to rST env: Allow U-Boot scripts to be placed in a .env file env: Allow environment files to use the C preprocessor sandbox: Use a text-based environment MAINTAINERS | 7 + Makefile | 39 ++- README | 328 ------------------------- board/sandbox/env/sandbox.env | 25 ++ config.mk | 2 + doc/usage/environment.rst | 444 ++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + env/embedded.c | 1 + include/configs/sandbox.h | 40 --- include/env_default.h | 8 + scripts/env2string.awk | 56 +++++ 11 files changed, 582 insertions(+), 369 deletions(-) create mode 100644 board/sandbox/env/sandbox.env create mode 100644 doc/usage/environment.rst create mode 100644 scripts/env2string.awk -- 2.33.0.800.g4c38ced690-goog

4 17

[ANN] U-Boot v2021.10 released
by Tom Rini 06 Oct '21

06 Oct '21

Hey all, It is release day and here is v2021.10. With this release we are now at the third of our 2 years past a number of DM migration deadlines. We're now at the point where it's watchdog related migrations that are past due. This is actually a small list of boards and I think can be quickly resolved. At this point, between what has been removed for this release and what's queued up already in -next, we've made good progress on clearing out legacy platforms. What I would like to call attention to in general is the number of CONFIG symbols that need to be migrated to Kconfig still. If you maintain a board or SoC, please check for symbols specific to your area of code that aren't migrated yet and see how to move them. The tools/moveconfig.py tool can handle a lot of cases. If it's tricky please reach out. In terms of a changelog, git log --merges v2021.10-rc4..v2021.10-rc5 contains what I've pulled since the last RC or: git log --merges v2021.07..v2021.10 for changes since the last full release. As always, more details in pull requests (or the tags referenced by them) will result in more details here. With this, the merge window is now open and I'll be merging in the next branch shortly. v2022.01 is scheduled for release on Monday, January 10th 2022 and the merge window closes on October 25th. Thanks all! -- Tom

3 5

[PATCH] pytest: Show a message when sandbox crashes
by Simon Glass 06 Oct '21

06 Oct '21

When a test hands on a real board there is no way on the console to obtain any information about why it hung. With sandbox we can actually find out that it died and get a signal or exit code. Add this to make it easier to figure out what happened. So instead of: test/py/u_boot_spawn.py:171: in expect c = os.read(self.fd, 1024).decode(errors='replace') E OSError: [Errno 5] Input/output error We get: test/py/u_boot_spawn.py:171: in expect c = os.read(self.fd, 1024).decode(errors='replace') E ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV) Signed-off-by: Simon Glass <sjg(a)chromium.org> --- doc/develop/py_testing.rst | 8 ++++++ test/py/u_boot_spawn.py | 56 ++++++++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 12 deletions(-) diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst index 52238ca54d3..06f919609b5 100644 --- a/doc/develop/py_testing.rst +++ b/doc/develop/py_testing.rst @@ -103,6 +103,14 @@ will be written to `${build_dir}/test-log.html`. This is best viewed in a web browser, but may be read directly as plain text, perhaps with the aid of the `html2text` utility. +If sandbox crashes (e.g. with a segfault) you will see message like this:: + + + test/py/u_boot_spawn.py:171: in expect + c = os.read(self.fd, 1024).decode(errors='replace') + E ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV) + + Controlling output ~~~~~~~~~~~~~~~~~~ diff --git a/test/py/u_boot_spawn.py b/test/py/u_boot_spawn.py index 6991b78cca8..b6ab544eaa1 100644 --- a/test/py/u_boot_spawn.py +++ b/test/py/u_boot_spawn.py @@ -35,6 +35,8 @@ class Spawn(object): """ self.waited = False + self.exit_code = 0 + self.exit_info = '' self.buf = '' self.output = '' self.logfile_read = None @@ -80,25 +82,44 @@ class Spawn(object): os.kill(self.pid, sig) - def isalive(self): + def checkalive(self): """Determine whether the child process is still running. - Args: - None. - Returns: - Boolean indicating whether process is alive. + tuple: + True if process is alive, else False + 0 if process is alive, else exit code of process + string describing what happened ('' or 'status/signal n') """ if self.waited: - return False + return False, exit_code, self.exit_info w = os.waitpid(self.pid, os.WNOHANG) if w[0] == 0: - return True - + return True, 0, 'running' + status = w[1] + + if os.WIFEXITED(status): + self.exit_code = os.WEXITSTATUS(status) + self.exit_info = 'status %d' % self.exit_code + elif os.WIFSIGNALED(status): + signum = os.WTERMSIG(status) + self.exit_code = -signum + self.exit_info = 'signal %d (%s)' % (signum, signal.Signals(signum)) self.waited = True - return False + return False, self.exit_code, self.exit_info + + def isalive(self): + """Determine whether the child process is still running. + + Args: + None. + + Returns: + Boolean indicating whether process is alive. + """ + return self.checkalive()[0] def send(self, data): """Send data to the sub-process's stdin. @@ -168,9 +189,20 @@ class Spawn(object): events = self.poll.poll(poll_maxwait) if not events: raise Timeout() - c = os.read(self.fd, 1024).decode(errors='replace') - if not c: - raise EOFError() + try: + c = os.read(self.fd, 1024).decode(errors='replace') + except OSError as err: + # With sandbox, try to detect when U-Boot exits when it + # shouldn't and explain why. This is much more friendly than + # just dying with an I/O error + if err.errno == 5: # Input/output error + alive, exit_code, info = self.checkalive() + if alive: + raise + else: + raise ValueError('U-Boot exited with %s' % info) + else: + raise if self.logfile_read: self.logfile_read.write(c) self.buf += c -- 2.33.0.800.g4c38ced690-goog

1 0

[PATCH 1/2] clk: sunxi: Add support for I2C gates/resets
by Samuel Holland 06 Oct '21

06 Oct '21

Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- drivers/clk/sunxi/clk_a10.c | 5 +++++ drivers/clk/sunxi/clk_a10s.c | 3 +++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 8 ++++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a80.c | 10 ++++++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ drivers/clk/sunxi/clk_h6.c | 10 ++++++++++ drivers/clk/sunxi/clk_h616.c | 12 ++++++++++++ drivers/clk/sunxi/clk_r40.c | 10 ++++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++++ 12 files changed, 86 insertions(+) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 1b5de86e204..20006925f1e 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -31,6 +31,11 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_GMAC] = GATE(0x064, BIT(17)), + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), + [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)), + [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index 184f61ab234..7e7b2bf7009 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -25,6 +25,9 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)), + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)), + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 5750514a74f..87011525dcf 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -23,6 +23,9 @@ static struct ccu_clk_gate a23_gates[] = { [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -53,6 +56,9 @@ static struct ccu_reset a23_resets[] = { [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 9226112f4af..2554762df9d 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -30,6 +30,10 @@ static struct ccu_clk_gate a31_gates[] = { [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)), + [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)), + [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)), + [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)), + [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)), [CLK_APB2_UART0] = GATE(0x06c, BIT(16)), [CLK_APB2_UART1] = GATE(0x06c, BIT(17)), [CLK_APB2_UART2] = GATE(0x06c, BIT(18)), @@ -71,6 +75,10 @@ static struct ccu_reset a31_resets[] = { [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)), [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)), + [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)), + [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)), + [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)), + [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)), [RST_APB2_UART0] = RESET(0x2d8, BIT(16)), [RST_APB2_UART1] = RESET(0x2d8, BIT(17)), [RST_APB2_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 0553ffa4399..013801c7e41 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -60,6 +63,9 @@ static const struct ccu_reset a64_resets[] = { [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 68973d528ed..79083e846f9 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -25,6 +25,11 @@ static const struct ccu_clk_gate a80_gates[] = { [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), [CLK_BUS_SPI3] = GATE(0x580, BIT(23)), + [CLK_BUS_I2C0] = GATE(0x594, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x594, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x594, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x594, BIT(3)), + [CLK_BUS_I2C4] = GATE(0x594, BIT(4)), [CLK_BUS_UART0] = GATE(0x594, BIT(16)), [CLK_BUS_UART1] = GATE(0x594, BIT(17)), [CLK_BUS_UART2] = GATE(0x594, BIT(18)), @@ -40,6 +45,11 @@ static const struct ccu_reset a80_resets[] = { [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)), [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)), + [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)), + [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)), + [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)), + [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)), + [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)), [RST_BUS_UART0] = RESET(0x5b4, BIT(16)), [RST_BUS_UART1] = RESET(0x5b4, BIT(17)), [RST_BUS_UART2] = RESET(0x5b4, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 880c7d75997..b21bd1db2c2 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -25,6 +25,9 @@ static struct ccu_clk_gate a83t_gates[] = { [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -57,6 +60,9 @@ static struct ccu_reset a83t_resets[] = { [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f81633b92d5..5741b5e6be6 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -74,6 +77,9 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index df93d96b3b0..0ee089295e0 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -22,6 +22,11 @@ static struct ccu_clk_gate h6_gates[] = { [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), + [CLK_SPI0] = GATE(0x940, BIT(31)), [CLK_SPI1] = GATE(0x944, BIT(31)), @@ -57,6 +62,11 @@ static struct ccu_reset h6_resets[] = { [RST_BUS_UART2] = RESET(0x90c, BIT(18)), [RST_BUS_UART3] = RESET(0x90c, BIT(19)), + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index 553d7c6e550..bebefc9caa1 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -24,6 +24,12 @@ static struct ccu_clk_gate h616_gates[] = { [CLK_BUS_UART4] = GATE(0x90c, BIT(4)), [CLK_BUS_UART5] = GATE(0x90c, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)), + [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)), + [CLK_SPI0] = GATE(0x940, BIT(31)), [CLK_SPI1] = GATE(0x944, BIT(31)), @@ -68,6 +74,12 @@ static struct ccu_reset h616_resets[] = { [RST_BUS_UART4] = RESET(0x90c, BIT(20)), [RST_BUS_UART5] = RESET(0x90c, BIT(21)), + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)), + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)), + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)), + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)), + [RST_BUS_I2C4] = RESET(0x91c, BIT(20)), + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)), [RST_BUS_SPI1] = RESET(0x96c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index ee1e86d22eb..b509bc2de62 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -32,6 +32,11 @@ static struct ccu_clk_gate r40_gates[] = { [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), + [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)), + [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -77,6 +82,11 @@ static struct ccu_reset r40_resets[] = { [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)), + [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)), + [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 29622199fdc..ba58dce5d8d 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -38,6 +40,8 @@ static struct ccu_reset v3s_resets[] = { [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), -- 2.31.1

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