October 2021 - U-Boot

[PATCH 0/4] arm64: dts: rockchip: px30: Linux-5.14-rc3 Sync
by Jagan Teki 09 Oct '21

09 Oct '21

Series sync Linux-5.14-rc3 devicetree files for px30 SoC. Any inputs? Jagan. Jagan Teki (4): arm64: dts: rockchip: px30: Sync Linux PX30.Core files arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi arm64: dts: rockchip: px30: Sync Linux-5.14-rc3 dts(i) engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF arch/arm/dts/Makefile | 5 +- arch/arm/dts/px30-engicam-common.dtsi | 90 +++++++ arch/arm/dts/px30-engicam-ctouch2.dtsi | 22 ++ arch/arm/dts/px30-engicam-edimm2.2.dtsi | 59 +++++ .../px30-engicam-px30-core-ctouch2-of10.dts | 77 ++++++ ...dts => px30-engicam-px30-core-ctouch2.dts} | 4 +- .../dts/px30-engicam-px30-core-edimm2.2.dts | 43 ++++ arch/arm/dts/px30-engicam-px30-core.dtsi | 241 ++++++++++++++++++ arch/arm/dts/px30-evb.dts | 91 +++++-- arch/arm/dts/px30-px30-core-edimm2.2.dts | 21 -- arch/arm/dts/px30-u-boot.dtsi | 10 +- arch/arm/dts/px30.dtsi | 183 ++++++++----- arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 +- arch/arm/mach-rockchip/px30/Kconfig | 8 + board/engicam/px30_core/MAINTAINERS | 6 + configs/px30-core-ctouch2-of10-px30_defconfig | 107 ++++++++ configs/px30-core-ctouch2-px30_defconfig | 4 +- configs/px30-core-edimm2.2-px30_defconfig | 4 +- 18 files changed, 861 insertions(+), 124 deletions(-) create mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts rename arch/arm/dts/{px30-px30-core-ctouch2.dts => px30-engicam-px30-core-ctouch2.dts} (80%) create mode 100644 arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts create mode 100644 arch/arm/dts/px30-engicam-px30-core.dtsi delete mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts create mode 100644 configs/px30-core-ctouch2-of10-px30_defconfig -- 2.25.1

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[PATCH v5 1/2] arm: dts: imx8mq: Add Kontron pitx-imx8m
by Heiko Thiery 09 Oct '21

09 Oct '21

This adds the device tree for the Kontron pitx-imx8m Board. It is a copy of the device tree from the linux kernel sources. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- v5: - no change v4: - no change v3: - no change v2: - no change arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts | 613 +++++++++++++++++++++ 2 files changed, 615 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9438bf735a..9228b1d6c1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -887,7 +887,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ - imx8mq-pico-pi.dtb + imx8mq-pico-pi.dtb \ + imx8mq-kontron-pitx-imx8m.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts new file mode 100644 index 0000000000..f593e4ff62 --- /dev/null +++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts @@ -0,0 +1,613 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree File for the Kontron pitx-imx8m board. + * + * Copyright (C) 2021 Heiko Thiery <heiko.thiery(a)gmail.com> + */ + +/dts-v1/; + +#include "imx8mq.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "Kontron pITX-imx8m"; + compatible = "kontron,pitx-imx8m", "fsl,imx8mq"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &qspi0; + spi1 = &ecspi2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + pcie0_refclk: pcie0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670"; + reg = <0>; + spi-max-frequency = <43000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <280>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-name = "V_0V9_GPU"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw1c_reg: sw1c { + regulator-name = "V_0V9_VPU"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw2_reg: sw2 { + regulator-name = "V_1V1_NVCC_DRAM"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-name = "V_1V0_DRAM"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-name = "NC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-name = "V_0V9_SNVS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-name = "V_0V55_VREF_DDR"; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-name = "V_1V5_CSI"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-name = "V_0V9_PHY"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-name = "V_1V8_PHY"; + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-name = "V_1V8_VDDA"; + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "V_3V3_PHY"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "V_2V8_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + fan-controller@1b { + compatible = "maxim,max6650"; + reg = <0x1b>; + maxim,fan-microvolt = <5000000>; + }; + + rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + sensor@4b { + compatible = "national,lm75b"; + reg = <0x4b>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* M.2 B-key slot */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +/* Intel Ethernet Controller I210/I211 */ +&pcie1 { + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + fsl,max-link-speed = <1>; + status = "okay"; +}; + +&pgc_gpu { + power-supply = <&sw1a_reg>; +}; + +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + spi-max-frequency = <50000000>; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <&sw4_reg>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */ + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */ + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */ + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */ + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */ + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */ + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */ + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */ + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */ + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */ + >; + }; + + pinctrl_reg_usdhc2: regusdhc2gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 + MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 + MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 + MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usb0: usb0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19 + MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- 2.30.0

1 1

[PATCH] mtd: Add SPI Nor Flash chip GD25LQ256D ID
by tekkamanv＠163.com 09 Oct '21

09 Oct '21

From: "yanhong.wang" <yanhong.wang(a)starfivetech.com> Signed-off-by: yanhong.wang <yanhong.wang(a)starfivetech.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4aef1ddd6e..35fa347c44 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -122,6 +122,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- 2.25.4

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[PATCH v2 0/7] arm64: dts: imx8mm: add common -binman.dtsi and further clean-up
by Marcel Ziswiler 09 Oct '21

09 Oct '21

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> With the move to using binman to generate SPL aka u-boot-spl-ddr.bin and U-Boot proper aka u-boot.itb every board now covers such configuration in its own U-Boot specific device tree include. Move the comon part of that configuration to the common imx8mm-u-boot.dtsi include file. The initial patch fixes an issue with intermediate binary naming for the imx8mm-cl-iot-gate. And subsequent patches further clean up that dtsi. This series is based on Peng's binman conversion of late [1], my Verdin iMX8M Mini target refresh [2], Fabio's generating a single bootable flash.bin again for imx8mm-evk [3] and Tim's switching imx8mm_venice to using binman to pack images [4]. This series has been run-time tested on Verdin iMX8M Mini. The other targets were only compile tested. [1] https://marc.info/?l=u-boot&m=163366377832026 [2] https://marc.info/?l=u-boot&m=163365299927718 [3] https://marc.info/?l=u-boot&m=162972343709264 [4] https://marc.info/?l=u-boot&m=162983187605276 Changes in v2: - New patch preparing cl-iot-gate. - Morph common binman dtsi into regular common u-boot dtsi as discussed on mailing list. - Re-based. - Rather than doing that clean-up to the separate binman dtsi now do it to the common u-boot dtsi one. Changes in v1: - This was suggested by Simon on my earlier patch set upon which we decided to first break this up into a common binman dtsi and then subsequently do such further improvements. Marcel Ziswiler (7): imx8mm-cl-iot-gate: fix imximage intermediate binary naming arm64: dts: imx8mm-cl-iot-gate-u-boot.dtsi: alphabetically re-order arm64: dts: imx8mm-cl-iot-gate-u-boot.dtsi: use common imx8mm-u-boot.dtsi arm64: dts: imx8mm: use common binman configuration arm64: dts: imx8mm-u-boot.dtsi: alphabetically re-order properties arm64: dts: imx8mm-u-boot.dtsi: explicitly add spl filename arm64: dts: imx8mm-u-boot.dtsi: improve odd blob-ext naming .../dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi | 209 ++++-------------- arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 188 +++------------- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 123 ----------- arch/arm/dts/imx8mm-u-boot.dtsi | 149 ++++++++++++- arch/arm/dts/imx8mm-venice-u-boot.dtsi | 119 ---------- arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 122 +--------- .../imximage-8mm-lpddr4.cfg | 2 +- 7 files changed, 212 insertions(+), 700 deletions(-) -- 2.26.2

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[PATCH v4 00/15] image: A partial series for the image clean-up
by Simon Glass 09 Oct '21

09 Oct '21

Now that the competing image clean-up has landed and the smoke has cleared, we can come back to this one. This series includes about a third of the original patches, mostly the ones that apply cleanly. It does not reduce the #idefs by as much, but it does make some small code improvements. Further patches can be pulled in once these ones have been reviewed and land. Build here: https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/9251 Changes in v4: - Rebase to master Changes in v3: - Pick up only the first part of the original v2 series Changes in v2: - Add a patch to introduce a memdup() function - Add new abuf_init_set() function - Update abuf_realloc() to return after every case - Use const for abuf_data() and abuf_size() - Make use of memdup() - Add abuf_init_move() - Add comments about the assumptions made by lib_test_abuf_realloc() - Add better comments about why some tests are skipped at present - Correct 'hose' typo Simon Glass (15): lib: Add memdup() Add support for an owned buffer compiler: Add a comment to host_build() zstd: Create a function for use from U-Boot btrfs: Use U-Boot API for decompression image: Avoid switch default in image_decomp() image: Update zstd to avoid reporting error twice gzip: Avoid use of u64 image: Update image_decomp() to avoid ifdefs image: Split board code out into its own file image: Fix up checkpatch warnings in image-board.c image: Split host code out into its own file image: Create a function to do manual relocation image: Avoid #ifdefs for manual relocation image: Remove ifdefs around image_setup_linux() el at common/Makefile | 2 +- common/bootm.c | 16 +- common/image-board.c | 939 +++++++++++++++++++++++++++++ common/image-host.c | 27 + common/image-sig.c | 40 +- common/image.c | 1177 +++---------------------------------- configs/sandbox_defconfig | 1 + fs/btrfs/compression.c | 51 +- include/abuf.h | 159 +++++ include/compiler.h | 8 + include/gzip.h | 8 +- include/linux/string.h | 13 + include/linux/zstd.h | 11 + include/relocate.h | 30 +- lib/Makefile | 1 + lib/abuf.c | 109 ++++ lib/gunzip.c | 28 +- lib/string.c | 13 + lib/zstd/Makefile | 2 +- lib/zstd/zstd.c | 64 ++ test/lib/Makefile | 1 + test/lib/abuf.c | 344 +++++++++++ test/lib/string.c | 32 + tools/Makefile | 1 + 24 files changed, 1887 insertions(+), 1190 deletions(-) create mode 100644 common/image-board.c create mode 100644 common/image-host.c create mode 100644 include/abuf.h create mode 100644 lib/abuf.c create mode 100644 lib/zstd/zstd.c create mode 100644 test/lib/abuf.c -- 2.33.0.685.g46640cef36-goog

2 30

[PATCH v3 00/13] stm32mp1: Support falcon mode with OP-TEE payloads
by Alexandru Gagniuc 08 Oct '21

08 Oct '21

The goal of this project is to to get to linux userspace within a second from power on, and be secure! This is my last full-time day on this project, so I don't expect to do a v4. I chose to use SPL with a FIT payload. We have to add certain logic to SPL, as well as some FDT modifications that would be normally done in u-boot. The boot flow is SPL -> OP-TEE -> Linux Patrick suggested more changes, but I decided against the following: I) Use SPL_OPTEE_IMAGE in mach-stm32mp Kconfig selection I explained in more detail in another email why this is a bad idea. II) Don't use USER2 button for falcon mode. This already exists as "fastboot-gpios", but I wasn't supposed to use it. So I aliased it as "falcon-gpios", but I'm again not supposed to use it because it aliases an existing GPIO. This makes absolutely no sense to me. I need a GPIO for this. This is America! I paid for the button, I intend to use the button! [*] III) Use env_get_yesno("boot_os") to select falcon mode I like this idea, but I feel it is part of the OS/SPL communication mechanism, which is beyond the scope of this series. IV) Use if (serial_getc() == 'c') in spl_start_uboot() I don't like the idea of doing serial input in SPL. V) Move SYS_MMCSD_RAW_MODE_ARGS_* to Kconfig The boot flow herein does not use the ARGS partition. It would destroy the security model to allow an external unsigned devicetree. I don't want to encourage others to use it, and I don't want to waste time with it. I hope the args partition just fizzles away into nothingness. VI) What the heck is "spl export" "spl export" is the u-boot (not SPL) command used to patch the devicetree and save it to the args partition mentioned above. This series avoids "spl export" because: it's a poor security choice (explained above). VII) Wait what? How does the devicetree work? Huh? A complete kernel devicetree is obtained using two methods: a) FDT patching done by SPL to the FIT devicetree b) devicetree overlays from the FIT Both (a) and (b) can be signed. In my specific use case, the bootargs are applied as a devicetree overlay. It's super effective. [*] This is meant to be humorous Changes since v2: - Drop armv7_boot_nonsec() hack - Introduce CONFIG_SPL_FALCON_BOOT_MMCSD - Remove superfluous spl_start_uboot() symbol Changes since v1: - Move SYS_MMCSD_RAW_MODE_KERNEL_SECTOR to Kconfig instead of stm32mp1.h - Create a new defconfig for STM32MP in falcon mode - Rework board_fit_config_name_match() per Patrick's suggestions - Use "u-boot,falcon-gpios" instead of "st,fastboot-gpios" - Only update shadow registers in SPL for BSEC .probe() Alexandru Gagniuc (13): spl: Untagle spl_start_uboot() from spl_mmc.c spl: Move SYS_MMCSD_RAW_MODE_KERNEL_SECTOR to Kconfig stm32mp1: Add support for baudrates higher than 115200 stm32mp1: Add support for falcon mode boot from SD card board: stm32mp1: Implement board_fit_config_name_match() for SPL fdt_support: Implement fdt_ethernet_set_macaddr() arm: stm32mp: bsec: Update OTP shadow registers in SPL arm: stm32mp: Factor out reading MAC address from OTP stm32mp1: spl: Configure MAC address when booting OP-TEE lib: Makefile: Make optee library available in SPL ARM: dts: stm32mp: Add OP-TEE "/firmware" node to SPL dtb stm32mp1: spl: Copy optee nodes to target FDT for OP-TEE payloads ARM: dts: stm32mp: dts: Don't remove OPTEE nodes for DK2 boards README | 4 - arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 6 +- arch/arm/mach-stm32mp/bsec.c | 4 +- arch/arm/mach-stm32mp/cpu.c | 59 ++++-- .../arm/mach-stm32mp/include/mach/sys_proto.h | 3 + arch/arm/mach-stm32mp/spl.c | 3 + board/st/stm32mp1/spl.c | 43 ++++ common/fdt_support.c | 30 +++ common/spl/Kconfig | 16 ++ common/spl/spl.c | 10 +- common/spl/spl_mmc.c | 6 +- configs/am335x_boneblack_vboot_defconfig | 2 + configs/am335x_evm_defconfig | 2 + configs/am335x_igep003x_defconfig | 2 + configs/am335x_shc_defconfig | 2 + configs/am335x_shc_ict_defconfig | 2 + configs/am335x_shc_netboot_defconfig | 2 + configs/am335x_shc_sdboot_defconfig | 2 + configs/am335x_sl50_defconfig | 2 + configs/am3517_evm_defconfig | 2 + configs/am43xx_evm_defconfig | 2 + configs/am43xx_evm_rtconly_defconfig | 2 + configs/am43xx_evm_usbhost_boot_defconfig | 2 + configs/am57xx_evm_defconfig | 2 + configs/devkit8000_defconfig | 2 + configs/display5_defconfig | 2 + configs/display5_factory_defconfig | 2 + configs/dra7xx_evm_defconfig | 2 + configs/gwventana_emmc_defconfig | 2 + configs/gwventana_gw5904_defconfig | 2 + configs/gwventana_nand_defconfig | 2 + configs/igep00x0_defconfig | 2 + configs/imx6dl_mamoj_defconfig | 2 + configs/imx6q_logic_defconfig | 2 + configs/omap35_logic_defconfig | 2 + configs/omap35_logic_somlv_defconfig | 2 + configs/omap3_logic_defconfig | 2 + configs/omap3_logic_somlv_defconfig | 2 + configs/omap4_panda_defconfig | 2 + configs/omap5_uevm_defconfig | 2 + configs/stm32mp15_falcon_defconfig | 183 ++++++++++++++++++ include/configs/brppt1.h | 1 - include/configs/devkit8000.h | 2 - include/configs/display5.h | 1 - include/configs/embestmx6boards.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/imx6-engicam.h | 1 - include/configs/imx6_logic.h | 1 - include/configs/imx6dl-mamoj.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/mccmon6.h | 1 - include/configs/mx6sabreauto.h | 1 - include/configs/mx6sabresd.h | 1 - include/configs/pico-imx6.h | 1 - include/configs/pico-imx6ul.h | 1 - include/configs/pico-imx7d.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/stm32mp1.h | 4 + include/configs/tam3517-common.h | 1 - include/configs/ti_armv7_common.h | 1 - include/configs/vyasa-rk3288.h | 1 - include/configs/xea.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/configs/zynq-common.h | 1 - include/fdt_support.h | 17 ++ lib/Makefile | 2 +- scripts/config_whitelist.txt | 1 - 67 files changed, 415 insertions(+), 57 deletions(-) create mode 100644 configs/stm32mp15_falcon_defconfig -- 2.31.1

1 13

Please pull u-boot-marvell/master
by Stefan Roese 08 Oct '21

08 Oct '21

Hi Tom, please pull this first batch of Marvell MVEBU related patches: ---------------------------------------------------------------- - a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB (Pali) - phy: marvell: a3700: Misc improvements (Pali) - a38x serdes cleanup (Pali) - A3720 PCIe enhancements (Pali & Marek) - mvebu: mvebu_armada-8k: Puzzle M801 enhancements (Robert) - mvebu: x530: Remove custom kwbimage.cfg (Chris) - mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT (Stefan) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=120&view=results Thanks, Stefan The following changes since commit 7a508a7245592ca44b3dc51c0293656dce60d658: Merge tag 'u-boot-amlogic-20211007' of https://source.denx.de/u-boot/custodians/u-boot-amlogic (2021-10-07 09:02:22 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 1ead6c20bd5fb8ea2f6afffb81dde91ea54bf54a: ARM: mvebu: x530: Remove custom kwbimage.cfg (2021-10-08 08:37:55 +0200) ---------------------------------------------------------------- Chris Packham (1): ARM: mvebu: x530: Remove custom kwbimage.cfg Marek Behún (2): arm: a37xx: pci: Cosmetic change arm: a37xx: pci: Update private structure documentation Pali Rohár (17): arm: a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization phy: marvell: a3700: Fix configuring polarity invert bits phy: marvell: a3700: Return correct error code when power up fails arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code arm: mvebu: a38x: serdes: Remove duplicate macro SOC_CTRL_REG arm: mvebu: a38x: serdes: Add comments for hws_pex_config() code arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration arm: mvebu: a38x: serdes: Don't overwrite PCI device ID arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init code arm: mvebu: a38x: serdes: Remove unused PCIe macros and functions arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines arm: a37xx: pci: Fix pcie_advk_link_up() arm: a37xx: pci: Add support for accessing PCI Bridge on root bus arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Robert Marko (2): arm: mvebu: dts: m801: correct CP1 pinctrl arm: mvebu: mvebu_armada-8k: drop Puzzle M801 early init code Stefan Roese (1): arm: mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT arch/arm/dts/armada-37xx.dtsi | 6 +- arch/arm/dts/armada-8040-puzzle-m801.dts | 36 ++- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 297 +-------------------- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 68 +---- .../mach-mvebu/serdes/a38x/high_speed_env_spec.c | 42 ++- board/Marvell/mvebu_armada-8k/board.c | 20 +- board/alliedtelesis/x530/kwbimage.cfg | 12 - drivers/pci/pci-aardvark.c | 199 +++++++++++--- drivers/phy/marvell/comphy_a3700.c | 40 ++- drivers/phy/marvell/comphy_a3700.h | 1 + include/pci.h | 4 + 12 files changed, 239 insertions(+), 487 deletions(-) delete mode 100644 board/alliedtelesis/x530/kwbimage.cfg

2 1

[PATCH v2] mtd: spi-nor-core: Add fixups for s25fs512s
by tkuw584924＠gmail.com 08 Oct '21

08 Oct '21

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> The current S25FS512S support has following issues that need to be fixed. - Non-uniform sectors by factory default. The setting needs to be checked and assign erase hook as needed. - Page size is wrongly advertised in SFDP. - READ_1_1_2 (3Bh/3Ch), READ_1_1_4 (6Bh/6Ch), and PP_1_1_4 (32h/34h) are not supported. - Bank Address Register (BAR) is not supported. In addtion, volatile version of Quad Enable is used for safety. For future use, the fixups is assigned for S25FS-S family. The datasheet can be found in the following link. https://www.cypress.com/file/216376/download Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> --- Changes in v2: - Add #define S25FS_S_RDAR_DUMMY and remove hard-coding - Remove #ifdef CONFIG_SPI_FLASH_BAR drivers/mtd/spi/spi-nor-core.c | 108 +++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f1b4e5ea8e..349b2f3f23 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3099,6 +3099,109 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, } #ifdef CONFIG_SPI_FLASH_SPANSION + +/* Number of dummy cycle for Read Any Register (RDAR) op. */ +#define S25FS_S_RDAR_DUMMY 8 + +static int s25fs_s_quad_enable(struct spi_nor *nor) +{ + return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY); +} + +static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 8 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, + SZ_32K); +} + +static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* Bank Address Register is not supported */ + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR)) + return -ENOTSUPP; + + /* + * Read CR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25fs_s_erase_non_uniform; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25fs_s_default_init(struct spi_nor *nor) +{ + nor->setup = s25fs_s_setup; +} + +static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + + /* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */ + nor->erase_opcode = SPINOR_OP_SE; + nor->mtd.erasesize = nor->info->sector_size; + + if (params->size > SZ_16M) { + ret = nor->write_reg(nor, SPINOR_OP_EN4B, NULL, 0); + if (ret) + return ret; + nor->addr_width = 4; + } else { + nor->addr_width = 3; + } + + /* + * The page_size is set to 512B from BFPT, but it actually depends on + * the configuration register. Look up the CFR3V and determine the + * page_size. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, + S25FS_S_RDAR_DUMMY, &cfr3v); + if (ret) + return ret; + + if (cfr3v & CFR3V_PGMBUF) + params->page_size = 512; + else + params->page_size = 256; + + return 0; +} + +static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_1_1_2 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + /* READ_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25fs_s_quad_enable; +} + +static struct spi_nor_fixups s25fs_s_fixups = { + .default_init = s25fs_s_default_init, + .post_bfpt = s25fs_s_post_bfpt_fixup, + .post_sfdp = s25fs_s_post_sfdp_fixup, +}; + static int s25hx_t_mdp_ready(struct spi_nor *nor) { u32 addr; @@ -3646,6 +3749,11 @@ void spi_nor_set_fixups(struct spi_nor *nor) break; } } + + /* For FS-S (family ID = 0x81) */ + if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && + nor->info->id[5] == 0x81) + nor->fixups = &s25fs_s_fixups; #endif #ifdef CONFIG_SPI_FLASH_S28HS512T -- 2.25.1

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[PATCH 0/3] stm32mp: Attempt to resolve unintended breakage with v2021.10-rc2
by Alexandru Gagniuc 08 Oct '21

08 Oct '21

u-boot v2021.10-rc2 Introduced support for booting from FIP images (not to be confused with FIT) for stm32mp. I am also working on a different boot flow based on u-boot's falcon mode. The changes to accommodate the FIP mode inadvertently broke the falcon flow. This series intends to address that. The core issue is that optee nodes are removed from the u-boot devicetree. For reasons detailed in my other series ("[PATCH v2 00/11] stm32mp1: Support falcon mode with OP-TEE payloads") the "optee" nodes are required. It might seem like an obvious solution to "just re-add the nodes", but I found out it didn't work like that. I couldn't use STM32MP15x_STM32IMAGE to get me back my nodes, because that would have required TFABOOT. What I needed was a new config that more accuratelyreflected the available boot flows. STM32MP15x_STM32IMAGE is a confusing because it conflates image generation with u-boot behavior. I'm proposing replacing it with TFABOOT_FIP_CONTAINER because I think this new config is much easier to understand in layman's terms. I also thinks it maps more elegantly to what STM is trying to do: add a new boot flow. Alexandru Gagniuc (3): stm32mp: Rename FIP config to stm32mp15_tfaboot_fip_defconig arm: Kconfig: Introduce a TFABOOT_FIP_CONTAINER option stm32mp1: Replace STM32MP15x_STM32IMAGE with TFABOOT_FIP_CONTAINER arch/arm/Kconfig | 15 ++++++++++++ arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 9 ++++---- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 9 ++++---- arch/arm/mach-stm32mp/Kconfig | 7 ------ .../cmd_stm32prog/cmd_stm32prog.c | 5 ++-- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 ---- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 2 -- arch/arm/mach-stm32mp/config.mk | 2 +- arch/arm/mach-stm32mp/fdt.c | 4 +--- .../arm/mach-stm32mp/include/mach/stm32prog.h | 2 -- board/st/common/Kconfig | 23 ++++++++++--------- board/st/common/stm32mp_mtdparts.c | 20 +--------------- board/st/stm32mp1/MAINTAINERS | 2 +- board/st/stm32mp1/stm32mp1.c | 6 ++--- ...config => stm32mp15_tfaboot_fip_defconfig} | 1 + configs/stm32mp15_trusted_defconfig | 1 - doc/board/st/stm32mp1.rst | 16 ++++++------- 17 files changed, 54 insertions(+), 74 deletions(-) rename configs/{stm32mp15_defconfig => stm32mp15_tfaboot_fip_defconfig} (99%) -- 2.31.1

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[PATCH v2] mtd: spi-nor: Add support for Spansion S25FL256L
by tkuw584924＠gmail.com 08 Oct '21

08 Oct '21

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> The S25FL256L is a part of the S25FL-L family and has the same feature set as S25FL128L except the density. The datasheet can be found in the following link. https://www.cypress.com/file/316171/download The S25FL256L is 32MB NOR Flash that does not support Bank Address Register. This fixup is activated if CONFIG_SPI_FLASH_BAR is enabled and returns ENOTSUPP in setup() hook to avoid further ops. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> --- Changes in v2: - Merge separated patches into one - Remove #ifdef CONFIG_SPI_FLASH_BAR drivers/mtd/spi/spi-nor-core.c | 19 +++++++++++++++++++ drivers/mtd/spi/spi-nor-ids.c | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f1b4e5ea8e..7572be5e34 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3224,6 +3224,21 @@ static struct spi_nor_fixups s25hx_t_fixups = { .post_bfpt = s25hx_t_post_bfpt_fixup, .post_sfdp = s25hx_t_post_sfdp_fixup, }; + +static int s25fl256l_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + return -ENOTSUPP; /* Bank Address Register is not supported */ +} + +static void s25fl256l_default_init(struct spi_nor *nor) +{ + nor->setup = s25fl256l_setup; +} + +static struct spi_nor_fixups s25fl256l_fixups = { + .default_init = s25fl256l_default_init, +}; #endif #ifdef CONFIG_SPI_FLASH_S28HS512T @@ -3646,6 +3661,10 @@ void spi_nor_set_fixups(struct spi_nor *nor) break; } } + + if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) && + !strcmp(nor->info->name, "s25fl256l")) + nor->fixups = &s25fl256l_fixups; #endif #ifdef CONFIG_SPI_FLASH_S28HS512T diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4aef1ddd6e..11d7d4fcaa 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -227,6 +227,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("s25fl256l", 0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, -- 2.25.1

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