October 2021 - U-Boot

Please pull u-boot-video
by Anatolij Gustschin 10 Oct '21

10 Oct '21

Hi Tom, please pull new video patches. gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/9433 Thanks, Anatolij The following changes since commit 94e922c76a0e1fcdead3359e340f53fd0709a963: Merge branch '2021-10-08-image-cleanups' (2021-10-08 16:02:55 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-video.git tags/video-20211009 for you to fetch changes up to 79c05335a9c101f0b54f2f378d0b08c9b765e1a3: video: move MXS to Kconfig (2021-10-09 19:50:03 +0200) ---------------------------------------------------------------- - add 30bpp support (EFI, simplefb, vidconsole) - fix video console name in CONSOLE_MUX Kconfig help - move mxsfb driver config option to Kconfig - remove unused mx3fb driver ---------------------------------------------------------------- Anatolij Gustschin (3): common: Kconfig: use 'vidconsole' name instead of old 'video' video: remove not used mx3fb driver video: move MXS to Kconfig Mark Kettenis (4): video: Add 30bpp support efi_loader: GOP: Add 30bpp support video: simplefb: Add 30bpp support efi_loader: GOP: Fix 30bpp block transfer support common/Kconfig | 4 +- configs/colibri-imx6ull_defconfig | 1 + configs/colibri_imx7_defconfig | 1 + configs/imxrt1050-evk_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/opos6uldev_defconfig | 1 + configs/pico-imx6ul_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + drivers/video/Kconfig | 6 + drivers/video/Makefile | 1 - drivers/video/cfb_console.c | 11 - drivers/video/mx3fb.c | 906 -------------------------------------- drivers/video/simplefb.c | 12 +- drivers/video/vidconsole-uclass.c | 11 +- include/configs/colibri-imx6ull.h | 3 +- include/configs/colibri_imx7.h | 3 +- include/configs/imxrt1050-evk.h | 1 - include/configs/mx23evk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx6sxsabresd.h | 3 +- include/configs/mx6ul_14x14_evk.h | 1 - include/configs/mx7dsabresd.h | 3 +- include/configs/mxs.h | 5 - include/configs/opos6uldev.h | 1 - include/configs/pico-imx6ul.h | 3 +- include/configs/pico-imx7d.h | 1 - include/video.h | 9 + lib/efi_loader/efi_gop.c | 61 ++- 30 files changed, 110 insertions(+), 948 deletions(-) delete mode 100644 drivers/video/mx3fb.c

2 1

[PATCH v2 0/1] sunxi: Add support for FriendlyARM NanoPi R1S H5
by Chukun Pan 10 Oct '21

10 Oct '21

Hi Andre, > Please don't include not-yet-merged parts in here. Make a verbatim copy > of the version in Linus' tree. Okay, I remove the not-yet-merged parts in dts. > who is reading the MAC address out of the EEPROM, and how > does it land in the kernel (if it lands there)? There is a rtl8153 usb network card on this machine, and it will randomly generate a mac address when it bootup. I think the mac address on the eeprom is for this rtl8153 usb network card. > So why is CONFIG_MACPWR missing from the defconfig? This is my mistake, I'm very sorry about that. Thanks, Chukun Chukun Pan (1): sunxi: Add support for FriendlyARM NanoPi R1S H5 arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 195 +++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/nanopi_r1s_h5_defconfig | 14 ++ 4 files changed, 215 insertions(+) create mode 100644 arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts create mode 100644 configs/nanopi_r1s_h5_defconfig -- 2.17.1

2 2

[PATCH] drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue
by Maninder Singh 10 Oct '21

10 Oct '21

Adds check for memory clock variable before calculating caslat_actual. Set mclk_ps to slowest DIMM supported if mclk_ps is found zero. Signed-off-by: Maninder Singh <maninder.singh_1(a)nxp.com> --- drivers/ddr/fsl/lc_common_dimm_params.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index d299d763db..d738ae3a7c 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2008-2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP Semiconductor + * Copyright 2017-2021 NXP Semiconductor */ #include <common.h> @@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num, unsigned int caslat_actual; unsigned int retry = 16; unsigned int tmp = ~0; - const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); + unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #ifdef CONFIG_SYS_FSL_DDR3 const unsigned int taamax = 20000; #else @@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num, } common_caslat = tmp; + if (!mclk_ps) { + printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n", + outpdimm->tckmin_x_ps); + mclk_ps = outpdimm->tckmin_x_ps; + } + /* validate if the memory clk is in the range of dimms */ if (mclk_ps < outpdimm->tckmin_x_ps) { printf("DDR clock (MCLK cycle %u ps) is faster than " -- 2.17.1

1 0

[PATCH] lz4: Use a private header for U-Boot
by Simon Glass 09 Oct '21

09 Oct '21

At present U-Boot has a header file called lz4.h for its own use. If the host has its own lz4 header file installed (e.g. from the 'liblz4-dev' package) then host builds will use that instead. Move the U-Boot file into its own directory, as is done with various other headers with the same problem. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Here is the azure build https://dev.azure.com/simon0972/u-boot/_build/results?buildId=9&view=results cmd/unlz4.c | 2 +- common/image.c | 2 +- include/{ => u-boot}/lz4.h | 0 lib/lz4_wrapper.c | 2 +- test/compression.c | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) rename include/{ => u-boot}/lz4.h (100%) diff --git a/cmd/unlz4.c b/cmd/unlz4.c index 323ab467173..5f20838e899 100644 --- a/cmd/unlz4.c +++ b/cmd/unlz4.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> #include <env.h> -#include <lz4.h> +#include <u-boot/lz4.h> static int do_unlz4(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/common/image.c b/common/image.c index 5b77113bea3..3fa60b58279 100644 --- a/common/image.c +++ b/common/image.c @@ -61,7 +61,6 @@ DECLARE_GLOBAL_DATA_PTR; #include <display_options.h> #include <gzip.h> #include <image.h> -#include <lz4.h> #include <imximage.h> #include <relocate.h> #include <linux/lzo.h> @@ -71,6 +70,7 @@ DECLARE_GLOBAL_DATA_PTR; #include <lzma/LzmaDec.h> #include <lzma/LzmaTools.h> #include <u-boot/crc.h> +#include <u-boot/lz4.h> static const table_entry_t uimage_arch[] = { { IH_ARCH_INVALID, "invalid", "Invalid ARCH", }, diff --git a/include/lz4.h b/include/u-boot/lz4.h similarity index 100% rename from include/lz4.h rename to include/u-boot/lz4.h diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c index cdbcd05bd43..ebcb5c09a22 100644 --- a/lib/lz4_wrapper.c +++ b/lib/lz4_wrapper.c @@ -6,10 +6,10 @@ #include <common.h> #include <compiler.h> #include <image.h> -#include <lz4.h> #include <linux/kernel.h> #include <linux/types.h> #include <asm/unaligned.h> +#include <u-boot/lz4.h> static u16 LZ4_readLE16(const void *src) { diff --git a/test/compression.c b/test/compression.c index 4cd1be564f3..26d3c80fb5a 100644 --- a/test/compression.c +++ b/test/compression.c @@ -9,11 +9,11 @@ #include <gzip.h> #include <image.h> #include <log.h> -#include <lz4.h> #include <malloc.h> #include <mapmem.h> #include <asm/io.h> +#include <u-boot/lz4.h> #include <u-boot/zlib.h> #include <bzlib.h> -- 2.33.0.882.g93a45727a2-goog

2 1

[PATCH v5 00/10] board: toradex: verdin-imx8mm: target refresh
by Marcel Ziswiler 09 Oct '21

09 Oct '21

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> An assortment of fixes and improvements like an Ethernet PHY configuration fix, DEK blob encapsulation preparation, migration to using binman to pack images, SLEEP_MOCI# enablement, dropping of V1.0 hardware support [1], renaming kernel image variable, using preboot for fdtfile evaluation and watchdog pinctrl fix. Note that this series is applied on top of Peng's Makefile fix [2] as otherwise, it may not quite generate all binman artefacts in the right order as discussed here [3]. [1] https://developer.toradex.com/verdin-sample-phase-over [2] https://marc.info/?l=u-boot&m=162908373904742 [3] https://marc.info/?l=u-boot&m=162945614207220 Changes in v5: - Drop device tree part already done by Marek's patch. - Add another fixes tag as his patch forgot the board code part. - Re-based on top of u-boot-imx, master yet again. Changes in v4: - Add Heiko Schocher's reviewed-by tag. - Fix copyright periods. - Re-based. Changes in v3: - Case fold hex string. - Revert binman part of imx8mm-verdin-u-boot.dtsi to a plain copy from imx8mm-evk and postpone further improvements to after migrating to a common binman config as agreed with Frieder and Simon. - New patch cleaning up include order. - Add Fabio's reviewed-by tag. - Fix patch. - Add missing apalis-imx8 part. - While at it update copyright year resp. period. - Fix closing endif comment. Changes in v2: - Explicitly pass filename to binman when generating binaries as suggested by Heiko. - Use proper intermediate binary u-boot-spl-ddr.bin for imximage as pointed out by Heiko. - Drop first patch ("imx: mkimage_fit_atf: fix legacy image generation") as a similar fix was already refused earlier. - New patch allows booting recent embedded Linux BSPs. - New patch addressing dynamic fdtfile definition. - New patch fixing watchdog pinctrl issue. Igor Opaniuk (1): verdin-imx8mm: use preboot for fdtfile evaluation Marcel Ziswiler (6): imx8m: clean-up kconfig indentation verdin-imx8mm: fix ethernet ARM: dts: imx8mm-verdin: prepare for dek blob encapsulation verdin-imx8mm: switch to use binman to pack images verdin-imx8mm: clean-up include order verdin-imx8mm: fix watchdog pinctrl issue Max Krummenacher (2): verdin-imx8mm: enable sleep_moci output verdin-imx8mm: drop support for v1.0 hardware Oleksandr Suvorov (1): include/configs: apalis-imx8/verdin-imx8mm: rename kernel image variable arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 135 +++++++++++++++++++- arch/arm/dts/imx8mm-verdin.dts | 18 +++ arch/arm/mach-imx/imx8m/Kconfig | 21 +-- board/toradex/verdin-imx8mm/imximage.cfg | 11 +- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 81 +----------- configs/verdin-imx8mm_defconfig | 6 +- doc/board/toradex/verdin-imx8mm.rst | 53 ++++---- include/configs/apalis-imx8.h | 6 +- include/configs/verdin-imx8mm.h | 10 +- 9 files changed, 214 insertions(+), 127 deletions(-) -- 2.26.2

2 11

[PATCH v4 00/10] board: toradex: verdin-imx8mm: target refresh
by Marcel Ziswiler 09 Oct '21

09 Oct '21

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> An assortment of fixes and improvements like an Ethernet PHY configuration fix, DEK blob encapsulation preparation, migration to using binman to pack images, SLEEP_MOCI# enablement, dropping of V1.0 hardware support [1], renaming kernel image variable, using preboot for fdtfile evaluation and watchdog pinctrl fix. Note that this series is applied on top of Peng's Makefile fix [2] as otherwise, it may not quite generate all binman artefacts in the right order as discussed here [3]. [1] https://developer.toradex.com/verdin-sample-phase-over [2] https://marc.info/?l=u-boot&m=162908373904742 [3] https://marc.info/?l=u-boot&m=162945614207220 Changes in v4: - Add Heiko Schocher's reviewed-by tag. - Fix copyright periods. - Re-based. Changes in v3: - Case fold hex string. - Revert binman part of imx8mm-verdin-u-boot.dtsi to a plain copy from imx8mm-evk and postpone further improvements to after migrating to a common binman config as agreed with Frieder and Simon. - New patch cleaning up include order. - Add Fabio's reviewed-by tag. - Fix patch. - Add missing apalis-imx8 part. - While at it update copyright year resp. period. - Fix closing endif comment. Changes in v2: - Explicitly pass filename to binman when generating binaries as suggested by Heiko. - Use proper intermediate binary u-boot-spl-ddr.bin for imximage as pointed out by Heiko. - Drop first patch ("imx: mkimage_fit_atf: fix legacy image generation") as a similar fix was already refused earlier. - New patch allows booting recent embedded Linux BSPs. - New patch addressing dynamic fdtfile definition. - New patch fixing watchdog pinctrl issue. Igor Opaniuk (1): verdin-imx8mm: use preboot for fdtfile evaluation Marcel Ziswiler (6): imx8m: clean-up kconfig indentation verdin-imx8mm: fix ethernet ARM: dts: imx8mm-verdin: prepare for dek blob encapsulation verdin-imx8mm: switch to use binman to pack images verdin-imx8mm: clean-up include order verdin-imx8mm: fix watchdog pinctrl issue Max Krummenacher (2): verdin-imx8mm: enable sleep_moci output verdin-imx8mm: drop support for v1.0 hardware Oleksandr Suvorov (1): include/configs: apalis-imx8/verdin-imx8mm: rename kernel image variable arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 135 +++++++++++++++++++- arch/arm/dts/imx8mm-verdin.dts | 20 ++- arch/arm/mach-imx/imx8m/Kconfig | 21 +-- board/toradex/verdin-imx8mm/imximage.cfg | 11 +- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 81 +----------- configs/verdin-imx8mm_defconfig | 6 +- doc/board/toradex/verdin-imx8mm.rst | 53 ++++---- include/configs/apalis-imx8.h | 6 +- include/configs/verdin-imx8mm.h | 10 +- 9 files changed, 215 insertions(+), 128 deletions(-) -- 2.26.2

3 13

[PATCH v1 2/3] arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node
by Nico Cheng 09 Oct '21

09 Oct '21

Enable sdhci and sdmmc0 node in rk3568-u-boot.dtsi Signed-off-by: Nico Cheng <nico.cheng(a)rock-chips.com> --- arch/arm/dts/rk3568-u-boot.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi index 1570f13fc7..5a80dda275 100644 --- a/arch/arm/dts/rk3568-u-boot.dtsi +++ b/arch/arm/dts/rk3568-u-boot.dtsi @@ -9,6 +9,10 @@ mmc1 = &sdmmc0; }; + chosen { + u-boot,spl-boot-order = &sdhci, &sdmmc0; + }; + dmc: dmc { compatible = "rockchip,rk3568-dmc"; u-boot,dm-pre-reloc; @@ -35,3 +39,16 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&sdmmc0 { + u-boot,dm-spl; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + u-boot,dm-spl; + mmc-hs200-1_8v; + status = "okay"; +}; + -- 2.17.1

2 1

[PATCH v1 1/3] rockchip: Kconfig: Enable SPL support for rk3568
by Nico Cheng 09 Oct '21

09 Oct '21

Enable SPL support in Kconfig and add some related option in rk3568_common.h Signed-off-by: Nico Cheng <nico.cheng(a)rock-chips.com> Signed-off-by: Jason Zhu <jason.zhu(a)rock-chips.com> --- arch/arm/mach-rockchip/Kconfig | 2 ++ configs/evb-rk3568_defconfig | 25 ++++++++++++++++++++++++- include/configs/rk3568_common.h | 4 ++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b164afb529..21b9c381cf 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -260,6 +260,8 @@ config ROCKCHIP_RK3399 config ROCKCHIP_RK3568 bool "Support Rockchip RK3568" select ARM64 + select SUPPORT_SPL + select SPL select CLK select PINCTRL select RAM diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index a102a5a999..a145b71ac2 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -1,20 +1,42 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_TARGET_EVB_RK3568=y CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -28,6 +50,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index b6568917ea..47fc91779e 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -18,6 +18,10 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 #define CONFIG_SYS_LOAD_ADDR 0x00c00800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x4000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #define CONFIG_SYS_SDRAM_BASE 0 -- 2.17.1

2 1

[PATCH v1] clk: rockchip: rk3568: update clks
by Elaine Zhang 09 Oct '21

09 Oct '21

fix up ppll init freq. support tclk_emmc. add freq (26M) for mmc device. fix up the sfc clk rate unit error. Change-Id: I41daa2c1daf55ab07229c1513c6be51b90125cfd Signed-off-by: Elaine Zhang <zhangqing(a)rock-chips.com> --- arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 2 +- drivers/clk/rockchip/clk_rk3568.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 6c59033f03a6..399f19ad21ec 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -14,7 +14,7 @@ #define APLL_HZ (816 * MHz) #define GPLL_HZ (1188 * MHz) #define CPLL_HZ (1000 * MHz) -#define PPLL_HZ (100 * MHz) +#define PPLL_HZ (200 * MHz) /* RK3568 pll id */ enum rk3568_pll_id { diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 553c6c0dafbd..d5e45e7602c7 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1441,6 +1441,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv, switch (rate) { case OSC_HZ: + case 26 * MHz: src_clk = CLK_SDMMC_SEL_24M; break; case 400 * MHz: @@ -1507,7 +1508,7 @@ static ulong rk3568_sfc_get_clk(struct rk3568_clk_priv *priv) case SCLK_SFC_SEL_125M: return 125 * MHz; case SCLK_SFC_SEL_150M: - return 150 * KHz; + return 150 * MHz; default: return -ENOENT; } @@ -1534,7 +1535,7 @@ static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) case 125 * MHz: src_clk = SCLK_SFC_SEL_125M; break; - case 150 * KHz: + case 150 * MHz: src_clk = SCLK_SFC_SEL_150M; break; default: @@ -2406,6 +2407,9 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case BCLK_EMMC: rate = rk3568_emmc_get_bclk(priv); break; + case TCLK_EMMC: + rate = OSC_HZ; + break; #ifndef CONFIG_SPL_BUILD case ACLK_VOP: rate = rk3568_aclk_vop_get_clk(priv); @@ -2582,6 +2586,9 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case BCLK_EMMC: ret = rk3568_emmc_set_bclk(priv, rate); break; + case TCLK_EMMC: + ret = OSC_HZ; + break; #ifndef CONFIG_SPL_BUILD case ACLK_VOP: ret = rk3568_aclk_vop_set_clk(priv, rate); -- 2.17.1

2 1

[PATCH v3 1/2] spi: rockchip_sfc: Implement set_speed logic
by Jon Lin 09 Oct '21

09 Oct '21

Set clock related processing into set_speed logic. And Optimize printing format. Tested-by: Chris Morgan <macromorgan(a)hotmail.com> Signed-off-by: Jon Lin <jon.lin(a)rock-chips.com> --- Changes in v3: - Remove useless headfile - Fix misspelling drivers/spi/rockchip_sfc.c | 82 ++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 43 deletions(-) diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index 4e2b861f22..94222df5ce 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -116,6 +116,7 @@ /* Master trigger */ #define SFC_DMA_TRIGGER 0x80 +#define SFC_DMA_TRIGGER_START 1 /* Src or Dst addr for master */ #define SFC_DMA_ADDR 0x84 @@ -163,14 +164,12 @@ #define SFC_DMA_TRANS_THRETHOLD (0x40) /* Maximum clock values from datasheet suggest keeping clock value under - * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver - * has a minimum of 10MHz and a default of 80MHz which seems reasonable. + * 150MHz. No minimum or average value is suggested. */ -#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000) -#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000) -#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000) +#define SFC_MAX_SPEED (150 * 1000 * 1000) struct rockchip_sfc { + struct udevice *dev; void __iomem *regbase; struct clk hclk; struct clk clk; @@ -197,8 +196,6 @@ static int rockchip_sfc_reset(struct rockchip_sfc *sfc) /* Still need to clear the masked interrupt from RISR */ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); - debug("reset\n"); - return err; } @@ -261,15 +258,11 @@ static int rockchip_sfc_probe(struct udevice *bus) #if CONFIG_IS_ENABLED(CLK) ret = clk_enable(&sfc->hclk); if (ret) - debug("Enable ahb clock fail %s: %d\n", bus->name, ret); + dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret); ret = clk_enable(&sfc->clk); if (ret) - debug("Enable clock fail for %s: %d\n", bus->name, ret); - - ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ); - if (ret) - debug("Could not set sfc clock for %s: %d\n", bus->name, ret); + dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret); #endif ret = rockchip_sfc_init(sfc); @@ -278,7 +271,8 @@ static int rockchip_sfc_probe(struct udevice *bus) sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); sfc->version = rockchip_sfc_get_version(sfc); - sfc->speed = SFC_DEFAULT_SPEED_HZ; + sfc->max_freq = SFC_MAX_SPEED; + sfc->dev = bus; return 0; @@ -411,11 +405,11 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; cmd |= plat->cs << SFC_CMD_CS_SHIFT; - debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", - op->addr.nbytes, op->addr.buswidth, - op->dummy.nbytes, op->dummy.buswidth); - debug("ctrl=%x cmd=%x addr=%llx len=%x\n", - ctrl, cmd, op->addr.val, len); + dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", + op->addr.nbytes, op->addr.buswidth, + op->dummy.nbytes, op->dummy.buswidth); + dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", + ctrl, cmd, op->addr.val, len); writel(ctrl, sfc->regbase + SFC_CTRL); writel(cmd, sfc->regbase + SFC_CMD); @@ -492,7 +486,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d { writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); - writel(0x1, sfc->regbase + SFC_DMA_TRIGGER); + writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); return len; } @@ -500,7 +494,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, const struct spi_mem_op *op, u32 len) { - debug("xfer_poll len=%x\n", len); + dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); if (op->data.dir == SPI_MEM_DATA_OUT) return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); @@ -516,7 +510,7 @@ static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, void *dma_buf; int ret; - debug("xfer_dma len=%x\n", len); + dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); if (op->data.dir == SPI_MEM_DATA_OUT) { dma_buf = (void *)op->data.buf.out; @@ -564,33 +558,16 @@ static int rockchip_sfc_exec_op(struct spi_slave *mem, u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize); int ret; -#if CONFIG_IS_ENABLED(CLK) - if (unlikely(mem->max_hz != sfc->speed)) { - ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ, - (uint)SFC_MAX_SPEED_HZ)); - if (ret < 0) { - printf("set_freq=%dHz fail, check if it's the cru support level\n", - mem->max_hz); - return ret; - } - - sfc->max_freq = mem->max_hz; - sfc->speed = mem->max_hz; - debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed); - } -#endif - rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); - rockchip_sfc_xfer_setup(sfc, mem, op, len); if (len) { - if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD) + if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) ret = rockchip_sfc_xfer_data_dma(sfc, op, len); else ret = rockchip_sfc_xfer_data_poll(sfc, op, len); if (ret != len) { - printf("xfer data failed ret %d dir %d\n", ret, op->data.dir); + dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); return -EIO; } @@ -604,13 +581,32 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent); op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); + return 0; } static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) { - /* We set up speed later for each transmission. - */ + struct rockchip_sfc *sfc = dev_get_plat(bus); + + if (speed > sfc->max_freq) + speed = sfc->max_freq; + + if (speed == sfc->speed) + return 0; + +#if CONFIG_IS_ENABLED(CLK) + int ret = clk_set_rate(&sfc->clk, speed); + + if (ret < 0) { + dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n", + speed); + return ret; + } + sfc->speed = speed; +#else + dev_dbg(sfc->dev, "sfc failed, CLK not support\n"); +#endif return 0; } -- 2.17.1

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