January 2021 - U-Boot

[PATCH 1/1] tools: efivar.py without arguments
by Heinrich Schuchardt 11 Jan '21

11 Jan '21

When tools: efivar.py is called without arguments an error occurs: Traceback (most recent call last): File "tools/efivar.py", line 380, in <module> main() File "tools/efivar.py", line 360, in main args.func(args) AttributeError: 'Namespace' object has no attribute 'func' Show the online help if the arguments do not specify a function. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- tools/efivar.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/efivar.py b/tools/efivar.py index ebfcab2f0a..c40a0fa6c7 100755 --- a/tools/efivar.py +++ b/tools/efivar.py @@ -357,7 +357,10 @@ def main(): signp.set_defaults(func=cmd_sign) args = ap.parse_args() - args.func(args) + if hasattr(args, "func"): + args.func(args) + else: + ap.print_help() def group(a, *ns): for n in ns: -- 2.29.2

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[PATCH] sunxi: display: introduce "sunxi-video" environment variable
by Giulio Benetti 11 Jan '21

11 Jan '21

From: Giulio Benetti <giulio.benetti(a)micronovasrl.com> At the moment you can specify lcd_mode only through hardcoded CONFIG_VIDEO_LCD_MODE but this way, if you have a board with multiple lcds compatible, you have to rebuild u-boot for every single lcd, so let's add sunxi-video environment variable to give the possibility to specify lcd settings at runtime. It's mandatory to "saveenv" after setting sunxi-video variable and then "reset" since sunxi_display driver apply those settings only on startup. Signed-off-by: Giulio Benetti <giulio.benetti(a)micronovasrl.com> --- drivers/video/sunxi/sunxi_display.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index f52aba4d21..99bafc544a 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -1017,6 +1017,10 @@ static bool sunxi_has_lcd(void) { char *lcd_mode = CONFIG_VIDEO_LCD_MODE; + lcd_mode = env_get("sunxi-video"); + if(lcd_mode == NULL) + lcd_mode = CONFIG_VIDEO_LCD_MODE; + return lcd_mode[0] != 0; } @@ -1065,7 +1069,11 @@ void *video_hw_init(void) int i, overscan_offset, overscan_x, overscan_y; unsigned int fb_dma_addr; char mon[16]; - char *lcd_mode = CONFIG_VIDEO_LCD_MODE; + char *lcd_mode; + + lcd_mode = env_get("sunxi-video"); + if(lcd_mode == NULL) + lcd_mode = CONFIG_VIDEO_LCD_MODE; memset(&sunxi_display, 0, sizeof(struct sunxi_display)); -- 2.25.1

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Re: [PATCH v7 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
by Rick Chen 11 Jan '21

11 Jan '21

Hi Padmarao > From: Padmarao Begari [mailto:padmarao.begari@microchip.com] > Sent: Tuesday, December 22, 2020 9:12 PM > To: u-boot(a)lists.denx.de; bmeng.cn(a)gmail.com; Rick Jian-Zhi Chen(陳建志); anup.patel(a)wdc.com; lukas.auer(a)aisec.fraunhofer.de; joe.hershberger(a)ni.com; lukma(a)denx.de; atish.patra(a)wdc.com > Cc: cyril.jean(a)microchip.com; lewis.hanly(a)microchip.com; ivan.griffin(a)emdalo.com; daire.mcnamara(a)emdalo.com; conor.dooley(a)microchip.com; Padmarao Begari > Subject: [PATCH v7 7/7] doc: board: Add Microchip MPFS Icicle Kit doc > > This doc describes the procedure to build, flash and > boot Linux using U-boot on Microchip MPFS Icicle Kit. > > Signed-off-by: Padmarao Begari <padmarao.begari(a)microchip.com> > Reviewed-by: Anup Patel <anup.patel(a)wdc.com> > Reviewed-by: Bin Meng <bin.meng(a)windriver.com> > --- > doc/board/index.rst | 1 + > doc/board/microchip/index.rst | 9 + > doc/board/microchip/mpfs_icicle.rst | 816 ++++++++++++++++++++++++++++ > 3 files changed, 826 insertions(+) > create mode 100644 doc/board/microchip/index.rst > create mode 100644 doc/board/microchip/mpfs_icicle.rst Please check the CI failure item as below: https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/199014 /builds/u-boot/custodians/u-boot-riscv/doc/board/microchip/mpfs_icicle.rst:99:Unexpected indentation. 199make[1]: *** [htmldocs] Error 1 200make: *** [htmldocs] Error 2 201doc/Makefile:69: recipe for target 'htmldocs' failed 202Makefile:2167: recipe for target 'htmldocs' failed Thanks, Rick

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[PATCH] board: amlogic: vim3: ethernet mac fixed from serial
by Artem Lapkin 11 Jan '21

11 Jan '21

Fixed randomly generated ethernet mac address! Used meson_generate_serial_ethaddr for generate mac address from board serial number, if ethaddr variable not defined. Signed-off-by: Artem Lapkin <art(a)khadas.com> --- board/amlogic/vim3/vim3.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c index 09ef39ff30..0315eaf569 100644 --- a/board/amlogic/vim3/vim3.c +++ b/board/amlogic/vim3/vim3.c @@ -133,5 +133,14 @@ int misc_init_r(void) { meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0); + u8 mac_addr[6]; + if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { + meson_generate_serial_ethaddr(); + eth_env_get_enetaddr("ethaddr", mac_addr); + printf("[i] serial eth mac %02X:%02X:%02X:%02X:%02X:%02X\n", + mac_addr[0],mac_addr[1],mac_addr[2], + mac_addr[3],mac_addr[4],mac_addr[5]); + } + return 0; } -- 2.25.1

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[PATCH] sunxi: dram: h6: Improve DDR3 config detection
by Jernej Skrabec 11 Jan '21

11 Jan '21

It turns out that in rare cases, current analytical approach to detect correct DRAM bus width and rank on H6 doesn't work. On some TV boxes with DDR3, incorrect DRAM configuration triggers write leveling error which immediately stops initialization process. Exact reason why this error appears isn't known. However, if correct configuration is used, initalization works without problem. In order to fix this issue, simply try another configuration when any kind of error appears during initialization, not just those related to rank and bus width. Tested-by: Thomas Graichen <thomas.graichen(a)googlemail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec(a)siol.net> --- arch/arm/mach-sunxi/dram_sun50i_h6.c | 95 +++++++++++++++------------- 1 file changed, 51 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 9e34da474798..1cde6132be2c 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -37,9 +37,9 @@ static void mctl_sys_init(struct dram_para *para); static void mctl_com_init(struct dram_para *para); -static void mctl_channel_init(struct dram_para *para); +static bool mctl_channel_init(struct dram_para *para); -static void mctl_core_init(struct dram_para *para) +static bool mctl_core_init(struct dram_para *para) { mctl_sys_init(para); mctl_com_init(para); @@ -51,7 +51,7 @@ static void mctl_core_init(struct dram_para *para) default: panic("Unsupported DRAM type!"); }; - mctl_channel_init(para); + return mctl_channel_init(para); } /* PHY initialisation */ @@ -411,7 +411,7 @@ static void mctl_bit_delay_set(struct dram_para *para) } } -static void mctl_channel_init(struct dram_para *para) +static bool mctl_channel_init(struct dram_para *para) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; @@ -528,46 +528,15 @@ static void mctl_channel_init(struct dram_para *para) clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); udelay(10); - if (readl(&mctl_phy->pgsr[0]) & 0x400000) - { - /* Check for single rank and optionally half DQ. */ - if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) { - para->ranks = 1; - - if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 || - (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2) - para->bus_full_width = 0; - - /* Restart DRAM initialization from scratch. */ - mctl_core_init(para); - return; - } - - /* - * Check for dual rank and half DQ. NOTE: This combination - * is highly unlikely and was not tested. Condition is the - * same as in libdram, though. - */ - if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 && - (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) { - para->bus_full_width = 0; - - /* Restart DRAM initialization from scratch. */ - mctl_core_init(para); - return; - } - - panic("This DRAM setup is currently not supported.\n"); - } - if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { /* Oops! There's something wrong! */ debug("PLL = %x\n", readl(0x3001010)); debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0])); for (i = 0; i < 4; i++) debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0])); - panic("Error while initializing DRAM PHY!\n"); + debug("Error while initializing DRAM PHY!\n"); + + return false; } if (sunxi_dram_is_lpddr(para->type)) @@ -582,13 +551,54 @@ static void mctl_channel_init(struct dram_para *para) writel(0xffffffff, &mctl_com->maer0); writel(0x7ff, &mctl_com->maer1); writel(0xffff, &mctl_com->maer2); + + return true; +} + +static void mctl_auto_detect_rank_width(struct dram_para *para) +{ + /* this is minimum size that it's supported */ + para->cols = 8; + para->rows = 13; + + /* + * Strategy here is to test most demanding combination first and least + * demanding last, otherwise HW might not be fully utilized. For + * example, half bus width and rank = 1 combination would also work + * on HW with full bus width and rank = 2, but only 1/4 RAM would be + * visible. + */ + + debug("testing 32-bit width, rank = 2\n"); + para->bus_full_width = 1; + para->ranks = 2; + if (mctl_core_init(para)) + return; + + debug("testing 32-bit width, rank = 1\n"); + para->bus_full_width = 1; + para->ranks = 1; + if (mctl_core_init(para)) + return; + + debug("testing 16-bit width, rank = 2\n"); + para->bus_full_width = 0; + para->ranks = 2; + if (mctl_core_init(para)) + return; + + debug("testing 16-bit width, rank = 1\n"); + para->bus_full_width = 0; + para->ranks = 1; + if (mctl_core_init(para)) + return; + + panic("This DRAM setup is currently not supported.\n"); } static void mctl_auto_detect_dram_size(struct dram_para *para) { /* TODO: non-(LP)DDR3 */ - /* Detect rank number and half DQ by the code in mctl_channel_init. */ - mctl_core_init(para); /* detect row address bits */ para->cols = 8; @@ -652,10 +662,6 @@ unsigned long sunxi_dram_init(void) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct dram_para para = { .clk = CONFIG_DRAM_CLK, - .ranks = 2, - .cols = 11, - .rows = 14, - .bus_full_width = 1, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 .type = SUNXI_DRAM_TYPE_LPDDR3, .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, @@ -673,6 +679,7 @@ unsigned long sunxi_dram_init(void) setbits_le32(0x7010310, BIT(8)); clrbits_le32(0x7010318, 0x3f); + mctl_auto_detect_rank_width(&para); mctl_auto_detect_dram_size(&para); mctl_core_init(&para); -- 2.29.2

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[PATCH v3 1/2] trace: select TIMER_EARLY to avoid infinite recursion
by Pragnesh Patel 10 Jan '21

10 Jan '21

When tracing functions is enabled this adds calls to __cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced functions. __cyg_profile_func_enter() and __cyg_profile_func_exit() invoke timer_get_us() to record the entry and exit time. initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an indefinite recursion. So select TIMER_EARLY when tracing got enabled. Signed-off-by: Pragnesh Patel <pragnesh.patel(a)sifive.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Rick Chen <rick(a)andestech.com> --- Changes in v3: - no change Changes in v2: - new patch lib/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/Kconfig b/lib/Kconfig index 7673d2e4e0..671386963a 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -210,6 +210,7 @@ config BITREVERSE config TRACE bool "Support for tracing of function calls and timing" imply CMD_TRACE + select TIMER_EARLY help Enables function tracing within U-Boot. This allows recording of call traces including timing information. The command can write data to -- 2.17.1

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Re: [PATCH v2 2/2] riscv: timer: Add support for an early timer
by Rick Chen 10 Jan '21

10 Jan '21

> From: Pragnesh Patel [mailto:pragnesh.patel@sifive.com] > Sent: Tuesday, December 22, 2020 2:23 PM > To: u-boot(a)lists.denx.de > Cc: atish.patra(a)wdc.com; palmerdabbelt(a)google.com; bmeng.cn(a)gmail.com; paul.walmsley(a)sifive.com; anup.patel(a)wdc.com; sagar.kadam(a)sifive.com; Rick Jian-Zhi Chen(陳建志); pragnesh.patel(a)openfive.com; Pragnesh Patel; Palmer Dabbelt; Sean Anderson; Claudiu Beznea; Simon Glass > Subject: [PATCH v2 2/2] riscv: timer: Add support for an early timer > > Added support for timer_early_get_count() and timer_early_get_rate() > This is mostly useful in tracing. > > Signed-off-by: Pragnesh Patel <pragnesh.patel(a)sifive.com> > --- > > Changes in v2: > - make u-boot compile for qemu (include/configs/qemu-riscv.h) > > drivers/timer/andes_plmt_timer.c | 21 ++++++++++++++++++++- > drivers/timer/riscv_timer.c | 21 ++++++++++++++++++++- > drivers/timer/sifive_clint_timer.c | 21 ++++++++++++++++++++- > include/configs/ax25-ae350.h | 5 +++++ > include/configs/qemu-riscv.h | 5 +++++ > include/configs/sifive-fu540.h | 5 +++++ > 6 files changed, 75 insertions(+), 3 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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RK3399 SPI flash boot
by Johnny Sorocil 09 Jan '21

09 Jan '21

I am trying to boot from SOM-RK3399v2 board. Can't get to u-boot shell, but TPL and SPL seems to be working. Booting from uSD or eMMC works. Reading SPI flash it and diff-ing hex dumps shows nothing weird. SPI image is created with following commands: make clean distclean && make <my custom conf based on rockpro64> && make -j6 tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl-dtb.bin:spl/u-boot-spl-dtb.bin spl.bin dd if=spl.bin of=spl-out.bin bs=128K conv=sync cat spl-out.bin u-boot-dtb.img > out.bin dd if=out.bin of=out.bin.pad bs=4M conv=sync dd if=out.bin.pad of=/dev/mtdblock0 conv=sync I have also tried dd-ing spl-out.bin with u-boot.itb or u-boot.img (with 384 kB offset) directly to SPI device - but result is the same. Same results are also with pinebook-pro-rk3399_defconfig. ls -lh <files> -rw-r--r-- 1 root root 1.2M Jan 9 01:11 out.bin -rw-r--r-- 1 root root 4.0M Jan 9 01:11 out.bin.pad -rw-r--r-- 1 root root 328K Jan 9 01:11 spl.bin -rw-r--r-- 1 root root 384K Jan 9 01:11 spl-out.bin -rw-r--r-- 1 root root 92K Jan 9 01:10 spl/u-boot-spl-dtb.bin -rw-r--r-- 1 root root 70K Jan 9 01:10 tpl/u-boot-tpl-dtb.bin -rw-r--r-- 1 root root 793K Jan 9 01:09 u-boot-dtb.img -rw-r--r-- 1 root root 793K Jan 9 01:09 u-boot.img -rw-r--r-- 1 root root 945K Jan 9 01:09 u-boot.itb du -h <files> 41K tpl/u-boot-tpl-dtb.bin 65K spl/u-boot-spl-dtb.bin 117K spl.bin 117K spl-out.bin 529K u-boot-dtb.img 529K u-boot.img 585K u-boot.itb 637K out.bin 637K out.bin.pad grep OFFS .config CONFIG_ENV_OFFSET=0x3F8000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_ERR_PTR_OFFSET=0x0 CONFIG_FIT_EXTERNAL_OFFSET=0x0 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x0 # CONFIG_TRANSLATION_OFFSET is not set Got same results with native build (on arm64) and cross-compile (amd64). UART console shows: U-Boot TPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 08 2021 - 14:43:26) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 08 2021 - 14:43:26 -0600) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from SPI <hang> Booting from SD and trying to write to the SPI flash from u-boot shell: => sf probe SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 ${kernel_addr_r} u-boot.itb 970832 bytes read in 60 ms (15.4 MiB/s) => sf write $kernel_addr_r 0x60000 ${filesize} device 0 offset 0x60000, size 0xed050 DH@b@N`@`@`@NL`@H@@N`01& 8" Bpteb x6 00 Written: ERROR-110 => load mmc 1:1 ${kernel_addr_r} u-boot.img 814892 bytes read in 51 ms (15.2 MiB/s) => sf write $kernel_addr_r 0x60000 ${filesize} device 0 offset 0x60000, size 0xc6f2c DH@b@N`@`@`@NL`@H@@N`00 00 @pteb x6 00 Wbitten:EROR -110 => load mmc 1:1 ${kernel_addr_r} u-boot-dtb.img 814892 bytes read in 51 ms (15.2 MiB/s) => sf write $kernel_addr_r 0x60000 ${filesize} device 0 offset 0x60000, size 0xc6f2c DH@b@N`@`@`@NL`@H@@N`00! 002@qt@s 0p60000 ritten: ERROR -110 If I skip dd-ing u-boot.itb part then UART console shows: dd if=spl.bin of=/dev/mtdblock0 conv=fsync U-Boot TPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 09 2021 - 16:43:10) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2021.01-rc5-00011-gc8f2a060a1 (Jan 09 2021 - 16:43:10 +0100) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from SPI Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Booting from SPI flash with extra logs: grep _LOG_ .config CONFIG_LOG_MAX_LEVEL=7 CONFIG_LOG_DEFAULT_LEVEL=7 CONFIG_LOG_CONSOLE=y # CONFIG_LOG_SYSLOG is not set CONFIG_SPL_LOG_MAX_LEVEL=7 CONFIG_SPL_LOG_CONSOLE=y CONFIG_TPL_LOG_MAX_LEVEL=7 CONFIG_TPL_LOG_CONSOLE=y # CONFIG_LOG_ERROR_RETURN is not set UART console: common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() common/spl/spl.c:601-board_init_r() >>TPL: board_init_r() <repeats for minutes...>

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[PATCH v1] sunxi: board: Move USB ethernet initialization to board_late_init()
by Andy Shevchenko 08 Jan '21

08 Jan '21

For the sake of consistency (*) and order of initialization, i.e. after we have got the ethernet address, interrupt and timer initialized, try to initialize USB ethernet gadget. *) for example, zynqmp uses same order. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- arch/arm/Kconfig | 1 + board/sunxi/board.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5903c093705a..3d9be8a7507e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1045,6 +1045,7 @@ config ARCH_SUNXI select SPL_USE_TINY_PRINTF select USE_PREBOOT select SYS_RELOC_GD_ENV_ADDR + imply BOARD_LATE_INIT imply CMD_DM imply CMD_GPT imply CMD_UBI if MTD_RAW_NAND diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 708a27ed78e9..77e464718846 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -890,6 +890,11 @@ int misc_init_r(void) setup_environment(gd->fdt_blob); + return 0; +} + +int board_late_init(void) +{ #ifdef CONFIG_USB_ETHER usb_ether_init(); #endif -- 2.29.2

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[PATCH v1 0/3] arm: xea: Regression fixes for i.MX28 based XEA board
by Lukasz Majewski 08 Jan '21

08 Jan '21

This patch set provides boot regression fix and some enhancements for i.MX28 based XEA board. The most notably one is the disablement of CONFIG_SPL_OF_PLATDATA_PARENT which prevents from having the board bricked. Lukasz Majewski (3): xea: spl: Disable pull UP for GPIO0_2{35} xea: config: Use CONFIG_PREBOOT from Kconfig xea: config: Disable CONFIG_SPL_OF_PLATDATA_PARENT on XEA (imx28) board/liebherr/xea/spl_xea.c | 2 +- configs/imx28_xea_defconfig | 3 +++ include/configs/xea.h | 1 - 3 files changed, 4 insertions(+), 2 deletions(-) -- 2.20.1

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