January 2021 - U-Boot

[PATCH 00/15] gpio: Update and simplify the uclass API
by Simon Glass 21 Jan '21

21 Jan '21

At present the GPIO uclass mirrors what was in U-Boot before driver model. It works well in most cases but is becoming cumbersome with things like pull-up/down and drive strength. In those cases it is easier for the driver to deal with all the flags at one, rather than piece by piece. In fact the current API does not officially have a method for adjusting anything other than the direction flags. While set_dir_flags() and get_dir_flags() do in fact support changing other flags, this is not documented. Secondly, set_dir_flags actually ORs the current flags with the new ones so it is not possible to clear flags. It seems better to use a clr/set interface (bit clear followed by OR) to provide more flexibility. Finally, direction_input() and direction_output() are really just the same thing as set_dir_flags(), with a different name. We currently use the latter if available, failing back to the former. But it makes sense to deprecate the old methods. This series makes the above changes. Existing drivers are mostly left alone, since they should continue to operate as is. The sandbox driver is updated to add the required new tests and the x86 driver is switched over to the new API. The STM32 driver should be checked to make sure the open source/open drain features still work as intended. Simon Glass (15): gpio: Disable functions not used with of-platdata dm: gpio: Rename set_dir_flags() method to update_flags() dm: gpio: Rename get_dir_flags() method to get_flags() gpio: Rename dm_gpio_get_dir_flags() to dm_gpio_get_flags() gpio: Drop dm_gpio_set_dir() gpio: sandbox: Rename GPIO dir_flags to flags gpio: sandbox: Use a separate flag for the value gpio: sandbox: Fully separate pin value from output value gpio: sandbox: Make sandbox_gpio_set_flags() set all flags dm: gpio: Add a way to update flags gpio: Replace direction_input() and direction_output() gpio: Use an 'ops' variable everywhere gpio: x86: Drop the deprecated methods in intel_gpio gpio: sandbox: Track whether a GPIO is driven gpio: Add a way to read 3-way strapping pins arch/sandbox/include/asm/gpio.h | 17 +- arch/x86/include/asm/intel_pinctrl_defs.h | 5 + drivers/gpio/gpio-uclass.c | 228 ++++++++++++++----- drivers/gpio/intel_gpio.c | 72 +++--- drivers/gpio/sandbox.c | 137 ++++++++---- drivers/gpio/stm32_gpio.c | 14 +- drivers/pinctrl/pinctrl-stmfx.c | 14 +- include/asm-generic/gpio.h | 130 +++++++++-- test/dm/gpio.c | 261 +++++++++++++++++++--- 9 files changed, 663 insertions(+), 215 deletions(-) -- 2.30.0.284.gd98b1dd5eaa7-goog

3 33

arm: rk3399: add support nanopi r4s
by alex tian 21 Jan '21

21 Jan '21

>From e4f4c74b1f0e2bb7205a7b083fab6faf0b65c1ba Mon Sep 17 00:00:00 2001 From: Xiaobo Tian <peterwillcn(a)gmail.com> Date: Sat, 26 Dec 2020 00:13:37 +0800 Subject: [PATCH] arm: rk3399: add support nanopi r4s Signed-off-by: Xiaobo Tian <peterwillcn(a)gmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 7 ++ arch/arm/dts/rk3399-nanopi-r4s.dts | 120 +++++++++++++++++++++ configs/nanopi-r4s-rk3399_defconfig | 62 +++++++++++ 4 files changed, 190 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts create mode 100644 configs/nanopi-r4s-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd47e408f8..8d42c37fcb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,6 +92,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3399-nanopi-r4s.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi new file mode 100644 index 0000000000..05f785e662 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Xiaobo <tianxiaobo(a)gelaxy.io> + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts new file mode 100644 index 0000000000..5c65447f0e --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-r4s.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (C) 2020 Xiaobo <tianxiaobo(a)gelaxy.io> + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* FIXME: adjust leveles for the connected fan */ + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vdd_5v>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "disabled"; +}; + +&fusb0 { + status = "disabled"; +}; + +&leds { + lan_led: led-1 { + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:lan"; + }; + + wan_led: led-2 { + gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + label = "nanopi-r4s:green:wan"; + }; +}; + +&leds_gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&pcie0 { + max-link-speed = <1>; + num-lanes = <1>; + vpcie3v3-supply = <&vcc3v3_sys>; +}; + +&sdhci { + status = "disabled"; +}; + +&sdio0 { + status = "disabled"; +}; + +&sdmmc { + host-index-min = <1>; +}; + +&u2phy0_host { + phy-supply = <&vdd_5v>; +}; + +&u2phy1_host { + status = "disabled"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_sys>; +}; diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig new file mode 100644 index 0000000000..0a3c28b012 --- /dev/null +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.30.0

2 2

[PATCH 1/1] cmd: CMD_ACPI depends on ACPIGEN
by Heinrich Schuchardt 21 Jan '21

21 Jan '21

Trying to compile qemu-x86_64_defconfig with CONFIG_CMD_ACPI=y and CONFIG_ACPIGEN=n fails with ld.bfd: cmd/built-in.o: in function `do_acpi_items': cmd/acpi.c:162: undefined reference to `acpi_dump_items' Add the missing configuration dependency. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 0625ee4050..928a2a0a2d 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -84,7 +84,8 @@ menu "Info commands" config CMD_ACPI bool "acpi" - default y if ACPIGEN + depends on ACPIGEN + default y help List and dump ACPI tables. ACPI (Advanced Configuration and Power Interface) is used mostly on x86 for providing information to the -- 2.29.2

3 5

[PATCH v2 0/2] Add Rockchip dwc-based PCIe controller and PHY support
by Shawn Lin 21 Jan '21

21 Jan '21

This patchset add Rockchip dwc-based PCIe controller and PHY found on RK356X platforms. It could support Gen3 as a root complex. Changes in v2: - reoder header file - add comment - reorder the header file - add more comment - use clrsetbits_le32 and setbits_le32 - fix other various suggestions from Simon Shawn Lin (2): phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY pci: Add Rockchip dwc based PCIe controller driver drivers/pci/Kconfig | 9 + drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_rockchip.c | 877 ++++++++++++++++++ drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 157 ++++ 6 files changed, 1054 insertions(+) create mode 100644 drivers/pci/pcie_dw_rockchip.c create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -- 2.17.1

3 5

[PATCH v2] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
by David Bauer 21 Jan '21

21 Jan '21

This adds support for the NanoPi R2S from FriendlyArm. Rockchip RK3328 SoC 1GB DDR4 RAM Gigabit Ethernet (WAN) Gigabit Ethernet (USB3) (LAN) USB 2.0 Host Port MicroSD slot Reset button WAN - LAN - SYS LED Signed-off-by: David Bauer <mail(a)david-bauer.net> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 40 +++ arch/arm/dts/rk3328-nanopi-r2s.dts | 370 +++++++++++++++++++++ board/rockchip/evb_rk3328/MAINTAINERS | 7 + configs/nanopi-r2s-rk3328_defconfig | 98 ++++++ 5 files changed, 516 insertions(+) create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts create mode 100644 configs/nanopi-r2s-rk3328_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd47e408f8..ea5b5586cc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ + rk3328-nanopi-r2s.dtb \ rk3328-roc-cc.dtb \ rk3328-rock64.dtb \ rk3328-rock-pi-e.dtb diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi new file mode 100644 index 0000000000..9e2ced1541 --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd + * (C) Copyright 2020 David Bauer + */ + +#include "rk3328-u-boot.dtsi" +#include "rk3328-sdram-ddr4-666.dtsi" +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; +}; + +&sdmmc0m1_gpio { + u-boot,dm-spl; +}; + +&pcfg_pull_up_4ma { + u-boot,dm-spl; +}; + +/* Need this and all the pinctrl/gpio stuff above to set pinmux */ +&vcc_sd { + u-boot,dm-spl; +}; + +&gmac2io { + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; +}; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts new file mode 100644 index 0000000000..5445c5cb3d --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 David Bauer <mail(a)david-bauer.net> + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "rk3328.dtsi" + +/ { + model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; + + lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:lan"; + }; + + sys_led: led-1 { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:red:sys"; + }; + + wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:wan"; + }; + }; + + vcc_io_sdio: sdmmcio-regulator { + compatible = "regulator-gpio"; + enable-active-high; + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdio_vcc_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_io_sdio"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-settling-time-us = <5000>; + regulator-type = "voltage"; + startup-delay-us = <2000>; + states = <1800000 0x1 + 3300000 0x0>; + vin-supply = <&vcc_io_33>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_gpio>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io_33>; + }; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; + pinctrl-names = "default"; + rx_delay = <0x18>; + snps,aal; + tx_delay = <0x24>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c915", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pmic_int_l>; + pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vdd_5v>; + vcc2-supply = <&vdd_5v>; + vcc3-supply = <&vdd_5v>; + vcc4-supply = <&vdd_5v>; + vcc5-supply = <&vcc_io_33>; + vcc6-supply = <&vdd_5v>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io_33: DCDC_REG4 { + regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + pmuio-supply = <&vcc_io_33>; + vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io_sdio>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io_33>; + vccio6-supply = <&vcc_io_33>; + status = "okay"; +}; + +&pinctrl { + button { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet-phy { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdio_vcc_pin: sdio-vcc-pin { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_io_sdio>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index e7dd59ff4e..14fda46e8f 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +NANOPI-R2S-RK3328 +M: David Bauer <mail(a)david-bauer.net> +S: Maintained +F: configs/nanopi-r2s-rk3328_defconfig +F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +F: arch/arm/dts/rk3328-nanopi-r2s.dts + ROC-RK3328-CC M: Loic Devulder <ldevulder(a)suse.com> M: Chen-Yu Tsai <wens(a)csie.org> diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig new file mode 100644 index 0000000000..2f67439f78 --- /dev/null +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYSINFO=y +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.30.0

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[PATCH] rockchip: pinebook-pro: fix SPI flash detection
by Marcin Juszkiewicz 21 Jan '21

21 Jan '21

Copy changes done to rockpro64 in commit c180e2939d3ccb43f89565d6660a0d6f912712b6 ("rockchip: rockpro64: fix boot from SPI flash on spi1") Remove the spi0 alias, set the default bus for SPI flash to 1, and enable support for numbered aliases in SPL so that it uses the same bus numbering as U-Boot proper. This fixes detection of SPI flash on the pinebook-pro board. Signed-off-by: Marcin Juszkiewicz <marcin(a)juszkiewicz.com.pl> --- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4 ---- configs/pinebook-pro-rk3399_defconfig | 2 ++ 2 files changed, 2 insertions(+), 4 deletions(-) diff --git arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi index ded7db0aef..ee3b98698e 100644 --- arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +++ arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -7,10 +7,6 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { - aliases { - spi0 = &spi1; - }; - chosen { u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; }; diff --git configs/pinebook-pro-rk3399_defconfig configs/pinebook-pro-rk3399_defconfig index 8fbd7280ac..a471c3e06a 100644 --- configs/pinebook-pro-rk3399_defconfig +++ configs/pinebook-pro-rk3399_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_DM_KEYBOARD=y @@ -49,6 +50,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y -- 2.29.2

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[PATCH 1/1] cmd: change suppress newline in echo command
by Heinrich Schuchardt 21 Jan '21

21 Jan '21

By default the echo command emits its arguments followed by a line feed. If any of the arguments contains the sub-string "\c", the line feed is suppressed. This does not match shells used in Linux and BSD where the first argument has to be -n to suppress the line feed. The hush shell interferes with the parsing of backslashes. E.g. in the following command line quadruple backslashes are required for suppressing the line feed: for i in 1 2 3; do for j in 4 5; do echo \\\\c ${i}${j}; done; echo; done; To avoid unexpected behavior the patch changes echo to use -n as first argument to suppress the line feed. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/echo.c | 49 ++++++++++++++++++------------------------------- 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/cmd/echo.c b/cmd/echo.c index d02a4cfd58..fda844ee9d 100644 --- a/cmd/echo.c +++ b/cmd/echo.c @@ -10,47 +10,34 @@ static int do_echo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int i; - int putnl = 1; - - for (i = 1; i < argc; i++) { - char *p = argv[i]; - char *nls; /* new-line suppression */ + int i = 1; + bool space = false; + bool newline = true; + + if (argc > 1) { + if (!strcmp(argv[1], "-n")) { + newline = false; + ++i; + } + } - if (i > 1) + for (; i < argc; ++i) { + if (space) { putc(' '); - - nls = strstr(p, "\\c"); - if (nls) { - char *prenls = p; - - putnl = 0; - /* - * be paranoid and guess that someone might - * say \c more than once - */ - while (nls) { - *nls = '\0'; - puts(prenls); - *nls = '\\'; - prenls = nls + 2; - nls = strstr(prenls, "\\c"); - } - puts(prenls); - } else { - puts(p); } + puts(argv[i]); + space = true; } - if (putnl) + if (newline) putc('\n'); return 0; } U_BOOT_CMD( - echo, CONFIG_SYS_MAXARGS, 1, do_echo, + echo, CONFIG_SYS_MAXARGS, 1, do_echo, "echo args to console", - "[args..]\n" - " - echo args to console; \\c suppresses newline" + "[-n] [args..]\n" + " - echo args to console; -n suppresses newline" ); -- 2.29.2

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[PATCH v2 00/11] tpm: Support using TPM1 and TPM2 from a single API
by Simon Glass 21 Jan '21

21 Jan '21

At present if an application wants to be written so it can work with both TPMv1.2 and TPM2 it must use two different APIs. This is inconvenient since it requires adding code to deal with the mismatch between the two. It would be better to have a common API that all boards could share. This series provides a simple API the covers some basic features and implements them for both TPM standards. Changes in v2: - Add comments for the offset value - Add definition of TPM2_RC_NV_DEFINED return code Simon Glass (11): tpm: Don't include cr50 in TPL/SPL tpm: Use logging in the uclass tpm: Add debugging of request in tpm_sendrecv_command() tpm: Add an API that can support v1.2 and v2 tpm: Switch TPMv1 over to use the new API tpm: Add a basic API implementation for TPMv2 tpm: Reduce duplication in a few functions tpm: Add an implementation of define_space tpm: Add TPM2 support for read/write values tpm: Add TPM2 support for write_lock tpm: Allow disabling platform hierarchy with TPM2 board/gdsys/a38x/controlcenterdc.c | 4 +- board/gdsys/a38x/hre.c | 28 +-- board/gdsys/a38x/keyprogram.c | 8 +- board/gdsys/mpc8308/gazerbeam.c | 4 +- board/gdsys/p1022/controlcenterd-id.c | 36 +-- cmd/tpm-v1.c | 25 +- cmd/tpm_test.c | 40 ++-- drivers/tpm/Makefile | 2 +- drivers/tpm/cr50_i2c.c | 4 +- drivers/tpm/tpm-uclass.c | 8 +- include/tpm-common.h | 3 + include/tpm-v1.h | 76 +++--- include/tpm-v2.h | 81 +++++++ include/tpm_api.h | 322 ++++++++++++++++++++++++++ lib/Makefile | 1 + lib/tpm-common.c | 11 +- lib/tpm-v1.c | 115 +++++---- lib/tpm-v2.c | 199 +++++++++++++++- lib/tpm_api.c | 285 +++++++++++++++++++++++ 19 files changed, 1069 insertions(+), 183 deletions(-) create mode 100644 include/tpm_api.h create mode 100644 lib/tpm_api.c -- 2.30.0.296.g2bfb1c46d8-goog

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[PATCH v4 00/23] Add support for MediaTek MT7620 SoC - v4
by Weijie Gao 21 Jan '21

21 Jan '21

This series will add support for MediaTek MT7620 SoC with two reference boards and related drivers. The MediaTek MT7620 is a 2x2 802.11n WiSoC integrating a MIPS 24KEc processor running at a maximum frequency of 620MHz. This chip can be found in many wireless routers. This series add all basic drivers which are useful in u-boot, like usb, sdhc, ethernet, spi and serial. Booting from NAND is currently unsupported. Thanks, Weijie v4 changes: - Remove unused code in drivers/serial/serial.c - Fix plat->cfg.f_max of mtk-sd driver v3 changes: - Use bool instead of int in for mt7620_spi_set_cs() mt7620_spi.c - Add detail comments for mt7620_wdt_expire_now() in mt7620_wdt.c - Remove duplicated dev field in mt7620-usb-phy.c - Add fixes for mtk-sd (fix sclk cycles shift value, assign plat->cfg.f_max) v2 changes: - Remove non-DM code from mt7620-serial driver, and use of-platdata instead - Fix dev_err related compilation error - Add expire_now for mt7620-wdt - Remove use of common.h Weijie Gao (23): mips: dts: switch to board defines for dtb for mtmips mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectory mips: mtmips: select SYSRESET for mt7628 only mips: mtmips: fix dram size detection in dram_init mips: enable _machine_restart for spl mips: mtmips: add support to initialize SDRAM mips: mtmips: add support for MediaTek MT7620 SoC mips: mtmips: add two reference boards for mt7620 configs: mtmips: refresh for mt7628 based boards serial: add uart driver for MediaTek MT7620 SoC clk: add clock driver for MediaTek MT7620 SoC reset: mtmips: add reset controller support for MediaTek MT7620 SoC pinctrl: mtmips: add support for MediaTek MT7620 SoC watchdog: add watchdog driver for MediaTek MT7620 SoC gpio: add GPIO controller driver for MediaTek MT7620 SoC spi: add spi controller support for MediaTek MT7620 SoC phy: add USB PHY driver for MediaTek MT7620 SoC net: add ethernet driver for MediaTek MT7620 SoC mmc: mtk-sd: fix sclk cycles shift value mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCs mmc: mtk-sd: assign plat->cfg.f_max with a correct value reset: reset-mtmips: add DM_FLAG_PRE_RELOC flag MAINTAINERS: add maintainer for MediaTek MIPS platform MAINTAINERS | 23 + arch/mips/Kconfig | 1 - arch/mips/cpu/cpu.c | 2 +- arch/mips/dts/Makefile | 7 +- arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts | 100 ++ arch/mips/dts/mediatek,mt7620-rfb.dts | 97 ++ arch/mips/dts/mt7620-u-boot.dtsi | 14 + arch/mips/dts/mt7620.dtsi | 296 ++++ arch/mips/mach-mtmips/Kconfig | 72 +- arch/mips/mach-mtmips/Makefile | 1 + arch/mips/mach-mtmips/cpu.c | 5 +- arch/mips/mach-mtmips/ddr_init.c | 59 + arch/mips/mach-mtmips/include/mach/ddr.h | 4 + .../mach-mtmips/include/mach/mt7620-sysc.h | 54 + arch/mips/mach-mtmips/mt7620/Kconfig | 71 + arch/mips/mach-mtmips/mt7620/Makefile | 10 + arch/mips/mach-mtmips/mt7620/dram.c | 113 ++ arch/mips/mach-mtmips/mt7620/init.c | 193 +++ arch/mips/mach-mtmips/mt7620/lowlevel_init.S | 53 + arch/mips/mach-mtmips/mt7620/mt7620.h | 103 ++ arch/mips/mach-mtmips/mt7620/serial.c | 36 + arch/mips/mach-mtmips/mt7620/sysc.c | 172 +++ arch/mips/mach-mtmips/mt7628/Kconfig | 53 + board/mediatek/mt7620/Kconfig | 12 + board/mediatek/mt7620/MAINTAINERS | 9 + board/mediatek/mt7620/Makefile | 3 + board/mediatek/mt7620/board.c | 6 + .../gardena-smart-gateway-mt7688_defconfig | 1 + configs/linkit-smart-7688_defconfig | 1 + configs/mt7620_mt7530_rfb_defconfig | 58 + configs/mt7620_rfb_defconfig | 76 + configs/mt7628_rfb_defconfig | 1 + configs/vocore2_defconfig | 1 + drivers/clk/mtmips/Makefile | 1 + drivers/clk/mtmips/clk-mt7620.c | 159 +++ drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/mt7620_gpio.c | 146 ++ drivers/mmc/mtk-sd.c | 136 +- drivers/net/Kconfig | 12 + drivers/net/Makefile | 1 + drivers/net/mt7620-eth.c | 1222 +++++++++++++++++ drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 1 + drivers/phy/mt7620-usb-phy.c | 110 ++ drivers/pinctrl/mtmips/Kconfig | 9 + drivers/pinctrl/mtmips/Makefile | 1 + drivers/pinctrl/mtmips/pinctrl-mt7620.c | 200 +++ drivers/reset/reset-mtmips.c | 1 + drivers/serial/Kconfig | 20 + drivers/serial/Makefile | 1 + drivers/serial/serial_mt7620.c | 246 ++++ drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mt7620_spi.c | 281 ++++ drivers/watchdog/Kconfig | 7 + drivers/watchdog/Makefile | 1 + drivers/watchdog/mt7620_wdt.c | 142 ++ include/configs/mt7620.h | 46 + include/dt-bindings/clock/mt7620-clk.h | 40 + include/dt-bindings/reset/mt7620-reset.h | 35 + 61 files changed, 4477 insertions(+), 72 deletions(-) create mode 100644 arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts create mode 100644 arch/mips/dts/mediatek,mt7620-rfb.dts create mode 100644 arch/mips/dts/mt7620-u-boot.dtsi create mode 100644 arch/mips/dts/mt7620.dtsi create mode 100644 arch/mips/mach-mtmips/include/mach/mt7620-sysc.h create mode 100644 arch/mips/mach-mtmips/mt7620/Kconfig create mode 100644 arch/mips/mach-mtmips/mt7620/Makefile create mode 100644 arch/mips/mach-mtmips/mt7620/dram.c create mode 100644 arch/mips/mach-mtmips/mt7620/init.c create mode 100644 arch/mips/mach-mtmips/mt7620/lowlevel_init.S create mode 100644 arch/mips/mach-mtmips/mt7620/mt7620.h create mode 100644 arch/mips/mach-mtmips/mt7620/serial.c create mode 100644 arch/mips/mach-mtmips/mt7620/sysc.c create mode 100644 arch/mips/mach-mtmips/mt7628/Kconfig create mode 100644 board/mediatek/mt7620/Kconfig create mode 100644 board/mediatek/mt7620/MAINTAINERS create mode 100644 board/mediatek/mt7620/Makefile create mode 100644 board/mediatek/mt7620/board.c create mode 100644 configs/mt7620_mt7530_rfb_defconfig create mode 100644 configs/mt7620_rfb_defconfig create mode 100644 drivers/clk/mtmips/clk-mt7620.c create mode 100644 drivers/gpio/mt7620_gpio.c create mode 100644 drivers/net/mt7620-eth.c create mode 100644 drivers/phy/mt7620-usb-phy.c create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7620.c create mode 100644 drivers/serial/serial_mt7620.c create mode 100644 drivers/spi/mt7620_spi.c create mode 100644 drivers/watchdog/mt7620_wdt.c create mode 100644 include/configs/mt7620.h create mode 100644 include/dt-bindings/clock/mt7620-clk.h create mode 100644 include/dt-bindings/reset/mt7620-reset.h -- 2.17.1

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[PATCH v3 0/7] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t
by tkuw584924＠gmail.com 21 Jan '21

21 Jan '21

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. The datasheet can be found in https://community.cypress.com/docs/DOC-15165 Tested on Xilinx Zynq-7000 FPGA board. Takahiro Kuwano (7): mtd: spi-nor: Add Cypress manufacturer ID mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t mtd: spi-nor: Add support for volatile QE bit mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte mtd: spi-nor-core: Add overlaid sector erase feature mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t drivers/mtd/spi/spi-nor-core.c | 178 +++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi-nor-ids.c | 24 +++++ drivers/mtd/spi/spi-nor-tiny.c | 73 ++++++++++++++ include/linux/mtd/spi-nor.h | 3 + 4 files changed, 278 insertions(+) --- Changes since v3: - Split into multiple patches Changes since v2: - Fixed typo in comment for spansion_overlaid_erase() - Fixed expressions for addr and len check in spansion_overlaid_erase() - Added device ID check to make the changes effective for S25 only - Added nor->setup() and fixup hooks based on the following patches https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-7-p.ya… https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-8-p.ya… https://patchwork.ozlabs.org/project/uboot/patch/20200904153500.3569-9-p.ya… -- 2.25.1

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