January 2021 - U-Boot

[PATCH v2 0/3] video: sunxi: Convert DM_VIDEO
by Jagan Teki 04 Feb '21

04 Feb '21

These series supports DM_VIDEO conversation for missing sunxi platforms. Separate splash screen support is required since the video log support in legacy drivers are not supporting with driver mode video. Dependencies: http://patchwork.ozlabs.org/project/uboot/list/?series=182476 http://patchwork.ozlabs.org/project/uboot/list/?series=182477 http://patchwork.ozlabs.org/project/uboot/list/?series=182478 Changes for v2: - new splash screen support patches Any inputs? Jagan. Jagan Teki (3): logos: Add sunxi logo sunxi: Enable splash screen support video: sunxi_display: Convert to DM_VIDEO arch/arm/mach-sunxi/Kconfig | 4 +- drivers/video/sunxi/sunxi_display.c | 264 ++++++++++++++++------------ include/configs/sunxi-common.h | 26 ++- scripts/config_whitelist.txt | 1 - tools/logos/sunxi.bmp | Bin 0 -> 11018 bytes 5 files changed, 167 insertions(+), 128 deletions(-) create mode 100644 tools/logos/sunxi.bmp -- 2.25.1

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[PATCH v2 0/8] Various minor fixes
by Simon Glass 04 Feb '21

04 Feb '21

This series collects a few minor fixes and improvements that have been hanging around in a branch for a while. Changes in v2: - Drop the file instead of fixing it up - Add new patch to add os_realloc() - Drop unnecessary check before calling os_free() - Update the comment for os_free() - Also free the RAM buffer - Convert the rest of the allocations in os.c, etc. Simon Glass (8): spl: Drop duplicate 'Jumping to U-Boot' message binman: Indicate how to make binman verbose doc: Add a note about how to produce 'md' output using hexdump s5p4418_nanopi2: Drop dead code sandbox: Add os_realloc() sandbox: Avoid using malloc() for system state sandbox: Write out bloblist when existing bootm: Fix duplicate debugging in bootm_process_cmdline() Makefile | 1 + README | 4 + arch/arm/mach-nexell/Makefile | 1 - arch/arm/mach-nexell/cmd_boot_linux.c | 144 -------------------------- arch/sandbox/cpu/os.c | 62 ++++++++--- arch/sandbox/cpu/spl.c | 10 +- arch/sandbox/cpu/start.c | 12 ++- arch/sandbox/cpu/state.c | 23 ++-- common/bootm.c | 2 +- common/spl/spl.c | 1 - include/os.h | 15 ++- tools/binman/README | 4 +- 12 files changed, 100 insertions(+), 179 deletions(-) delete mode 100644 arch/arm/mach-nexell/cmd_boot_linux.c -- 2.30.0.280.ga3ce27912f-goog

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[PATCH] cmd: fdt: skip board specific fixup using env variable
by Wasim Khan 04 Feb '21

04 Feb '21

From: Wasim Khan <wasim.khan(a)nxp.com> Sometimes it is useful to boot OS with already fixed-up device tree. Check for env variable 'skip_board_fixup' before calling ft_board_setup(). Current behaviour is unchanged, additionally user can set skip_board_fixup to 1 to skip the fixup. Signed-off-by: Wasim Khan <wasim.khan(a)nxp.com> --- common/image-fdt.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 327a8c4c39..0435176863 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -572,11 +572,18 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, fdt_fixup_pstore(blob); #endif if (IMAGE_OF_BOARD_SETUP) { - fdt_ret = ft_board_setup(blob, gd->bd); - if (fdt_ret) { - printf("ERROR: board-specific fdt fixup failed: %s\n", - fdt_strerror(fdt_ret)); - goto err; + const char *skip_board_fixup; + + skip_board_fixup = env_get("skip_board_fixup"); + if (skip_board_fixup && ((int)simple_strtol(skip_board_fixup, NULL, 10) == 1)) { + printf("skip board fdt fixup\n"); + } else { + fdt_ret = ft_board_setup(blob, gd->bd); + if (fdt_ret) { + printf("ERROR: board-specific fdt fixup failed: %s\n", + fdt_strerror(fdt_ret)); + goto err; + } } } if (IMAGE_OF_SYSTEM_SETUP) { -- 2.25.1

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[PATCH v5 00/20] Add support for MMC higher speed modes for TI's am65x, j721e and j7200 platforms
by Aswath Govindraju 04 Feb '21

04 Feb '21

The following patches add support for higher speeds in the SD card and eMMC for TI's am65x, j721e, j7200 platforms. With these patches, the following max speeds are supported: j721e: DDR50, HS200 j7200: SDR104, HS200 am65x: SDR104*, HS200 changes since v4: 1. removed patch(15 in v4) that adds support for HS400 in J7200 platform, as there are some errors while switching to HS400 mode. 2. changed the function regulator_set_enable() in patch 1 to regulator_set_enable_if_allowed() as there is a possibility of not having an enable gpio. 3. changed the pin direction from PIN_INPUT to PIN_OUTPUT for pins SPI1_CS1 and SPI0_D1 in patches 13 and 15 (in v4) repectively. 4. changed the configs enabled, to HS200 from HS400 for J7200 in patch 18 (in v4). changes since v3: 1. changed #if to if(IS_ENABLED()) in patch 1 for MMC_IO_VOLTAGE. 2. changed the format for print statements added in v3 to remove warnings arising when DM_REGULATOR variable is not defined 3. Added a patch to add support for HS400 speed mode in J7200 as it is now supported. 4. edited patch 17 (in v3) to add support for HS400 instead of HS200 as it is now supported in J7200 SoC. 4. Added description for sdhci_set_ctrl_reg() function in include/sdhci.h 5. Added comment for mdelay in patch 1 6. Picked up Reviewed-by's from Jaehoon Chung changes since v2: 1. Added print statements in case of failure for regulator_set_enable and regulator_set_value function calls in patch 1 2. Removed patch 18 (in v2) as it has been applied by commit [1] 3. renamed the function dev_get_platdata() to dev_get_plat in patch 8 4. rebased all the patches in seriesn changes since v1: 1. Added patches to support UHS modes for the SD card even in am654x platforms. 2. Fixed an issue with patch 1 that was breaking builds on some platforms. * There's an issue with the am65x base board such that the power cycle circuit to the card takes way longer than the wait time in mmc core. Until this is fixed, am654x-evm and -idk will only support High speed mode at 3.3V (see patch 20) but this shouldn't block us from adding UHS modes in the dtsi as well as in the configs so other boards can still take advantage of the higher speed. UHS modes have been tested by adding the appropriate delay in the power cycle circuit. [1] - commit 67507e4aab5b ("sandbox: Fix up building for of-platdata") Link to v1: https://patchwork.ozlabs.org/project/uboot/list/?series=206622 Faiz Abbas (20): mmc: sdhci: Add helper functions for UHS modes mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post() mmc: am654_sdhci: Convert flag fields to BIT macro mmc: am654_sdhci: Add flag for PHY calibration mmc: am654_sdhci: Add support for AM65x SR2.0 mmc: am654_sdhci: Add support for input tap delay mmc: am654_sdhci: Add support for writing to clkbuf_sel mmc: am654_sdhci: Add support for software tuning mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes mmc: am654_sdhci: Use sdhci_set_control_reg() arm: dts: k3-am65: Fix mmc nodes arm: dts: k3-j721e-main: Update otap-delay values arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card arm: dts: k3-j7200-main: Add support for gpio0 arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes configs: j721e_evm: Add support for UHS modes configs: j7200_evm: Add support for UHS modes arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values arm: dts: k3-am654-base-board: Limit Sd card to High speed modes configs: am65x_evm: Add configs for UHS modes arch/arm/dts/k3-am65-main.dtsi | 31 ++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +-- arch/arm/dts/k3-am654-base-board.dts | 26 ++ arch/arm/dts/k3-am654-r5-base-board.dts | 20 +- arch/arm/dts/k3-j7200-common-proc-board.dts | 49 ++- arch/arm/dts/k3-j7200-main.dtsi | 23 ++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 32 ++ arch/arm/dts/k3-j721e-main.dtsi | 8 +- configs/am65x_evm_a53_defconfig | 8 + configs/am65x_evm_r5_defconfig | 2 + configs/j7200_evm_a72_defconfig | 8 + configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 8 + configs/j721e_evm_r5_defconfig | 1 + drivers/mmc/Kconfig | 1 + drivers/mmc/am654_sdhci.c | 384 +++++++++++++----- drivers/mmc/sdhci.c | 73 ++++ include/sdhci.h | 10 + 19 files changed, 594 insertions(+), 173 deletions(-) -- 2.17.1

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[PATCH 1/1] cmd/riscv/sbi: support System Reset Extension
by Heinrich Schuchardt 04 Feb '21

04 Feb '21

Let the sbi command detect the 'System Reset Extension' (EID #0x53525354 "SRST"). Cf. https://github.com/riscv/riscv-sbi-doc Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/riscv/sbi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index e66fc8e41d..9897483eb6 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -29,6 +29,7 @@ static struct sbi_ext extensions[] = { { 0x00735049, "IPI Extension" }, { 0x52464E43, "RFENCE Extension" }, { 0x0048534D, "Hart State Management Extension" }, + { 0x53525354, "System Reset Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, -- 2.28.0

4 3

[PATCH v5 0/9] dm: core: Add support for vital devices
by Simon Glass 04 Feb '21

04 Feb '21

This is an attempt to come up with a 'late removal' feature, as implemented by Marek, but using different terminology and trying to fit in with the existing removal flags. I have taken the opportunity to clean up a few related things. The series is available at u-boot-dm/late-working The previous patch was here: http://patchwork.ozlabs.org/project/uboot/patch/20201108140818.55172-1-mare… Changes in v5: - Change logic to allow flags to be combined - Add patch to remove vital devices last Changes in v4: - Use 'vital' rather than 'late' as the description - Invert the removal flag to DM_REMOVE_NON_VITAL, to avoid the need for two-pass processing in the bowels of driver model - Simplify the test to only test 'vital' - Drop the change to uclass_destroy() - Revised and updated based on discussion Marek Vasut (1): dm: core: Add late driver remove option Simon Glass (8): smem: Don't use -EPROBE_DEFER nand: brcmnand: Don't use -EPROBE_DEFER dm: Rename DM_FLAG_REMOVE_WITH_PD_ON dm: pci: Correct use of wrong flag name dm: core: Remove children before advising uclass dm: core: Avoid partially removing devices arm: Remove vital devices last dm: core: Add documentation about device removal arch/arm/lib/bootm.c | 3 + doc/driver-model/design.rst | 20 +++++ drivers/core/device-remove.c | 96 +++++++++++++++++------- drivers/core/root.c | 2 + drivers/mtd/nand/raw/brcmnand/brcmnand.c | 5 +- drivers/pci/pcie_iproc.c | 2 +- drivers/smem/msm_smem.c | 6 +- drivers/video/meson/meson_vpu.c | 2 +- drivers/watchdog/rti_wdt.c | 2 +- include/dm/device-internal.h | 15 +++- include/dm/device.h | 15 +++- test/dm/core.c | 94 +++++++++++++++++++++++ test/dm/test-driver.c | 22 ++++++ test/dm/virtio.c | 4 +- 14 files changed, 244 insertions(+), 44 deletions(-) -- 2.30.0.280.ga3ce27912f-goog

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[PATCH v2 00/10] Allow booting a 32-bit system with a top memory address beyond 4 GiB
by Bin Meng 04 Feb '21

04 Feb '21

When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While 2 GiB QEMU RISC-V 'virt' happens to work with U-Boot today, increasing more memory doesn't make a bootable system. There are various places in U-Boot that prevents such from working. While this is seen and tested on RISC-V, it's not RISC-V centric, but a generic issue that may affect all architectures. Changes in v2: - new patch: arm: rockchip: Explicitly cast gd->ram_top in dram_init_banksize() - new patch: riscv: ax25-ae350: Cast addr with uintptr_t - new patch: net: ftmac100: Cast priv->iobase with uintptr_t Bin Meng (10): riscv: Adjust board_get_usable_ram_top() for 32-bit arm: rockchip: Explicitly cast gd->ram_top in dram_init_banksize() global_data.h: Change ram_top type to phys_addr_t serial: sifive: Cast dev_read_addr() with uintptr_t riscv: ax25-ae350: Cast addr with uintptr_t net: ftmac100: Cast priv->iobase with uintptr_t fdtdec: Cast prior_stage_fdt_address with uintptr_t riscv: Change phys_addr_t and phys_size_t to 64-bit bdinfo: Rename function names to be clearer bdinfo: Change to use bdinfo_print_num_ll() where the number could be 64-bit arch/arm/lib/bdinfo.c | 16 ++++---- arch/arm/mach-rockchip/sdram.c | 2 +- arch/m68k/lib/bdinfo.c | 2 +- arch/powerpc/lib/bdinfo.c | 4 +- arch/riscv/cpu/fu540/dram.c | 7 ++-- arch/riscv/cpu/generic/dram.c | 7 ++-- arch/riscv/include/asm/types.h | 4 +- board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +- cmd/bdinfo.c | 52 ++++++++++++------------- drivers/net/ftmac100.c | 10 ++--- drivers/serial/serial_sifive.c | 2 +- include/asm-generic/global_data.h | 2 +- include/init.h | 3 +- lib/fdtdec.c | 2 +- 14 files changed, 57 insertions(+), 58 deletions(-) -- 2.25.1

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[PATCH] spi: imx: Implement set_speed
by Marek Vasut 03 Feb '21

03 Feb '21

The set_speed() callback should configure the bus speed, make it so. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/spi/mxc_spi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 553a0315df5..47100d89aef 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -661,7 +661,10 @@ static int mxc_spi_release_bus(struct udevice *dev) static int mxc_spi_set_speed(struct udevice *bus, uint speed) { - /* Nothing to do */ + struct mxc_spi_slave *mxcs = dev_get_platdata(bus); + + mxcs->max_hz = speed; + return 0; } -- 2.29.2

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[PATCH v2] spi: zynqmp_gqspi: support dual and quad mode
by Brandon Maier 03 Feb '21

03 Feb '21

The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It also doesn't allow the zynqmp_gqspi driver to calculate the correct number of dummy cycles for some NOR ops (as doing so also requires the buswidth). Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us the buswidth values to correctly support all SNOR_PROTO_X_X_X commands and to properly calculate dummy cycles. Signed-off-by: Brandon Maier <brandon.maier(a)rockwellcollins.com> CC: jagan(a)amarulasolutions.com CC: michal.simek(a)xilinx.com CC: Ashok Reddy Soma <ashokred(a)xilinx.com> --- v1: https://lists.denx.de/pipermail/u-boot/2021-January/437506.html v2: - Initialize 'ret' to 0 for exec_op() commands without data in/out. --- drivers/spi/zynqmp_gqspi.c | 164 ++++++++++++++++--------------------- 1 file changed, 70 insertions(+), 94 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index efcbd0557f..c7db43a09a 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -16,6 +16,7 @@ #include <malloc.h> #include <memalign.h> #include <spi.h> +#include <spi-mem.h> #include <ubi_uboot.h> #include <wait_bit.h> #include <dm/device_compat.h> @@ -171,8 +172,7 @@ struct zynqmp_qspi_priv { unsigned int len; int bytes_to_transfer; int bytes_to_receive; - unsigned int is_inst; - unsigned int cs_change:1; + const struct spi_mem_op *op; }; static int zynqmp_qspi_of_to_plat(struct udevice *bus) @@ -221,6 +221,21 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv) return gqspi_fifo_reg; } +static u32 zynqmp_qspi_genfifo_mode(u8 buswidth) +{ + switch (buswidth) { + case 1: + return GQSPI_SPI_MODE_SPI; + case 2: + return GQSPI_SPI_MODE_DUAL_SPI; + case 4: + return GQSPI_SPI_MODE_QSPI; + default: + debug("Unsupported bus width %u\n", buswidth); + return GQSPI_SPI_MODE_SPI; + } +} + static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, u32 gqspi_fifo_reg) { @@ -445,21 +460,42 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) { + const struct spi_mem_op *op = priv->op; u32 gen_fifo_cmd; - u32 bytecount = 0; + u8 i, dummy_cycles, addr; + + /* Send opcode */ + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth); + gen_fifo_cmd |= GQSPI_GFIFO_TX; + gen_fifo_cmd |= op->cmd.opcode; + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + + /* Send address */ + for (i = 0; i < op->addr.nbytes; i++) { + addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); - while (priv->len) { gen_fifo_cmd = zynqmp_qspi_bus_select(priv); - gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI; - gen_fifo_cmd |= *(u8 *)priv->tx_buf; - bytecount++; - priv->len--; - priv->tx_buf = (u8 *)priv->tx_buf + 1; + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth); + gen_fifo_cmd |= GQSPI_GFIFO_TX; + gen_fifo_cmd |= addr; debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); } + + /* Send dummy */ + if (op->dummy.nbytes) { + dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; + + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth); + gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX); + gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK; + gen_fifo_cmd |= dummy_cycles; + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + } } static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv, @@ -496,11 +532,10 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) int ret = 0; gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; - while (priv->len) { len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); @@ -574,11 +609,10 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) u32 actuallen = priv->len; gen_fifo_cmd = zynqmp_qspi_bus_select(priv); + gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; - gen_fifo_cmd |= GQSPI_SPI_MODE_SPI; - /* * Check if receive buffer is aligned to 4 byte and length * is multiples of four byte as we are using dma to receive. @@ -595,62 +629,6 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); } -static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv) -{ - int ret = 0; - - if (priv->is_inst) { - if (priv->tx_buf) - zynqmp_qspi_genfifo_cmd(priv); - else - return -EINVAL; - } else { - if (priv->tx_buf) - ret = zynqmp_qspi_genfifo_fill_tx(priv); - else if (priv->rx_buf) - ret = zynqmp_qspi_genfifo_fill_rx(priv); - else - return -EINVAL; - } - return ret; -} - -static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv) -{ - static unsigned int cs_change = 1; - int status = 0; - - debug("%s\n", __func__); - - while (1) { - /* Select the chip if required */ - if (cs_change) - zynqmp_qspi_chipselect(priv, 1); - - cs_change = priv->cs_change; - - if (!priv->tx_buf && !priv->rx_buf && priv->len) { - status = -EINVAL; - break; - } - - /* Request the transfer */ - if (priv->len) { - status = zynqmp_qspi_start_transfer(priv); - priv->is_inst = 0; - if (status < 0) - break; - } - - if (cs_change) - /* Deselect the chip */ - zynqmp_qspi_chipselect(priv, 0); - break; - } - - return status; -} - static int zynqmp_qspi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -673,45 +651,43 @@ static int zynqmp_qspi_release_bus(struct udevice *dev) return 0; } -int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +static int zynqmp_qspi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) { - struct udevice *bus = dev->parent; - struct zynqmp_qspi_priv *priv = dev_get_priv(bus); + struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent); + int ret = 0; - debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__, - (unsigned long)priv, bitlen, (unsigned long)dout); - debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags); + priv->op = op; + priv->tx_buf = op->data.buf.out; + priv->rx_buf = op->data.buf.in; + priv->len = op->data.nbytes; - priv->tx_buf = dout; - priv->rx_buf = din; - priv->len = bitlen / 8; + zynqmp_qspi_chipselect(priv, 1); - /* - * Assume that the beginning of a transfer with bits to - * transmit must contain a device command. - */ - if (dout && flags & SPI_XFER_BEGIN) - priv->is_inst = 1; - else - priv->is_inst = 0; + /* Send opcode, addr, dummy */ + zynqmp_qspi_genfifo_cmd(priv); - if (flags & SPI_XFER_END) - priv->cs_change = 1; - else - priv->cs_change = 0; + /* Request the transfer */ + if (op->data.dir == SPI_MEM_DATA_IN) + ret = zynqmp_qspi_genfifo_fill_rx(priv); + else if (op->data.dir == SPI_MEM_DATA_OUT) + ret = zynqmp_qspi_genfifo_fill_tx(priv); - zynqmp_qspi_transfer(priv); + zynqmp_qspi_chipselect(priv, 0); - return 0; + return ret; } +static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = { + .exec_op = zynqmp_qspi_exec_op, +}; + static const struct dm_spi_ops zynqmp_qspi_ops = { .claim_bus = zynqmp_qspi_claim_bus, .release_bus = zynqmp_qspi_release_bus, - .xfer = zynqmp_qspi_xfer, .set_speed = zynqmp_qspi_set_speed, .set_mode = zynqmp_qspi_set_mode, + .mem_ops = &zynqmp_qspi_mem_ops, }; static const struct udevice_id zynqmp_qspi_ids[] = { -- 2.29.1

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[PATCH 1/5] arm: dts: r8a774a1: Import DTS queued for Linux 5.12-rc1
by Adam Ford 02 Feb '21

02 Feb '21

Update the RZ/G2M dtsi and r8a774a1-beacon-rzg2m-kit kit from Renesas repo destined to become 5.12-rc1. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- arch/arm/dts/beacon-renesom-baseboard.dtsi | 359 ++++++++++++++++----- arch/arm/dts/beacon-renesom-som.dtsi | 57 +++- arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts | 59 +++- arch/arm/dts/r8a774a1.dtsi | 74 ++++- 4 files changed, 445 insertions(+), 104 deletions(-) diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi b/arch/arm/dts/beacon-renesom-baseboard.dtsi index 8a472c057a..5f998d4706 100644 --- a/arch/arm/dts/beacon-renesom-baseboard.dtsi +++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi @@ -5,35 +5,27 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/clk/versaclock.h> / { - aliases { - serial0 = &scif2; - serial1 = &hscif0; - serial2 = &hscif1; - serial3 = &scif0; - serial4 = &hscif2; - serial5 = &scif5; - spi0 = &msiof0; - spi1 = &msiof1; - spi2 = &msiof2; - spi3 = &msiof3; - ethernet0 = &avb; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; power-supply = <&reg_lcd>; enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>; - pwms = <&pwm0 0 50000>; + pwms = <&pwm2 0 25000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; + backlight_dpi: backlight-dpi { + compatible = "pwm-backlight"; + power-supply = <&reg_lcd>; + enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 0 25000>; + brightness-levels = <0 25 33 50 63 75 88 100>; + default-brightness-level = <6>; + }; + hdmi0-out { compatible = "hdmi-connector"; type = "a"; @@ -48,38 +40,38 @@ keys { compatible = "gpio-keys"; - key-1 { + key-1 { /* S19 */ gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - linux,code = <KEY_1>; - label = "Switch-1"; + linux,code = <KEY_UP>; + label = "Up"; wakeup-source; debounce-interval = <20>; }; - key-2 { + key-2 { /*S20 */ gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - linux,code = <KEY_2>; - label = "Switch-2"; + linux,code = <KEY_LEFT>; + label = "Left"; wakeup-source; debounce-interval = <20>; }; - key-3 { + key-3 { /* S21 */ gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - linux,code = <KEY_3>; - label = "Switch-3"; + linux,code = <KEY_DOWN>; + label = "Down"; wakeup-source; debounce-interval = <20>; }; - key-4 { + key-4 { /* S22 */ gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - linux,code = <KEY_4>; - label = "Switch-4"; + linux,code = <KEY_RIGHT>; + label = "Right"; wakeup-source; debounce-interval = <20>; }; - key-5 { + key-5 { /* S23 */ gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - linux,code = <KEY_5>; - label = "Switch-4"; + linux,code = <KEY_ENTER>; + label = "Center"; wakeup-source; debounce-interval = <20>; }; @@ -98,17 +90,59 @@ led1 { gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; label = "LED1"; - linux,default-trigger = "heartbeat"; }; led2 { gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; label = "LED2"; - linux,default-trigger = "heartbeat"; }; led3 { gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; label = "LED3"; - linux,default-trigger = "heartbeat"; + }; + }; + + lvds { + compatible = "panel-lvds"; + power-supply = <&reg_lcd_reset>; + width-mm = <223>; + height-mm = <125>; + backlight = <&backlight_lvds>; + data-mapping = "vesa-24"; + + panel-timing { + /* 800x480@60Hz */ + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hsync-len = <48>; + hfront-porch = <40>; + hback-porch = <40>; + vfront-porch = <13>; + vback-porch = <29>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <3>; + de-active = <1>; + pixelclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + rgb { + /* Different LCD with compatible timings */ + compatible = "rocktech,rk070er9427"; + backlight = <&backlight_dpi>; + enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + power-supply = <&reg_lcd>; + port { + rgb_panel: endpoint { + remote-endpoint = <&du_out_rgb>; + }; }; }; @@ -117,7 +151,7 @@ regulator-name = "audio-1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>; + gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -167,15 +201,12 @@ vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; - regulator-name = "SDHI0 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; - regulator-always-on; }; /* External DU dot clocks */ @@ -190,10 +221,29 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; -}; -&audio_clk_a { - clock-frequency = <22579200>; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_b { @@ -214,30 +264,19 @@ status = "okay"; }; -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; +&du_out_rgb { + remote-endpoint = <&rgb_panel>; }; &ehci0 { dr_mode = "otg"; status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>, <&versaclock6_bb 4>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>; }; &ehci1 { status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 4>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; }; &hdmi0 { @@ -258,7 +297,6 @@ }; }; port@2 { - /* HDMI sound */ reg = <2>; dw_hdmi0_snd_in: endpoint { remote-endpoint = <&rsnd_endpoint1>; @@ -281,7 +319,7 @@ &i2c2 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -299,18 +337,49 @@ #gpio-cells = <2>; }; - versaclock6_bb: versaclock6_bb@6a { + gpio_exp4: gpio@23 { + compatible = "onnn,pca9654"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + versaclock6_bb: clock-controller@6a { compatible = "idt,5p49v6965"; reg = <0x6a>; #clock-cells = <1>; clocks = <&x304_clk>; clock-names = "xin"; - /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */ + assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, <&versaclock6_bb 3>, <&versaclock6_bb 4>; - assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24000000>; + assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>; + + OUT1 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT2 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT3 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; + + OUT4 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; }; }; @@ -324,13 +393,14 @@ &i2c5 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c5_pins>; pinctrl-names = "default"; codec: wm8962@1a { compatible = "wlf,wm8962"; reg = <0x1a>; + clocks = <&versaclock6_bb 3>; DCVDD-supply = <&reg_audio>; DBVDD-supply = <&reg_audio>; AVDD-supply = <&reg_audio>; @@ -375,6 +445,49 @@ interrupts = <9 IRQ_TYPE_EDGE_RISING>; wakeup-source; }; + + hd3ss3220@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + interrupt-parent = <&gpio6>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&msiof1 { + pinctrl-0 = <&msiof1_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; }; &ohci0 { @@ -440,6 +553,11 @@ function = "pwm0"; }; + pwm2_pins: pwm2 { + groups = "pwm2_a"; + function = "pwm2"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -458,7 +576,7 @@ }; sound_clk_pins: sound_clk { - groups = "audio_clk_a_a"; + groups = "audio_clk_a_a", "audio_clk_b_a"; function = "audio_clk"; }; @@ -490,6 +608,12 @@ status = "okay"; }; +&pwm2 { + pinctrl-0 = <&pwm2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &rcar_sound { pinctrl-0 = <&sound_pins &sound_clk_pins>; pinctrl-names = "default"; @@ -503,23 +627,6 @@ status = "okay"; - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; - ports { #address-cells = <1>; #size-cells = <0>; @@ -551,6 +658,11 @@ }; }; +&rwdt { + status = "okay"; + timeout-sec = <60>; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; @@ -584,6 +696,26 @@ shared-pin; }; +&tmu0 { + status = "okay"; +}; + +&tmu1 { + status = "okay"; +}; + +&tmu2 { + status = "okay"; +}; + +&tmu3 { + status = "okay"; +}; + +&tmu4 { + status = "okay"; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; @@ -595,3 +727,62 @@ pinctrl-names = "default"; status = "okay"; }; + +&usb3_peri0 { + companion = <&xhci0>; + status = "okay"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&vin0 { + status = "okay"; +}; +&vin1 { + status = "okay"; +}; +&vin2 { + status = "okay"; +}; +&vin3 { + status = "okay"; +}; +&vin4 { + status = "okay"; +}; +&vin5 { + status = "okay"; +}; +&vin6 { + status = "okay"; +}; +&vin7 { + status = "okay"; +}; + +&xhci0 +{ + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi index 6c16a2732a..9565495b49 100644 --- a/arch/arm/dts/beacon-renesom-som.dtsi +++ b/arch/arm/dts/beacon-renesom-som.dtsi @@ -4,17 +4,18 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clk/versaclock.h> / { memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; + reg = <0x0 0x48000000 0x0 0xc000000>; }; - memory@600000000 { + memory@57000000 { device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; + reg = <0x0 0x57000000 0x0 0x29000000>; }; osc_32k: osc_32k { @@ -55,7 +56,8 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { @@ -88,7 +90,6 @@ pinctrl-names = "default"; uart-has-rtscts; status = "okay"; - max-speed = <4000000>; bluetooth { compatible = "brcm,bcm43438-bt"; @@ -97,6 +98,7 @@ device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>; clocks = <&osc_32k>; clock-names = "extclk"; + max-speed = <4000000>; }; }; @@ -108,7 +110,7 @@ &i2c4 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; pca9654: gpio@20 { compatible = "onnn,pca9654"; @@ -147,7 +149,7 @@ }; eeprom@50 { - compatible = "microchip, at24c64", "atmel,24c64"; + compatible = "microchip,at24c64", "atmel,24c64"; pagesize = <32>; read-only; /* Manufacturing EEPROM programmed at factory */ reg = <0x50>; @@ -169,7 +171,32 @@ <&versaclock5 2>, <&versaclock5 3>, <&versaclock5 4>; + assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>; + + OUT1 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT2 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT3 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT4 { + idt,mode = <VC5_CMOS>; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; }; }; @@ -295,18 +322,14 @@ status = "okay"; }; -&usb_extal_clk { - clock-frequency = <50000000>; +&usb2_clksel { + status = "okay"; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&versaclock5 3>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; }; &usb3s0_clk { clock-frequency = <100000000>; }; - -&vspb { - status = "okay"; -}; - -&vspi0 { - status = "okay"; -}; diff --git a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts index e7ed5d4806..501cb05da2 100644 --- a/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts +++ b/arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts @@ -10,6 +10,61 @@ #include "beacon-renesom-baseboard.dtsi" / { - model = "Beacon Embedded Works RZ/G2M Development Kit"; - compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; + model = "Beacon EmbeddedWorks RZ/G2M Development Kit"; + compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; + + aliases { + serial0 = &scif2; + serial1 = &hscif0; + serial2 = &hscif1; + serial3 = &scif0; + serial4 = &hscif2; + serial5 = &scif5; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; +}; + +/* Reference versaclock instead of audio_clk_a */ +&rcar_sound { + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774A1_CLK_S0D4>; }; diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi index 8e80f50132..d64fb8b1b8 100644 --- a/arch/arm/dts/r8a774a1.dtsi +++ b/arch/arm/dts/r8a774a1.dtsi @@ -408,7 +408,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; }; @@ -835,6 +835,21 @@ status = "disabled"; }; + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0 0xe6590630 0 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal_clk>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a774a1-usb-dmac", "renesas,usb-dmac"; @@ -1115,6 +1130,8 @@ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; @@ -2300,6 +2317,23 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774a1-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -2371,6 +2405,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a774a1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + status = "disabled"; + }; + fdp1@fe940000 { compatible = "renesas,fdp1"; reg = <0 0xfe940000 0 0x2400>; -- 2.25.1

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