August 2020 - U-Boot

[PATCH v1] configs: socfpga: soc64: Avoid SPL enter infinite loop during exception
by Chee Hong Ang 06 Aug '20

06 Aug '20

From: Chin Liang See <chin.liang.see(a)intel.com> In current implementation, any exception would trigger a CPU reset. But a bad written SPL would cause infinite loop where the system will reload the same SPL instead of loading factory safe image. Hence this patch is to ensure any exception will cause a hang. At this moment, watchdog shall be triggered and Remote System Update mechanism shall load the next production image or factory safe image. Signed-off-by: Chin Liang See <chin.liang.see(a)intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- configs/socfpga_agilex_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 2885c60..acf0316 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -61,3 +61,4 @@ CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y # CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 9ae6ef6..8b4d1fb 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -67,3 +67,4 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y -- 2.2.0

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[PATCH] arm64: Layerscape: Survive LPI one-way reset workaround
by Zhiqiang Hou 06 Aug '20

06 Aug '20

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 ++++++++++++++++- arch/arm/dts/fsl-ls1028a.dtsi | 6 ++++++ arch/arm/dts/fsl-ls1088a.dtsi | 6 ++++++ arch/arm/dts/fsl-ls2080a.dtsi | 6 ++++++ arch/arm/dts/fsl-lx2160a.dtsi | 6 ++++++ 5 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index fde893e8c9..53d790f395 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -43,7 +43,22 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_GIC_V3_ITS int ls_gic_rd_tables_init(void *blob) { - int ret; + struct fdt_memory lpi_base; + fdt_addr_t addr; + fdt_size_t size; + int offset, ret; + + offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000"); + addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg", + 0, &size, false); + + lpi_base.start = addr; + lpi_base.end = addr + size - 1; + ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL); + if (ret) { + debug("%s: failed to add reserved memory\n", __func__); + return ret; + } ret = gic_lpi_tables_init(); if (ret) diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 9911690e5c..bf6373d5ec 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -44,6 +44,12 @@ IRQ_TYPE_LEVEL_LOW)>; }; + gic_lpi_base: syscon@0x80000000 { + compatible = "gic-lpi-base"; + reg = <0x0 0x80000000 0x0 0x100000>; + max-gic-redistributors = <2>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index bf303c6ad3..6653794d1c 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -26,6 +26,12 @@ interrupts = <1 9 0x4>; }; + gic_lpi_base: syscon@0x80000000 { + compatible = "gic-lpi-base"; + reg = <0x0 0x80000000 0x0 0x100000>; + max-gic-redistributors = <8>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 90a0a3f8fb..6b7bf8eb16 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -26,6 +26,12 @@ interrupts = <1 9 0x4>; }; + gic_lpi_base: syscon@0x80000000 { + compatible = "gic-lpi-base"; + reg = <0x0 0x80000000 0x0 0x100000>; + max-gic-redistributors = <8>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index dee1e2f215..37a4f39c8f 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -43,6 +43,12 @@ interrupts = <1 9 0x4>; }; + gic_lpi_base: syscon@0x80000000 { + compatible = "gic-lpi-base"; + reg = <0x0 0x80000000 0x0 0x200000>; + max-gic-redistributors = <16>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ -- 2.17.1

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Re: [PATCH 4/6] riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level
by Rick Chen 06 Aug '20

06 Aug '20

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Monday, August 03, 2020 2:09 PM > To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List > Cc: Bin Meng > Subject: [PATCH 4/6] riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level > > From: Bin Meng <bin.meng(a)windriver.com> > > All FU540 driver related options should be in the SoC level Kconfig. > > Signed-off-by: Bin Meng <bin.meng(a)windriver.com> > --- > > arch/riscv/cpu/fu540/Kconfig | 22 ++++++++++++++++++++++ > board/sifive/fu540/Kconfig | 22 ---------------------- > 2 files changed, 22 insertions(+), 22 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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[PATCH v2] arm: socfpga: Use DM watchdog timer
by Chee Hong Ang 06 Aug '20

06 Aug '20

All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4 ++++ arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4 ++++ arch/arm/dts/socfpga_stratix10.dtsi | 1 - arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 1 + arch/arm/mach-socfpga/spl_agilex.c | 2 +- arch/arm/mach-socfpga/spl_s10.c | 2 +- configs/socfpga_agilex_defconfig | 2 ++ 7 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index debeb8b..6cac36a 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -40,3 +40,7 @@ &qspi { status = "okay"; }; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi index 58cd497..22e614d 100644 --- a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi @@ -15,3 +15,7 @@ &uart1 { u-boot,dm-pre-reloc; }; + +&watchdog1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index a8e61cf..cb799bc 100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -386,7 +386,6 @@ reg = <0xffd00200 0x100>; interrupts = <0 117 4>; resets = <&rst WATCHDOG0_RESET>; - u-boot,dm-pre-reloc; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index a903040..2669abb 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -33,5 +33,6 @@ }; &watchdog0 { + status = "okay"; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index bd971ec..6896c07 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -51,11 +51,11 @@ void board_init_f(ulong dummy) socfpga_get_managers_addr(); -#ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); +#ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index b3c6f6a..ad15ed1 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -53,11 +53,11 @@ void board_init_f(ulong dummy) socfpga_get_managers_addr(); -#ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); +#ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 2885c60..41bd925 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -60,4 +60,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -- 2.2.0

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[PATCH v2] arm: socfpga: soc64: Check FPGA Config status register before bridge reset
by Chee Hong Ang 06 Aug '20

06 Aug '20

Instead of querying SDM for FPGA configuration status through mailbox messages, U-Boot now checks System Manager's FPGA Config status register for FPGA configuration status before resetting bridge. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- arch/arm/mach-socfpga/include/mach/misc.h | 5 +++++ .../mach-socfpga/include/mach/system_manager_soc64.h | 6 +++++- arch/arm/mach-socfpga/misc_s10.c | 18 ++++++++++-------- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index a85c5ae..649d2f6 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -39,6 +39,11 @@ void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX) +int is_fpga_config_ready(void); +#endif + void do_bridge_reset(int enable, unsigned int mask); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c90f63a..5e3f54a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -88,8 +88,12 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); #define SYSMGR_ECC_OCRAM_EN BIT(0) #define SYSMGR_ECC_OCRAM_SERR BIT(3) #define SYSMGR_ECC_OCRAM_DERR BIT(4) -#define SYSMGR_FPGAINTF_USEFPGA 0x1 +#define SYSMGR_FPGACONFIG_FPGA_COMPLETE BIT(0) +#define SYSMGR_FPGACONFIG_EARLY_USERMODE BIT(1) +#define SYSMGR_FPGACONFIG_READY_MASK (SYSMGR_FPGACONFIG_FPGA_COMPLETE | \ + SYSMGR_FPGACONFIG_EARLY_USERMODE) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 #define SYSMGR_FPGAINTF_NAND BIT(4) #define SYSMGR_FPGAINTF_SDMMC BIT(8) #define SYSMGR_FPGAINTF_SPIM0 BIT(16) diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 670bfa1..52868fb 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -151,17 +151,19 @@ int arch_early_init_r(void) return 0; } +/* Return 1 if FPGA is ready otherwise return 0 */ +int is_fpga_config_ready(void) +{ + return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) & + SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK; +} + void do_bridge_reset(int enable, unsigned int mask) { /* Check FPGA status before bridge enable */ - if (enable) { - int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); - - if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG) - ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS); - - if (ret) - return; + if (!is_fpga_config_ready()) { + puts("FPGA not ready. Bridge reset aborted!\n"); + return; } socfpga_bridges_reset(enable); -- 2.2.0

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[PATCH] ddr: socfpga: stratix10: Use phys_size_t for memory size
by tien.fong.chee＠intel.com 06 Aug '20

06 Aug '20

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Replace with phys_size_t for better scalable. phys_size_t is defined in arch/arm/include/asm/types.h . Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/ddr/altera/sdram_s10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 2945f1e1df..5d24a5800a 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -276,7 +276,7 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_SCH_DEVTODEV); /* assigning the SDRAM size */ - unsigned long long size = sdram_calculate_size(plat); + phys_size_t size = sdram_calculate_size(plat); /* If the size is invalid, use default Config size */ if (size <= 0) hw_size = PHYS_SDRAM_1_SIZE; -- 2.13.0

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Re: [PATCH 3/6] riscv: sifive/fu540: spl: Rename soc_spl_init()
by Rick Chen 06 Aug '20

06 Aug '20

> From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Monday, August 03, 2020 2:09 PM > To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List > Cc: Bin Meng > Subject: [PATCH 3/6] riscv: sifive/fu540: spl: Rename soc_spl_init() > > From: Bin Meng <bin.meng(a)windriver.com> > > spl_soc_init() seems to be a better name, as all SPL functions names start from the spl_ prefix. > > Signed-off-by: Bin Meng <bin.meng(a)windriver.com> > --- > > arch/riscv/cpu/fu540/spl.c | 2 +- > arch/riscv/include/asm/arch-fu540/spl.h | 2 +- > board/sifive/fu540/spl.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH 1/1] cmd: exception: unaligned data access on RISC-V
by Rick Chen 06 Aug '20

06 Aug '20

Hi Heinrich > From: Heinrich Schuchardt [mailto:xypron.glpk@gmx.de] > Sent: Tuesday, August 04, 2020 7:10 PM > To: Rick Jian-Zhi Chen(陳建志) > Cc: u-boot(a)lists.denx.de; Heinrich Schuchardt > Subject: [PATCH 1/1] cmd: exception: unaligned data access on RISC-V > > The command 'exception' can be used to test the handling of exceptions. > > Currently the exception command only allows to create an illegal instruction exception on RISC-V. > > Provide a sub-command 'exception unaligned' to cause a misaligned load address exception. > > Adjust the online help for 'exception undefined'. > > Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> > --- > cmd/riscv/exception.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c index 3c8dbbec0e..53159531d9 100644 > --- a/cmd/riscv/exception.c > +++ b/cmd/riscv/exception.c > @@ -8,6 +8,17 @@ > #include <common.h> > #include <command.h> > > +static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc, > + char *const argv[]) > +{ > + asm volatile ( > + "auipc a1, 0\n" > + "ori a1, a1, 3\n" > + "lw a2, (0)(a1)\n" > + ); > + return CMD_RET_FAILURE; I suggest that we can modify it as below to print the unaligned address and data for more debug information. int ret = 0; int addr = 0; asm volatile ( "auipc a1, 0\n" "ori %0, a1, 3\n" "lw %1, (0)(a1)\n" : "=r" (addr), "=r" (ret) : : "memory" ); printf("unaligned addr 0x%x , ret 0x%x\n",addr,ret); return CMD_RET_SUCCESS; ==================================== So if run in S-Mode, it will work as below: RISC-V # exception unaligned unaligned addr 0x3ff92fd7 , ret 0x35e59300 RISC-V # (gdb) x/4x 0x3ff92fd0 0x3ff92fd0: 0x7ac362ef 0x00000597 0x0035e593 0xc5174190 (gdb) ==================================== If run in M-Mode, it will work as below: RISC-V # exception unaligned Unhandled exception: Load address misaligned EPC: 000000003ff92fdc RA: 000000003ff93032 TVAL: 000000003ff92fd7 EPC: 0000000000009fdc RA: 000000000000a032 reloc adjusted ### ERROR ### Please RESET the board ### Thanks, Rick > +} > + > static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, > char *const argv[]) > { > @@ -16,6 +27,8 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, } > > static struct cmd_tbl cmd_sub[] = { > + U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned, > + "", ""), > U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined, > "", ""), > }; > @@ -23,7 +36,8 @@ static struct cmd_tbl cmd_sub[] = { static char exception_help_text[] = > "<ex>\n" > " The following exceptions are available:\n" > - " undefined - undefined instruction\n" > + " undefined - illegal instruction\n" > + " unaligned - load address misaligned\n" > ; > > #include <exception.h> > -- > 2.27.0

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[PATCH v1] arm: socfpga: Use DM watchdog timer
by Chee Hong Ang 06 Aug '20

06 Aug '20

All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4 ++++ arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 4 ++++ arch/arm/dts/socfpga_stratix10.dtsi | 1 - arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++++ arch/arm/mach-socfpga/spl_agilex.c | 2 +- arch/arm/mach-socfpga/spl_s10.c | 2 +- configs/socfpga_agilex_defconfig | 2 ++ 7 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index debeb8b..6cac36a 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -40,3 +40,7 @@ &qspi { status = "okay"; }; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi index 58cd497..22e614d 100644 --- a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi @@ -15,3 +15,7 @@ &uart1 { u-boot,dm-pre-reloc; }; + +&watchdog1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index a8e61cf..cb799bc 100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -386,7 +386,6 @@ reg = <0xffd00200 0x100>; interrupts = <0 117 4>; resets = <&rst WATCHDOG0_RESET>; - u-boot,dm-pre-reloc; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index b7b48a5..fceae93 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -137,3 +137,7 @@ &usb0 { status = "okay"; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index bd971ec..6896c07 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -51,11 +51,11 @@ void board_init_f(ulong dummy) socfpga_get_managers_addr(); -#ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); +#ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index b3c6f6a..ad15ed1 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -53,11 +53,11 @@ void board_init_f(ulong dummy) socfpga_get_managers_addr(); -#ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); +#ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 2885c60..41bd925 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -60,4 +60,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -- 2.2.0

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[PATCH v1 0/2] Print reset information in SPL
by Chee Hong Ang 06 Aug '20

06 Aug '20

Show reset information such as reset types (cold/warm) and which events triggered the reset. Chee Hong Ang (2): arm: socfpga: soc64: Add SDM triggered warm reset bit mask arm: socfpga: soc64: Show reset state in SPL .../include/mach/reset_manager_soc64.h | 12 ++++++++++-- arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++++++++++++++++++++++ arch/arm/mach-socfpga/spl_agilex.c | 1 + arch/arm/mach-socfpga/spl_s10.c | 1 + 4 files changed, 34 insertions(+), 2 deletions(-) -- 2.2.0

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