June 2020 - U-Boot

[PATCH 00/22] x86: Enhance MTRR functionality to support multiple CPUs
by Simon Glass 10 Jun '20

10 Jun '20

At present MTRRs are mirrored to the secondary CPUs only once, as those CPUs are started up. But U-Boot may add more MTRRs later, e.g. if it decides that a video console must be set up. This series enhances the x86 multi-processor support to allow MTRRs to be updated at any time. It also updates the 'mtrr' command to support setting the MTRRs on CPUs other than the boot CPU. Simon Glass (22): x86: mp_init: Switch to livetree x86: Move MP code into mp_init x86: mp_init: Avoid declarations in header files x86: mp_init: Switch parameter names in start_aps() x86: mp_init: Drop the num_cpus static variable x86: mtrr: Fix 'ensable' typo x86: mp_init: Set up the CPU numbers at the start x86: mp_init: Adjust bsp_init() to return more information x86: cpu: Remove unnecessary #ifdefs x86: mp: Support APs waiting for instructions global_data: Add a generic global_data flag for SMP state x86: Set the SMP flag when MP init is complete x86: mp: Allow running functions on multiple CPUs x86: mp: Park CPUs before running the OS x86: mp: Add iterators for CPUs x86: mtrr: Use MP calls to list the MTRRs x86: mtrr: Update MTRRs on all CPUs x86: mtrr: Add support for writing to MTRRs on any CPU x86: mtrr: Update the command to use the new mtrr calls x86: mtrr: Restructure so command execution is in one place x86: mtrr: Update 'mtrr' to allow setting MTRRs on any CPU x86: mtrr: Enhance 'mtrr' command to list MTRRs on any CPU arch/x86/cpu/cpu.c | 63 ++--- arch/x86/cpu/i386/cpu.c | 26 +-- arch/x86/cpu/mp_init.c | 377 +++++++++++++++++++++++++----- arch/x86/cpu/mtrr.c | 149 ++++++++++++ arch/x86/include/asm/mp.h | 118 ++++++++-- arch/x86/include/asm/mtrr.h | 51 ++++ cmd/x86/mtrr.c | 148 ++++++++---- include/asm-generic/global_data.h | 1 + include/dm/uclass.h | 2 +- 9 files changed, 751 insertions(+), 184 deletions(-) -- 2.27.0.rc0.183.gde8f92d652-goog

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[PATCH v2] mmc: sdhci: Fix HISPD bit handling
by Jagan Teki 10 Jun '20

10 Jun '20

SDHCI HISPD bits need to be configured based on desired mmc timings mode and some HISPD quirks. So, handle the HISPD bit based on the mmc computed selected mode(timing parameter) rather than fixed mmc card clock frequency. Linux handle the HISPD similar like this in below commit, commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling") This eventually fixed the mmc write issue observed in rk3399 sdhci controller. Bug log for refernece, => gpt write mmc 0 $partitions Writing GPT: mmc write failed ** Can't write to device 0 ** ** Can't write to device 0 ** error! Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Peng Fan <peng.fan(a)nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v2: - collect Jaehoon R-b drivers/mmc/sdhci.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 92cc8434af..280b8c88eb 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -594,14 +594,21 @@ static int sdhci_set_ios(struct mmc *mmc) ctrl &= ~SDHCI_CTRL_4BITBUS; } - if (mmc->clock > 26000000) - ctrl |= SDHCI_CTRL_HISPD; - else - ctrl &= ~SDHCI_CTRL_HISPD; - - if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) || - (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) - ctrl &= ~SDHCI_CTRL_HISPD; + if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) || + !(host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) { + if (mmc->selected_mode == MMC_HS || + mmc->selected_mode == SD_HS || + mmc->selected_mode == MMC_DDR_52 || + mmc->selected_mode == MMC_HS_200 || + mmc->selected_mode == MMC_HS_400 || + mmc->selected_mode == UHS_SDR25 || + mmc->selected_mode == UHS_SDR50 || + mmc->selected_mode == UHS_SDR104 || + mmc->selected_mode == UHS_DDR50) + ctrl |= SDHCI_CTRL_HISPD; + else + ctrl &= ~SDHCI_CTRL_HISPD; + } sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); -- 2.25.1

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[PATCH] nvme: Invalidate dcache before submitting admin cmd
by Jagan Teki 10 Jun '20

10 Jun '20

Some architecture like ARM Cortex A53, A72 would need to invalidate dcache to sync the cache with the memory contents before flushing the cache to memory. The NVME here submitting the admin command using dma_addr to the memory without prior cache invalidation. This causing dma_addr is pointing to an invalid location in the memory and found the sane nvme_ctrl result. Below example shows the nvme disk scan result improper result => nvme scan nvme_get_info_from_identify: nn = 544502629, vwc = 100, sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105 So, invalidating the cache before submitting the admin command makes the dma_addr points to a valid location in the memory. Cc: Andre Przywara <andre.przywara(a)arm.com> Reported-by: Suniel Mahesh <sunil(a)amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> Tested-by: Suniel Mahesh <sunil(a)amarulasolutions.com> --- drivers/nvme/nvme.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index 0357aba7f1..fc64d93ab8 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -466,6 +466,9 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid, c.identify.cns = cpu_to_le32(cns); + invalidate_dcache_range(dma_addr, + dma_addr + sizeof(struct nvme_id_ctrl)); + ret = nvme_submit_admin_cmd(dev, &c, NULL); if (!ret) invalidate_dcache_range(dma_addr, -- 2.25.1

4 6

[PATCH 0/7] mmc: zynqmp_sdhci: Add support for Tap delay
by Michal Simek 10 Jun '20

10 Jun '20

Hi, this patchset adding support for Tap delay programming for ZynqMP and Versal. Based on mainline discussion also DT properties have been introduced which are documented here. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/D… The patchset is using these DT properties which are optional. Default values are also listed. The patchset is based on: https://lists.denx.de/pipermail/u-boot/2020-May/410326.html Also new code is adding checking for SOCs which are not needed at that time when patch is applied (For example "mmc: zynq_sdhci: Read clock phase delays from dt" and IS_ENABLED(CONFIG_ARCH_ZYNQMP)... But I kept it there for more cleaner patches built on the top. Thanks, Michal Ashok Reddy Soma (5): Revert "mmc: zynq: parse dt when probing" mmc: zynq_sdhci: Define timing macro's mmc: zynq_sdhci: Set tapdelays based on clk phase delays mmc: zynq_sdhci: Add clock phase delays for Versal mmc: zynq_sdhci: Extend UHS timings till hs200 Michal Simek (2): mmc: zynq_sdhci: Move macro to the top mmc: zynq_sdhci: Read clock phase delays from dt drivers/mmc/sdhci.c | 3 +- drivers/mmc/zynq_sdhci.c | 406 ++++++++++++++++++++++++++++++++++++--- include/mmc.h | 13 ++ include/sdhci.h | 1 + 4 files changed, 398 insertions(+), 25 deletions(-) -- 2.26.2

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[PATCH v2 0/3] add FIT image support for broadcom NS3 soc
by Rayagonda Kokatanur 10 Jun '20

10 Jun '20

This is third patch set series prepared on top of second patch set ("add basic driver support for broadcom NS3 soc"). This patch set enables FIT config and add FIT image its files and keys. Changes from v1: -Address self review comments, Rebase on top of latest uboot and updated previous patch series. Pramod Kumar (2): board: ns3: add FIT image its file board: ns3: add development keys used in FIT Rayagonda Kokatanur (1): configs: ns3: enable FIT config board/broadcom/bcmns3/fit/keys/dev.crt | 21 +++++++++ board/broadcom/bcmns3/fit/keys/dev.key | 28 ++++++++++++ board/broadcom/bcmns3/fit/multi.its | 59 ++++++++++++++++++++++++++ configs/bcm_ns3_defconfig | 5 +++ 4 files changed, 113 insertions(+) create mode 100644 board/broadcom/bcmns3/fit/keys/dev.crt create mode 100644 board/broadcom/bcmns3/fit/keys/dev.key create mode 100644 board/broadcom/bcmns3/fit/multi.its -- 2.17.1

1 3

[PATCH v2 00/35] dm: Add programmatic generation of ACPI tables (part B)
by Simon Glass 10 Jun '20

10 Jun '20

NOTE: I have resent this as v1 to avoid confusion This is split from the original series in an attempt to get things applied in chunks. This part includes: - writing basic ACPI code for integers, strings, names, packages - writing descriptors for GPIO, I2C, interrupts, SPI - writing code to enable/disable ACPI peripherals via GPIOs - writing SSDT and DSDT tables - additional ways to determine ACPI device names Much of this code is taken from coreboot and I have tried to avoid changing the original code for no reason. Changes include: - splitting the acpi_dp functions into their own file - adding tests - adding (lots of) comments - using a context pointer instead of global variables - tidying up some code where couldn't resist (e.g. acpigen_emit_namestring()) Changes in v2: - Fix memset of I2C descriptor - Fix memset of SPI descriptor Changes in v1: - Capitalise ACPI_OPS_PTR - Split into more patches for review - Add tests - Rebase on top of common.h series - Fix 'the an' typo - Move header definitions into this patch - Update sandbox driver slightly for testing - Switch parameter order of _acpi_fill_ssdt() and make it static - Fix 'sentinal' and 'METHOD_FILL_SDDT' typos - Correct the commit subject - Generalise the ACPI function recursion with acpi_recurse_method() - Generalise the ACPI function recursion with acpi_recurse_method() - Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR - Update ACPI_DSTATUS enum - Drop writing of coreboot tables - Generalise the ACPI function recursion with acpi_recurse_method() - Use acpi,ddn instead of acpi,desc - Rename to acpi_device_infer_name() - Update newly created sandbox tests Simon Glass (35): dm: core: Add an ACPI name for the root node acpi: Add a function to get a device path and scope acpi: Add a way to check device status irq: Add a method to convert an interrupt to ACPI acpi: Support generation of ACPI code acpi: Support generation of interrupt descriptor gpio: Add a method to convert a GPIO to ACPI acpi: Support string output acpi: Support generation of GPIO descriptor acpi: Support generation of a GPIO/irq for a device acpi: Support generation of I2C descriptor acpi: Support generation of SPI descriptor acpigen: Support writing a length acpigen: Support writing a package acpi: Support writing an integer acpi: Support writing a string acpi: Support writing a name acpi: Support writing a UUID acpi: Support writing Device Properties objects via _DSD acpi: Support writing a GPIO acpi: Support copying properties from device tree to ACPI acpi: Add support for various misc ACPI opcodes acpi: Add support for writing a Power Resource acpi: Add support for writing a GPIO power sequence acpi: Add support for a generic power sequence acpi: Add support for SSDT generation x86: acpi: Move MADT down a bit acpi: Record the items added to SSDT acpi: Support ordering SSDT data by device x86: Allow devices to write an SSDT acpi: Add support for DSDT generation x86: Allow devices to write to DSDT pci: Avoid a crash in device_is_on_pci_bus() dm: acpi: Enhance acpi_get_name() acpi: Add an acpi split command arch/sandbox/dts/test.dts | 14 +- arch/x86/lib/acpi_table.c | 54 +- cmd/acpi.c | 15 +- doc/device-tree-bindings/chosen.txt | 9 + doc/device-tree-bindings/device.txt | 13 + drivers/core/acpi.c | 207 ++++++- drivers/core/root.c | 13 + drivers/gpio/gpio-uclass.c | 21 + drivers/gpio/sandbox.c | 86 +++ drivers/i2c/sandbox_i2c.c | 1 + drivers/misc/irq-uclass.c | 18 +- drivers/misc/irq_sandbox.c | 16 + drivers/rtc/sandbox_rtc.c | 13 + drivers/spi/sandbox_spi.c | 1 + include/acpi/acpi_device.h | 401 +++++++++++++ include/acpi/acpi_dp.h | 283 +++++++++ include/acpi/acpi_table.h | 6 + include/acpi/acpigen.h | 347 +++++++++++ include/asm-generic/gpio.h | 27 + include/dm/acpi.h | 63 ++ include/dm/device.h | 2 +- include/irq.h | 43 ++ include/spi.h | 4 +- include/test/ut.h | 17 + lib/acpi/Makefile | 3 + lib/acpi/acpi_device.c | 812 ++++++++++++++++++++++++++ lib/acpi/acpi_dp.c | 397 +++++++++++++ lib/acpi/acpigen.c | 477 +++++++++++++++ test/dm/Makefile | 2 + test/dm/acpi.c | 277 ++++++++- test/dm/acpi_dp.c | 511 +++++++++++++++++ test/dm/acpigen.c | 861 ++++++++++++++++++++++++++++ test/dm/gpio.c | 62 ++ test/dm/irq.c | 23 + test/dm/pci.c | 14 + 35 files changed, 5080 insertions(+), 33 deletions(-) create mode 100644 include/acpi/acpi_device.h create mode 100644 include/acpi/acpi_dp.h create mode 100644 include/acpi/acpigen.h create mode 100644 lib/acpi/acpi_device.c create mode 100644 lib/acpi/acpi_dp.c create mode 100644 lib/acpi/acpigen.c create mode 100644 test/dm/acpi_dp.c create mode 100644 test/dm/acpigen.c -- 2.26.2.645.ge9eca65c58-goog

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[PATCH] drivers: spi: Add SPI controller driver for Octeon
by Stefan Roese 10 Jun '20

10 Jun '20

From: Suneel Garapati <sgarapati(a)marvell.com> Adds support for SPI controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams(a)marvell.com> Signed-off-by: Suneel Garapati <sgarapati(a)marvell.com> Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Aaron Williams <awilliams(a)marvell.com> Cc: Chandrakala Chavva <cchavva(a)marvell.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> --- RFC -> v1 (Stefan): - Separated this patch from the OcteonTX/TX2 RFC patch series into a single patch. This is useful, as the upcoming MIPS Octeon support will use this driver. - Added MIPS Octeon II/III support (big endian). Rename driver and its function names from "octeontx" to "octeon" to better match all Octeon platforms. - Moved from union to defines / bitmasks. This makes the driver usage on little- and big-endian platforms much easier. - Enhanced Kconfig text - Removed all clock macros (use values from DT) - Dropped all #ifdef's - Misc minor cleanup drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/octeon_spi.c | 662 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 671 insertions(+) create mode 100644 drivers/spi/octeon_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 59415209ee..eeecdd2cbc 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -214,6 +214,14 @@ config NXP_FSPI Enable the NXP FlexSPI (FSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this NXP IP core. +config OCTEON_SPI + bool "Octeon SPI driver" + depends on ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2 + help + Enable the Octeon SPI driver. This driver can be used to + access the SPI NOR flash on Octeon II/III and OcteonTX/TX2 + SoC platforms. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 342776404a..ee4b277f21 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o +obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o obj-$(CONFIG_PIC32_SPI) += pic32_spi.o obj-$(CONFIG_PL022_SPI) += pl022_spi.o diff --git a/drivers/spi/octeon_spi.c b/drivers/spi/octeon_spi.c new file mode 100644 index 0000000000..f36da93749 --- /dev/null +++ b/drivers/spi/octeon_spi.c @@ -0,0 +1,662 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <spi-mem.h> +#include <watchdog.h> +#include <asm/io.h> +#include <asm/unaligned.h> +#include <linux/bitfield.h> +#include <linux/compat.h> +#include <linux/delay.h> + +#define OCTEON_SPI_MAX_BYTES 9 +#define OCTEON_SPI_MAX_CLOCK_HZ 50000000 + +#define OCTEON_SPI_NUM_CS 4 + +#define OCTEON_SPI_CS_VALID(cs) ((cs) < OCTEON_SPI_NUM_CS) + +#define MPI_CFG 0x0000 +#define MPI_STS 0x0008 +#define MPI_TX 0x0010 +#define MPI_XMIT 0x0018 +#define MPI_WIDE_DAT 0x0040 +#define MPI_IO_CTL 0x0048 +#define MPI_DAT(X) (0x0080 + ((X) << 3)) +#define MPI_WIDE_BUF(X) (0x0800 + ((X) << 3)) +#define MPI_CYA_CFG 0x1000 +#define MPI_CLKEN 0x1080 + +#define MPI_CFG_ENABLE BIT_ULL(0) +#define MPI_CFG_IDLELO BIT_ULL(1) +#define MPI_CFG_CLK_CONT BIT_ULL(2) +#define MPI_CFG_WIREOR BIT_ULL(3) +#define MPI_CFG_LSBFIRST BIT_ULL(4) +#define MPI_CFG_CS_STICKY BIT_ULL(5) +#define MPI_CFG_CSHI BIT_ULL(7) +#define MPI_CFG_IDLECLKS GENMASK_ULL(9, 8) +#define MPI_CFG_TRITX BIT_ULL(10) +#define MPI_CFG_CSLATE BIT_ULL(11) +#define MPI_CFG_CSENA0 BIT_ULL(12) +#define MPI_CFG_CSENA1 BIT_ULL(13) +#define MPI_CFG_CSENA2 BIT_ULL(14) +#define MPI_CFG_CSENA3 BIT_ULL(15) +#define MPI_CFG_CLKDIV GENMASK_ULL(28, 16) +#define MPI_CFG_LEGACY_DIS BIT_ULL(31) +#define MPI_CFG_IOMODE GENMASK_ULL(35, 34) +#define MPI_CFG_TB100_EN BIT_ULL(49) + +#define MPI_DAT_DATA GENMASK_ULL(7, 0) + +#define MPI_STS_BUSY BIT_ULL(0) +#define MPI_STS_MPI_INTR BIT_ULL(1) +#define MPI_STS_RXNUM GENMASK_ULL(12, 8) + +#define MPI_TX_TOTNUM GENMASK_ULL(4, 0) +#define MPI_TX_TXNUM GENMASK_ULL(12, 8) +#define MPI_TX_LEAVECS BIT_ULL(16) +#define MPI_TX_CSID GENMASK_ULL(21, 20) + +#define MPI_XMIT_TOTNUM GENMASK_ULL(10, 0) +#define MPI_XMIT_TXNUM GENMASK_ULL(30, 20) +#define MPI_XMIT_BUF_SEL BIT_ULL(59) +#define MPI_XMIT_LEAVECS BIT_ULL(60) +#define MPI_XMIT_CSID GENMASK_ULL(62, 61) + +enum { + PROBE_PCI = 0, /* PCI based probing */ + PROBE_DT, /* DT based probing */ +}; + +/* Used on Octeon TX2 */ +void board_acquire_flash_arb(bool acquire); + +struct octeon_spi_data { + int probe; + u32 reg_offs; +}; + +/* Local driver data structure */ +struct octeon_spi { + void __iomem *base; /* Register base address */ + const struct octeon_spi_data *data; + struct clk clk; + + u32 clkdiv; /* Clock divisor for device speed */ +}; + +static u64 octeon_spi_set_mpicfg(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + u64 mpi_cfg; + uint max_speed = slave->max_hz; + bool cpha, cpol; + + if (!max_speed) + max_speed = 12500000; + if (max_speed > OCTEON_SPI_MAX_CLOCK_HZ) + max_speed = OCTEON_SPI_MAX_CLOCK_HZ; + + debug("\n slave params %d %d %d\n", slave->cs, + slave->max_hz, slave->mode); + cpha = !!(slave->mode & SPI_CPHA); + cpol = !!(slave->mode & SPI_CPOL); + + mpi_cfg = FIELD_PREP(MPI_CFG_CLKDIV, priv->clkdiv & 0x1fff) | + FIELD_PREP(MPI_CFG_CSHI, !!(slave->mode & SPI_CS_HIGH)) | + FIELD_PREP(MPI_CFG_LSBFIRST, !!(slave->mode & SPI_LSB_FIRST)) | + FIELD_PREP(MPI_CFG_WIREOR, !!(slave->mode & SPI_3WIRE)) | + FIELD_PREP(MPI_CFG_IDLELO, cpha != cpol) | + FIELD_PREP(MPI_CFG_CSLATE, cpha) | + MPI_CFG_CSENA0 | MPI_CFG_CSENA1 | + MPI_CFG_CSENA2 | MPI_CFG_CSENA1 | + MPI_CFG_ENABLE; + + debug("\n mpi_cfg %llx\n", mpi_cfg); + return mpi_cfg; +} + +/** + * Wait until the SPI bus is ready + * + * @param dev SPI device to wait for + */ +static void octeon_spi_wait_ready(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_sts; + + do { + mpi_sts = readq(base + MPI_STS); + WATCHDOG_RESET(); + } while (mpi_sts & MPI_STS_BUSY); + + debug("%s(%s)\n", __func__, dev->name); +} + +/** + * Claim the bus for a slave device + * + * @param dev SPI bus + * + * @return 0 for success, -EINVAL if chip select is invalid + */ +static int octeon_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_cfg; + + debug("\n\n%s(%s)\n", __func__, dev->name); + if (!OCTEON_SPI_CS_VALID(spi_chip_select(dev))) + return -EINVAL; + + if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) + board_acquire_flash_arb(true); + + mpi_cfg = readq(base + MPI_CFG); + mpi_cfg &= ~MPI_CFG_TRITX; + mpi_cfg |= MPI_CFG_ENABLE; + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(5); /** Wait for bus to settle */ + + return 0; +} + +/** + * Release the bus to a slave device + * + * @param dev SPI bus + * + * @return 0 for success, -EINVAL if chip select is invalid + */ +static int octeon_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_cfg; + + debug("%s(%s)\n\n", __func__, dev->name); + if (!OCTEON_SPI_CS_VALID(spi_chip_select(dev))) + return -EINVAL; + + if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) + board_acquire_flash_arb(false); + + mpi_cfg = readq(base + MPI_CFG); + mpi_cfg &= ~MPI_CFG_ENABLE; + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(1); + + return 0; +} + +static int octeon_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_tx; + u64 mpi_cfg; + u64 wide_dat = 0; + int len = bitlen / 8; + int i; + const u8 *tx_data = dout; + u8 *rx_data = din; + int cs = spi_chip_select(dev); + + if (!OCTEON_SPI_CS_VALID(cs)) + return -EINVAL; + + debug("\n %s(%s, %u, %p, %p, 0x%lx), cs: %d\n", + __func__, dev->name, bitlen, dout, din, flags, cs); + + mpi_cfg = octeon_spi_set_mpicfg(dev); + if (mpi_cfg != readq(base + MPI_CFG)) { + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(10); + } + + debug("\n mpi_cfg upd %llx\n", mpi_cfg); + + /* + * Start by writing and reading 8 bytes at a time. While we can support + * up to 10, it's easier to just use 8 with the MPI_WIDE_DAT register. + */ + while (len > 8) { + if (tx_data) { + wide_dat = get_unaligned((u64 *)tx_data); + debug(" tx: %016llx \t", (unsigned long long)wide_dat); + tx_data += 8; + writeq(wide_dat, base + MPI_WIDE_DAT); + } + + mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) | + FIELD_PREP(MPI_TX_LEAVECS, 1) | + FIELD_PREP(MPI_TX_TXNUM, tx_data ? 8 : 0) | + FIELD_PREP(MPI_TX_TOTNUM, 8); + writeq(mpi_tx, base + MPI_TX); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + wide_dat = readq(base + MPI_WIDE_DAT); + debug(" rx: %016llx\t", (unsigned long long)wide_dat); + *(u64 *)rx_data = wide_dat; + rx_data += 8; + } + len -= 8; + } + + debug("\n "); + + /* Write and read the rest of the data */ + if (tx_data) { + for (i = 0; i < len; i++) { + debug(" tx: %02x\n", *tx_data); + writeq(*tx_data++, base + MPI_DAT(i)); + } + } + + mpi_tx = FIELD_PREP(MPI_TX_CSID, cs) | + FIELD_PREP(MPI_TX_LEAVECS, !(flags & SPI_XFER_END)) | + FIELD_PREP(MPI_TX_TXNUM, tx_data ? len : 0) | + FIELD_PREP(MPI_TX_TOTNUM, len); + writeq(mpi_tx, base + MPI_TX); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + for (i = 0; i < len; i++) { + *rx_data = readq(base + MPI_DAT(i)) & 0xff; + debug(" rx: %02x\n", *rx_data); + rx_data++; + } + } + + return 0; +} + +static int octeontx2_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct octeon_spi *priv = dev_get_priv(bus); + void *base = priv->base; + u64 mpi_xmit; + u64 mpi_cfg; + u64 wide_dat = 0; + int len = bitlen / 8; + int rem; + int i; + const u8 *tx_data = dout; + u8 *rx_data = din; + int cs = spi_chip_select(dev); + + if (!OCTEON_SPI_CS_VALID(cs)) + return -EINVAL; + + debug("\n %s(%s, %u, %p, %p, 0x%lx), cs: %d\n", + __func__, dev->name, bitlen, dout, din, flags, cs); + + mpi_cfg = octeon_spi_set_mpicfg(dev); + + mpi_cfg |= MPI_CFG_TRITX | MPI_CFG_LEGACY_DIS | MPI_CFG_CS_STICKY | + MPI_CFG_TB100_EN; + + mpi_cfg &= ~MPI_CFG_IOMODE; + if (flags & (SPI_TX_DUAL | SPI_RX_DUAL)) + mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 2); + if (flags & (SPI_TX_QUAD | SPI_RX_QUAD)) + mpi_cfg |= FIELD_PREP(MPI_CFG_IOMODE, 3); + + if (mpi_cfg != readq(base + MPI_CFG)) { + writeq(mpi_cfg, base + MPI_CFG); + mpi_cfg = readq(base + MPI_CFG); + udelay(10); + } + + debug("\n mpi_cfg upd %llx\n\n", mpi_cfg); + + /* Start by writing or reading 1024 bytes at a time. */ + while (len > 1024) { + if (tx_data) { + /* 8 bytes per iteration */ + for (i = 0; i < 128; i++) { + wide_dat = get_unaligned((u64 *)tx_data); + debug(" tx: %016llx \t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + tx_data += 8; + writeq(wide_dat, base + MPI_WIDE_BUF(i)); + } + } + + mpi_xmit = FIELD_PREP(MPI_XMIT_CSID, cs) | MPI_XMIT_LEAVECS | + FIELD_PREP(MPI_XMIT_TXNUM, tx_data ? 1024 : 0) | + FIELD_PREP(MPI_XMIT_TOTNUM, 1024); + writeq(mpi_xmit, base + MPI_XMIT); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + /* 8 bytes per iteration */ + for (i = 0; i < 128; i++) { + wide_dat = readq(base + MPI_WIDE_BUF(i)); + debug(" rx: %016llx\t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + *(u64 *)rx_data = wide_dat; + rx_data += 8; + } + } + len -= 1024; + } + + if (tx_data) { + rem = len % 8; + /* 8 bytes per iteration */ + for (i = 0; i < len / 8; i++) { + wide_dat = get_unaligned((u64 *)tx_data); + debug(" tx: %016llx \t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + tx_data += 8; + writeq(wide_dat, base + MPI_WIDE_BUF(i)); + } + if (rem) { + memcpy(&wide_dat, tx_data, rem); + debug(" rtx: %016llx\t", wide_dat); + writeq(wide_dat, base + MPI_WIDE_BUF(i)); + } + } + + mpi_xmit = FIELD_PREP(MPI_XMIT_CSID, cs) | + FIELD_PREP(MPI_XMIT_LEAVECS, !(flags & SPI_XFER_END)) | + FIELD_PREP(MPI_XMIT_TXNUM, tx_data ? len : 0) | + FIELD_PREP(MPI_XMIT_TOTNUM, len); + writeq(mpi_xmit, base + MPI_XMIT); + + octeon_spi_wait_ready(dev); + + debug("\n "); + + if (rx_data) { + rem = len % 8; + /* 8 bytes per iteration */ + for (i = 0; i < len / 8; i++) { + wide_dat = readq(base + MPI_WIDE_BUF(i)); + debug(" rx: %016llx\t", + (unsigned long long)wide_dat); + if ((i % 4) == 3) + debug("\n"); + *(u64 *)rx_data = wide_dat; + rx_data += 8; + } + if (rem) { + wide_dat = readq(base + MPI_WIDE_BUF(i)); + debug(" rrx: %016llx\t", + (unsigned long long)wide_dat); + memcpy(rx_data, &wide_dat, rem); + rx_data += rem; + } + } + + return 0; +} + +static bool octeon_spi_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + /* For now, support only below combinations + * 1-1-1 + * 1-1-2 1-2-2 + * 1-1-4 1-4-4 + */ + if (op->cmd.buswidth != 1) + return false; + return true; +} + +static int octeon_spi_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + unsigned long flags = SPI_XFER_BEGIN; + const void *tx; + void *rx; + u8 opcode, *buf; + u8 *addr; + int i, temp, ret; + + if (op->cmd.buswidth != 1) + return -ENOTSUPP; + + /* Send CMD */ + i = 0; + opcode = op->cmd.opcode; + + if (!op->data.nbytes && !op->addr.nbytes && !op->dummy.nbytes) + flags |= SPI_XFER_END; + + ret = octeon_spi_xfer(slave->dev, 8, (void *)&opcode, NULL, + flags); + if (ret < 0) + return ret; + + /* Send Address and dummy */ + if (op->addr.nbytes) { + /* Alloc buffer for address+dummy */ + buf = (u8 *)calloc(1, op->addr.nbytes + op->dummy.nbytes); + if (!buf) { + printf("%s Out of memory\n", __func__); + return -ENOMEM; + } + addr = (u8 *)&op->addr.val; + for (temp = 0; temp < op->addr.nbytes; temp++) + buf[i++] = *(u8 *)(addr + op->addr.nbytes - 1 - temp); + for (temp = 0; temp < op->dummy.nbytes; temp++) + buf[i++] = 0xff; + if (op->addr.buswidth == 2) + flags |= SPI_RX_DUAL; + if (op->addr.buswidth == 4) + flags |= SPI_RX_QUAD; + + if (!op->data.nbytes) + flags |= SPI_XFER_END; + ret = octeon_spi_xfer(slave->dev, i * 8, (void *)buf, NULL, + flags); + free(buf); + if (ret < 0) + return ret; + } + if (!op->data.nbytes) + return 0; + + /* Send/Receive Data */ + flags |= SPI_XFER_END; + if (op->data.buswidth == 2) + flags |= SPI_RX_DUAL; + if (op->data.buswidth == 4) + flags |= SPI_RX_QUAD; + + rx = (op->data.dir == SPI_MEM_DATA_IN) ? op->data.buf.in : NULL; + tx = (op->data.dir == SPI_MEM_DATA_OUT) ? op->data.buf.out : NULL; + + ret = octeon_spi_xfer(slave->dev, (op->data.nbytes * 8), tx, rx, + flags); + return ret; +} + +static const struct spi_controller_mem_ops octeontx2_spi_mem_ops = { + .supports_op = octeon_spi_supports_op, + .exec_op = octeon_spi_exec_op, +}; + +/** + * Set the speed of the SPI bus + * + * @param bus bus to set + * @param max_hz maximum speed supported + */ +static int octeon_spi_set_speed(struct udevice *bus, uint max_hz) +{ + struct octeon_spi *priv = dev_get_priv(bus); + ulong clk_rate; + u32 calc_hz; + + if (max_hz > OCTEON_SPI_MAX_CLOCK_HZ) + max_hz = OCTEON_SPI_MAX_CLOCK_HZ; + + clk_rate = clk_get_rate(&priv->clk); + if (IS_ERR_VALUE(clk_rate)) + return -EINVAL; + + debug("%s(%s, %u, %lu)\n", __func__, bus->name, max_hz, clk_rate); + + priv->clkdiv = clk_rate / (2 * max_hz); + while (1) { + calc_hz = clk_rate / (2 * priv->clkdiv); + if (calc_hz <= max_hz) + break; + priv->clkdiv += 1; + } + + if (priv->clkdiv > 8191) + return -1; + + debug("%s: clkdiov=%d\n", __func__, priv->clkdiv); + + return 0; +} + +static int octeon_spi_set_mode(struct udevice *bus, uint mode) +{ + /* We don't set it here */ + return 0; +} + +static int octeon_pci_spi_probe(struct udevice *dev) +{ + struct octeon_spi *priv = dev_get_priv(dev); + int ret; + + if (priv->data->probe == PROBE_PCI) { + pci_dev_t bdf = dm_pci_get_bdf(dev); + + debug("SPI PCI device: %x\n", bdf); + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + } else { + priv->base = dev_remap_addr(dev); + } + + priv->base += priv->data->reg_offs; + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + debug("SPI bus %s %d at %p\n", dev->name, dev->seq, priv->base); + + return 0; +} + +static const struct dm_spi_ops octeon_spi_ops = { + .claim_bus = octeon_spi_claim_bus, + .release_bus = octeon_spi_release_bus, + .xfer = octeon_spi_xfer, + .set_speed = octeon_spi_set_speed, + .set_mode = octeon_spi_set_mode, +}; + +static const struct dm_spi_ops octeontx2_spi_ops = { + .claim_bus = octeon_spi_claim_bus, + .release_bus = octeon_spi_release_bus, + .set_speed = octeon_spi_set_speed, + .set_mode = octeon_spi_set_mode, + .xfer = octeontx2_spi_xfer, + .mem_ops = &octeontx2_spi_mem_ops, +}; + +static const struct octeon_spi_data spi_octeon_data = { + .probe = PROBE_DT, + .reg_offs = 0x0000, +}; + +static const struct octeon_spi_data spi_octeontx_data = { + .probe = PROBE_PCI, + .reg_offs = 0x1000, +}; + +static const struct udevice_id octeon_spi_ids[] = { + { .compatible = "cavium,octeon-3010-spi", + .data = (ulong)&spi_octeon_data }, + { .compatible = "cavium,thunder-8190-spi", + .data = (ulong)&spi_octeontx_data }, + { } +}; + +static const struct udevice_id octeontx2_spi_ids[] = { + { .compatible = "cavium,thunder-8890-spi", + .data = (ulong)&spi_octeontx_data }, + { } +}; + +U_BOOT_DRIVER(octeon_pci_spi) = { + .name = "spi_octeon", + .id = UCLASS_SPI, + .of_match = octeon_spi_ids, + .probe = octeon_pci_spi_probe, + .priv_auto_alloc_size = sizeof(struct octeon_spi), + .ops = &octeon_spi_ops, +}; + +/* Octeon TX2 needs a different ops struct */ +U_BOOT_DRIVER(octeontx2_pci_spi) = { + .name = "spi_octeontx2", + .id = UCLASS_SPI, + .of_match = octeontx2_spi_ids, + .probe = octeon_pci_spi_probe, + .priv_auto_alloc_size = sizeof(struct octeon_spi), + .ops = &octeontx2_spi_ops, +}; + +static struct pci_device_id octeon_spi_supported[] = { + { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_MPI) }, + { }, +}; + +U_BOOT_PCI_DEVICE(octeon_pci_spi, octeon_spi_supported); +U_BOOT_PCI_DEVICE(octeontx2_pci_spi, octeon_spi_supported); -- 2.27.0

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[PATCH] armv8: ls1028ardb: add xspi parameter to qixis command
by andy.tang＠nxp.com 10 Jun '20

10 Jun '20

From: Yuantian Tang <andy.tang(a)nxp.com> Add xspi boot source to qixis command to let the soc boot from flex-nor flash chip. Signed-off-by: Yuantian Tang <andy.tang(a)nxp.com> --- board/freescale/common/qixis.c | 13 +++++++++++++ include/configs/ls1028ardb.h | 4 ++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index dd1ee90b3c..f4a8ad78c0 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -322,6 +322,19 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "xspi") == 0) { +#ifdef QIXIS_LBMAP_XSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_XSPI); + set_rcw_src(QIXIS_RCW_SRC_XSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); #endif } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 0f289cb078..4d65d5d38b 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -38,10 +38,10 @@ #define QIXIS_LBMAP_ALTBANK 0x00 #define QIXIS_LBMAP_SD 0x00 #define QIXIS_LBMAP_EMMC 0x00 -#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_LBMAP_XSPI 0x00 #define QIXIS_RCW_SRC_SD 0xf8 #define QIXIS_RCW_SRC_EMMC 0xf9 -#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RCW_SRC_XSPI 0xff #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10 #define QIXIS_RCFG_CTL_RECONFIG_START 0x11 -- 2.17.1

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[PATCH v2 1/5] fdtdec: Fix the types of addr and size in fdtdec_add_reserved_memory()
by Bin Meng 10 Jun '20

10 Jun '20

From: Bin Meng <bin.meng(a)windriver.com> fdtdec_get_addr_size() expects size is of type 'fdt_size_t', and return value is of type 'fdt_addr_t'. Adjust their types accordingly. Signed-off-by: Bin Meng <bin.meng(a)windriver.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- (no changes since v1) lib/fdtdec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 1f2b763..42f7a25 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1294,7 +1294,8 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, /* find a matching node and return the phandle to that */ fdt_for_each_subnode(node, blob, parent) { const char *name = fdt_get_name(blob, node, NULL); - phys_addr_t addr, size; + fdt_addr_t addr; + fdt_size_t size; addr = fdtdec_get_addr_size(blob, node, "reg", &size); if (addr == FDT_ADDR_T_NONE) { -- 2.7.4

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[PATCH 1/3] mx6ul_14x14_evk: Enable SPL USB and SDP support
by Otavio Salvador 09 Jun '20

09 Jun '20

This fixes the boot from USB loader, which is critical to easy the manufacture process. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- configs/mx6ul_14x14_evk_defconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 2906782b126..cad766443c2 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -22,6 +22,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -32,6 +35,8 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y @@ -46,6 +51,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y @@ -73,5 +79,10 @@ CONFIG_SOFT_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y -- 2.27.0

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