May 2020 - U-Boot

[PATCH] board: xilinx/zynqmp: Remove 1-second delay at boot
by Mike Looijmans 29 May '20

29 May '20

SPL boot is slow on the ZynqMP because of this delay. The initialization done in psu_init no longer requires an external delay, so this can be removed to speed up the SPL boot flow considerably. Signed-off-by: Mike Looijmans <mike.looijmans(a)topic.nl> --- board/xilinx/zynqmp/zynqmp.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index cb72914adb..d00235f236 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -32,7 +32,6 @@ #include <zynqmp_firmware.h> #include <g_dnl.h> #include <linux/bitops.h> -#include <linux/delay.h> #include <linux/sizes.h> #include "../common/board.h" @@ -334,9 +333,6 @@ int board_early_init_f(void) ret = psu_init(); if (ret) return ret; - - /* Delay is required for clocks to be propagated */ - udelay(1000000); #endif #ifdef CONFIG_DEBUG_UART -- 2.17.1

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[PATCH 0/5] Enable I2C in SPL, support runtime detection of add-on board
by sunil＠amarulasolutions.com 29 May '20

29 May '20

From: Suniel Mahesh <sunil(a)amarulasolutions.com> This patch series adds runtime detection of add-on board(ROC-RK3399-PC Mezzanine) by enabling I2C in SPL. This add on board hosts a CW2015 chip which is connected as slave to I2C2. In order to dynamically detect this add-on board at runtime, I2C2 is probed in SPL. If probe is successfull then a corresponding dtb is loaded, else regular dtb is loaded for the u-boot proper. Patch #1 moves board initialiation code after rk3399 init is done. Patch #2 enables I2C in SPL for any add-on board detection at run time. Patch #3 adds support for add-on board run-time detection. Patch #4 drops ROC-RK3399-PC Mezzanine board as this is an add-on board, it will be detected at runtime. Patch #5 enables PCIe/M.2 and NVMe, as this add-on board has a PCIe/M.2. Jagan Teki (1): rockchip: spl: Move board_early_init_f after cpu timer Suniel Mahesh (4): roc-pc-rk3399: Enable I2C in SPL for add-on board detection roc-pc-rk3399: Add support for add-on board run-time detection rk3399: drop ROC-RK3399-PC Mezzanine board roc-pc-rk3399: Enable PCIe/M.2, NVMe arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 13 +++++ arch/arm/mach-rockchip/spl.c | 5 +- board/firefly/roc-pc-rk3399/MAINTAINERS | 2 - board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 56 ++++++++++++++++++++++ configs/roc-pc-mezzanine-rk3399_defconfig | 74 ----------------------------- configs/roc-pc-rk3399_defconfig | 10 +++- 6 files changed, 81 insertions(+), 79 deletions(-) delete mode 100644 configs/roc-pc-mezzanine-rk3399_defconfig -- 2.7.4

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[PATCH] rockchip: enable RNG on RockPro64
by Marcin Juszkiewicz 29 May '20

29 May '20

Signed-off-by: Marcin Juszkiewicz <marcin(a)juszkiewicz.com.pl> --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++++ configs/rockpro64-rk3399_defconfig | 2 ++ 2 files changed, 6 insertions(+) diff --git arch/arm/dts/rk3399-rockpro64-u-boot.dtsi arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index deaa3efd39..824ee4e3ce 100644 --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -23,3 +23,7 @@ &vdd_log { regulator-init-microvolt = <950000>; }; + +&rng { + status = "okay"; +}; diff --git configs/rockpro64-rk3399_defconfig configs/rockpro64-rk3399_defconfig index 53abce0057..04ba151475 100644 --- configs/rockpro64-rk3399_defconfig +++ configs/rockpro64-rk3399_defconfig @@ -43,6 +43,8 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y -- 2.26.2

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Failsafe booting to alternate linux image/fs
by Brendan Simon (eTRIX) 29 May '20

29 May '20

Hi, Before I embark on my own implementation of a failsafe bootloading process from my embedded system (Xilinx Zynq board booting from SD Card), I thought I'd quickly ask the experts if there are any standard implementations in u-boot. The current u-boot being used is from 2015. It probably needs to be updated (for various reasons). It is loaded from the first partition (64MB/FAT32) of an SD Card as part of a file called `BOOT.BIN`. The `Env.txt` file contains settings for two linux root systems (including kernel and dtb) on separate partitions (ext4/1GB). The first statement in `Env.txt` has a `part=2` or `part=3` to indicate, which partition to boot from (load kernel and set cmdline for rootfs, etc). My simple approach was to store a env var for the number of reboot attempts. On every boot attempt, the env var would be incremented. If linux booted successfully it would set the env var to zero (I believe there are linux tools to do that). If linux didn't boot successfully, eventually the reboot count env var would reach some value, where the alternative partition would be selected as an attempt to get something booting and up and running. NOTE: the devices are remote and need to be up as much as possible so they can be monitored/managed. *Does this type of functionality exist already in u-boot?* I'm guessing/hoping it does (and hope to use it directly or leverage the features that make sense) rather than reinventing the wheel. *Where is the best place to go to get information/documentation on this?* Finally, I'm looking at migrating to EMMC, maybe with a golden image for failsafe use, and two partitions for current filesystem and next/upgrade filesystem. *Is there any documentation that might be a useful in this use case?* Thanks, Brendan.

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[PATCH v12 00/18] RISC-V SiFive FU540 support SPL
by Pragnesh Patel 29 May '20

29 May '20

This series add support for SPL to FU540. U-Boot SPL can boot from L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. This series is also available here [1] for testing [1] https://github.com/pragnesh26992/u-boot/tree/spl How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y 2) export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin> 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) # sudo sgdisk --clear \ > --set-alignment=2 \ > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ > /dev/sda 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082 Changes in v12: - Rebase on mainline U-Boot Added necessary include files which are not part of common header now Remove unnecessary include files drivers/misc/sifive-otp.c +#include <linux/bitops.h> +#include <linux/delay.h> board/sifive/fu540/fu540.c -#include <common.h> +#include <log.h> board/sifive/fu540/spl.c +#include <init.h> +#include <log.h> +#include <linux/delay.h> drivers/ram/sifive/fu540_ddr.c +#include <linux/bitops.h> arch/riscv/cpu/fu540/cpu.c -#include <common.h> +#include <asm/cache.h> arch/riscv/cpu/fu540/spl.c -#include <common.h> +#include <log.h> board/sifive/fu540/spl.c -#include <common.h> +#include <init.h> +#include <log.h> +#include <linux/delay.h> - Update commit description for Release ethernet clock reset - Update OpenSBI building section in "doc/board/sifive/fu540.rst" Changes in v11: - Remove TPL related code and OF_PLATDATA from FU540 DDR driver (drivers/ram/sifive/fu540_ddr.c) - Update FU540 doc (doc/board/sifive/fu540.rst) Remove unnecessary print Changes in v10: - Update commit description for ethernet clock reset (https://patchwork.ozlabs.org/patch/1289003) - Update commit description for ddr clock initialization (https://patchwork.ozlabs.org/patch/1289000) Changes in v9: - Remove cache related patches from this series sifive: dts: fu540: Enable L2 Cache in U-Boot (https://patchwork.ozlabs.org/patch/1286705) riscv: sifive: fu540: enable all cache ways from U-Boot proper (https://patchwork.ozlabs.org/patch/1286706) - Rename SiFive DDR driver from sdram_fu540.c to fu540_ddr.c and also do some typo correction in driver - Remove CONFIG_SPL_BUILD for __prci_ddr_release_reset() - Release ethernet clock reset instead of ethernet clock initialization (https://patchwork.ozlabs.org/patch/1286697) - Squash fu540 cpu patches (https://patchwork.ozlabs.org/patch/1286699) (https://patchwork.ozlabs.org/patch/1286700) - Use spl_boot_device() instead of board_boot_order() Changes in v8: - Remove SPL_CRC7_SUPPORT Kconfig option and compile crc7.o when CONFIG_MMC_SPI selected - Add "TODO" in drivers/ram/sifive/sdram_fu540.c - Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c - Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed - Add 2 new patches sifive: fu540: Add sample SD gpt partition layout (https://patchwork.ozlabs.org/patch/1092) sifive: fu540: Add U-Boot proper sector start (https://patchwork.ozlabs.org/patch/1093) - Remove patch riscv: Enable cpu clock if it is present (https://patchwork.ozlabs.org/patch/1281573) - Update doc/board/sifive/fu540.rst for PLATFORM=generic Changes in v7: - Standardize SD gpt partition layout - Add delay for SiFive OTP driver - Use DM way for corepll and ddrpll - Add new cpu fu540 (arch/riscv/cpu/fu540) - Update document for FU540 (doc/board/sifive/fu540.rst) Changes in v6: - Typo Correction - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi Dual Licensed - Sync Hifive unleashed dts from Linux - Add arch/riscv/fu540 for FU540 specific code Changes in v5: - Return read/write bytes for sifive_otp_read and sifive_otp_write - Correct Palmer's email address Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Jagan Teki (2): sifive: fu540: Add sample SD gpt partition layout sifive: fu540: Add U-Boot proper sector start Pragnesh Patel (16): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings riscv: sifive: dts: fu540: add U-Boot dmc node clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: Add ddr clock initialization clk: sifive: fu540-prci: Release ethernet clock reset riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux riscv: cpu: fu540: Add support for cpu fu540 riscv: sifive: fu540: add SPL configuration configs: fu540: Add config options for U-Boot SPL doc: sifive: fu540: Add description for OpenSBI generic platform arch/riscv/Kconfig | 1 + arch/riscv/cpu/fu540/Kconfig | 15 + arch/riscv/cpu/fu540/Makefile | 11 + arch/riscv/cpu/fu540/cpu.c | 22 + arch/riscv/cpu/fu540/dram.c | 38 + arch/riscv/cpu/fu540/spl.c | 23 + arch/riscv/cpu/u-boot-spl.lds | 1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 84 + arch/riscv/dts/fu540-c000.dtsi | 37 +- .../dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 22 + arch/riscv/dts/hifive-unleashed-a00.dts | 9 + arch/riscv/include/asm/arch-fu540/clk.h | 14 + arch/riscv/include/asm/arch-fu540/gpio.h | 38 + arch/riscv/include/asm/arch-fu540/spl.h | 14 + board/sifive/fu540/Kconfig | 18 +- board/sifive/fu540/Makefile | 4 + board/sifive/fu540/fu540.c | 134 +- board/sifive/fu540/spl.c | 74 + common/spl/Kconfig | 3 +- configs/sifive_fu540_defconfig | 8 + doc/board/sifive/fu540.rst | 135 +- drivers/clk/sifive/fu540-prci.c | 177 +- drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/sifive-otp.c | 275 +++ drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/sifive/Kconfig | 13 + drivers/ram/sifive/Makefile | 6 + drivers/ram/sifive/fu540_ddr.c | 410 +++++ include/configs/sifive-fu540.h | 31 + lib/Makefile | 2 +- 33 files changed, 3013 insertions(+), 106 deletions(-) create mode 100644 arch/riscv/cpu/fu540/Kconfig create mode 100644 arch/riscv/cpu/fu540/Makefile create mode 100644 arch/riscv/cpu/fu540/cpu.c create mode 100644 arch/riscv/cpu/fu540/dram.c create mode 100644 arch/riscv/cpu/fu540/spl.c create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h create mode 100644 board/sifive/fu540/spl.c create mode 100644 drivers/misc/sifive-otp.c create mode 100644 drivers/ram/sifive/Kconfig create mode 100644 drivers/ram/sifive/Makefile create mode 100644 drivers/ram/sifive/fu540_ddr.c -- 2.17.1

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imx: move ATF to the back of the FIT to fix loading over yModem
by Patrick Wildt 29 May '20

29 May '20

With yModem the FIT Image is only supplied once, so we can only seek forward in the yModem supplied image and never backwards. With the recent changes to the SPL mechanism, including loading U-Boot first, FDT after, then the loadables, we must also reorder the FIT image script to make sure that the loadables are last in the FIT image. Signed-off-by: Patrick Wildt <patrick(a)blueri.se> diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh index dd1ca5ad3fd..fe12b7bb4bd 100755 --- a/arch/arm/mach-imx/mkimage_fit_atf.sh +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh @@ -62,6 +62,23 @@ cat << __HEADER_EOF compression = "none"; load = <$BL33_LOAD_ADDR>; }; +__HEADER_EOF + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt@$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF +cnt=$((cnt+1)) +done + +cat << __HEADER_EOF atf@1 { description = "ARM Trusted Firmware"; os = "arm-trusted-firmware"; @@ -88,20 +105,6 @@ cat << __HEADER_EOF __HEADER_EOF fi -cnt=1 -for dtname in $* -do - cat << __FDT_IMAGE_EOF - fdt@$cnt { - description = "$(basename $dtname .dtb)"; - data = /incbin/("$dtname"); - type = "flat_dt"; - compression = "none"; - }; -__FDT_IMAGE_EOF -cnt=$((cnt+1)) -done - cat << __CONF_HEADER_EOF }; configurations {

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[PATCH v2 0/4] update clock handler and proper cpu features
by Sagar Shrikant Kadam 29 May '20

29 May '20

U-Boot cmd "cpu detail" shows inconsistent CPU features and is missing clk_request and free handlers. The current "cpu detail" sometimes shows "Microcode" as a feature, which is not the case with FU540-C000 on HiFive Unleashed board. Patch 1: add clk request handler to check if valid clock id is requested. Patch 2: add cpu node aliases Patch 3: Correctly parse and update mmu-type. RISC-V core's on FU540-C000 SoC have separate instruction and data (split) L1 cache. Patch 4:Use i-cache-size dt property as one of identifier to indicate a split cache is available. I have picked few dependent patches from Sean's and Pragnesh's latest series from here [1]...[5]. These have applied on mainline U-Boot commit 8c48bb21bd6a ("Prepare v2020.07-rc3") Patch history: ============================================= V2: 1. Incorporate review comments from Bin and Sean Anderson. and dropped 2nd patch as similar work was already done in [1] & [2] 2 Add cpu node aliases to display cpu node's in sequence. 3. Add fix to show mmu as available cpu feature. 4. Check and append L1 cache feature. V1: Base version. Thanks to Vincent Chen <vincent.chen(a)sifive.com> for testing the V1 version of this series. [1] https://patchwork.ozlabs.org/patch/1295345 [2] https://patchwork.ozlabs.org/patch/1295346 [3] https://patchwork.ozlabs.org/patch/1297146 [4] https://patchwork.ozlabs.org/patch/1297147 [5] https://patchwork.ozlabs.org/patch/1297149 All these together is available here: https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v2 Sagar Shrikant Kadam (4): fu540: prci: add request and free clock handlers riscv: dts: hifive-unleashed-a00: add cpu aliases riscv: cpu: fixes to display proper CPU features riscv: cpu: check and append L1 cache to cpu features arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++ drivers/clk/sifive/fu540-prci.c | 21 +++++++++++++++++++++ drivers/cpu/riscv_cpu.c | 10 +++++++++- 3 files changed, 35 insertions(+), 1 deletion(-) -- 2.7.4

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[PATCH v2] spl: allow board_spl_fit_post_load() to fail
by Patrick Wildt 28 May '20

28 May '20

On i.MX platforms board_spl_fit_post_load() can check the loaded SPL image for authenticity using its HAB engine. U-Boot's SPL mechanism allows booting images from other sources as well, but in the current setup the SPL would just hang if it encounters an image that does not pass scrutiny. Allowing the function to return an error, allows the SPL to try booting from another source as a fallback instead of ending up as a brick. Signed-off-by: Patrick Wildt <patrick(a)blueri.se> --- Changes in v2: - set SPL_FIT_FOUND only after successful post load arch/arm/mach-imx/spl.c | 6 ++++-- common/spl/spl_fit.c | 10 ++++++---- include/spl.h | 2 +- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 1a231c67f5a..bbf398f18a7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -313,7 +313,7 @@ ulong board_spl_fit_size_align(ulong size) return size; } -void board_spl_fit_post_load(ulong load_addr, size_t length) +int board_spl_fit_post_load(ulong load_addr, size_t length) { u32 offset = length - CONFIG_CSF_SIZE; @@ -321,8 +321,10 @@ void board_spl_fit_post_load(ulong load_addr, size_t length) offset + IVT_SIZE + CSF_PAD_SIZE, offset)) { puts("spl: ERROR: image authentication unsuccessful\n"); - hang(); + return -1; } + + return 0; } #endif diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index f581a224213..ead4c6713af 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -26,8 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_BOOTM_LEN (64 << 20) #endif -__weak void board_spl_fit_post_load(ulong load_addr, size_t length) +__weak int board_spl_fit_post_load(ulong load_addr, size_t length) { + return 0; } __weak ulong board_spl_fit_size_align(ulong size) @@ -677,11 +678,12 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0) spl_image->entry_point = spl_image->load_addr; - spl_image->flags |= SPL_FIT_FOUND; - #ifdef CONFIG_IMX_HAB - board_spl_fit_post_load((ulong)fit, size); + ret = board_spl_fit_post_load((ulong)fit, size); + if (ret) + return ret; #endif + spl_image->flags |= SPL_FIT_FOUND; return 0; } diff --git a/include/spl.h b/include/spl.h index b31c9bb4ab2..2607767d940 100644 --- a/include/spl.h +++ b/include/spl.h @@ -564,7 +564,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, * board_spl_fit_post_load - allow process images after loading finished * */ -void board_spl_fit_post_load(ulong load_addr, size_t length); +int board_spl_fit_post_load(ulong load_addr, size_t length); /** * board_spl_fit_size_align - specific size align before processing payload -- 2.26.2

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[PATCH 0/4] bootefi fixes for aarch64/layerscape
by Michael Walle 28 May '20

28 May '20

I'm bringing up efiboot on a ARM64 board which runs without TF-a and PSCI, therefore the secondary cores are brought up by spin-tables. I ran into several problems. Here are the fixes. Michael Walle (4): efi_loader: aarch64: align runtime section to 64kb efi_loader: check alignment in efi_add_memory_map() fsl-layerscape: align first parameter of efi_add_memory_map() efi_loader: call smp_kick_all_cpus() arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/arm/cpu/armv8/u-boot.lds | 9 ++++++++- common/bootm.c | 9 +++++++++ lib/efi_loader/efi_memory.c | 18 +++++------------- lib/efi_loader/efi_setup.c | 6 ++++++ 5 files changed, 29 insertions(+), 15 deletions(-) -- 2.20.1

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[PATCH] dm: test: Add a test for dm_test_dev_read_addr_ptr()
by Simon Glass 28 May '20

28 May '20

Check the behaviour of this function. Hopefully this is start of a complete test suite for the dev_read...() functions. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Due to the nature of the test harness, this tests all cases: 1. CONFIG_OF_LIVE and livetree in use (normal sandbox test, gd->of_root is set) 2. CONFIG_OF_LIVE but livetree not yet in use (sandbox with gd->of_root = NULL) 3. !CONFIG_OF_LIVE (in sandbox_flattree) The third one is tested by 'make qcheck' which calls test/run test/dm/Makefile | 1 + test/dm/read.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 test/dm/read.c diff --git a/test/dm/Makefile b/test/dm/Makefile index 6c18fd04ce..ad2d3547f5 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_UT_DM) += bus.o obj-$(CONFIG_UT_DM) += nop.o +obj-$(CONFIG_UT_DM) += read.o obj-$(CONFIG_UT_DM) += test-driver.o obj-$(CONFIG_UT_DM) += test-fdt.o obj-$(CONFIG_UT_DM) += test-main.o diff --git a/test/dm/read.c b/test/dm/read.c new file mode 100644 index 0000000000..38b128b144 --- /dev/null +++ b/test/dm/read.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Livetree API + * + * Copyright 2020 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <mapmem.h> +#include <syscon.h> +#include <asm/test.h> +#include <dm/test.h> +#include <test/ut.h> + +/* Test that dev_read_addr_ptr() works in flattree and livetree */ +static int dm_test_dev_read_addr_ptr(struct unit_test_state *uts) +{ + struct udevice *gpio, *dev; + void *ptr; + + /* Test for missing reg property */ + ut_assertok(uclass_first_device_err(UCLASS_GPIO, &gpio)); + ut_assertnull(dev_read_addr_ptr(gpio)); + + ut_assertok(syscon_get_by_driver_data(SYSCON0, &dev)); + ptr = dev_read_addr_ptr(dev); + ut_asserteq(0x10, map_to_sysmem(ptr)); + + /* See dm_test_fdt_translation() which has more tests */ + + return 0; +} +DM_TEST(dm_test_dev_read_addr_ptr, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -- 2.27.0.rc0.183.gde8f92d652-goog

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