May 2020 - U-Boot

[PATCH] ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7
by Marek Vasut 23 Jun '20

23 Jun '20

The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx(a)nxp.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-mx7/mx7-ddr.h | 4 +++- arch/arm/mach-imx/mx7/ddr.c | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h index 37aaee0ad7..bea5dd8ec5 100644 --- a/arch/arm/include/asm/arch-mx7/mx7-ddr.h +++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h @@ -39,7 +39,9 @@ struct ddrc { u32 dramtmg8; /* 0x0120 */ u32 reserved7[0x17]; u32 zqctl0; /* 0x0180 */ - u32 reserved8[0x03]; + u32 zqctl1; /* 0x0184 */ + u32 zqctl2; /* 0x0188 */ + u32 zqstat; /* 0x018c */ u32 dfitmg0; /* 0x0190 */ u32 dfitmg1; /* 0x0194 */ u32 reserved9[0x02]; diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index 9713835bf2..9ffd8c6c66 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -58,6 +58,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5); writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8); writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0); + writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1); writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0); writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1); writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0); -- 2.25.1

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[PATCH v3 0/4] mx6cuboxi: enable support for OF_CONTROL and DM in SPL
by Walter Lozano 23 Jun '20

23 Jun '20

Make an additional step to add full DM support to mx6cuboxi, including its support for SPL With this new configuration SPL image is 50 KB, higher than the 38 KB from the previous version, but it still under the 68 KB limit. Changes in v3: - Cleanup Changes in v2: - Fix board_boot_order to avoid pointing to a NAND device - Fix board_boot_order to include MMC iomux - Remove unused code Walter Lozano (4): mx6cuboxi: enable MMC and eMMC in DT for SPL mx6cuboxi: customize board_boot_order to access eMMC mx6cuboxi: enable OF_CONTROL and DM in SPL mx6cuboxi: remove unused code ...qdl-hummingboard2-emmc-som-v15-u-boot.dtsi | 8 ++ board/solidrun/mx6cuboxi/mx6cuboxi.c | 113 ++++++++---------- configs/mx6cuboxi_defconfig | 3 + 3 files changed, 59 insertions(+), 65 deletions(-) -- 2.20.1

2 8

[PATCH] ARM: imx: soc: Select default TEXT_BASE for MX7
by Marek Vasut 23 Jun '20

23 Jun '20

Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot text base is picked as the one used by various MX7 boards. The SPL text base however is different. The SPL text base is set to 0x912000 instead of the usual 0x911000, that is because the 0x911000 value cannot work. Using 0x911000 as a SPL text base will result in the DCD header being placed below the 0x911000 address, which is a reserved SRAM area which must not be used. This will actually trigger eMMC boot failure on MX7D at least. Hence the increment. Update all boards affected by this SPL problem to the new SPL_TEXT_BASE. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx(a)nxp.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/mach-imx/mx7/Kconfig | 7 +++++++ configs/cl-som-imx7_defconfig | 2 -- configs/pico-dwarf-imx7d_defconfig | 2 -- configs/pico-hobbit-imx7d_defconfig | 2 -- configs/pico-imx7d_defconfig | 2 -- configs/pico-nymph-imx7d_defconfig | 2 -- configs/pico-pi-imx7d_defconfig | 2 -- 7 files changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 286d36589d..c8146c3509 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -16,6 +16,13 @@ config MX7D select ROM_UNIFIED_SECTIONS imply CMD_FUSE +config SYS_TEXT_BASE + default 0x87800000 + +config SPL_TEXT_BASE + depends on SPL + default 0x00912000 + choice prompt "MX7 board select" optional diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index d2766190de..b54048343f 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -17,7 +16,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 8a1e15de65..07b17f52ec 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 830fddeee9..d04b0d7dd6 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 545acd2c89..f3719187ef 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 8a1e15de65..07b17f52ec 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index c9e6abc7d2..13b6a2f35c 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -15,7 +14,6 @@ CONFIG_SPL=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_TEXT_BASE=0x00911000 CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" -- 2.25.1

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[PATCH] ARM: imx6: Fetch MAC address in board_init_late() on DH iMX6 PDK2
by Marek Vasut 23 Jun '20

23 Jun '20

This is needed to obtain the MAC from EEPROM/OTP only after the final env is populated, otherwise the ethaddr might be overriden. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Claudius Heine <ch(a)denx.de> Cc: Harald Seiler <hws(a)denx.de> Cc: Ludwig Zenz <lzenz(a)dh-electronics.com> Cc: Stefano Babic <sbabic(a)denx.de> --- board/dhelectronics/dh_imx6/dh_imx6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index b6f8b11a10..8735d583bd 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -139,8 +139,6 @@ int board_init(void) /* Enable eim_slow clocks */ setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); - setup_dhcom_mac_from_fuse(); - setup_fec_clock(); return 0; @@ -186,6 +184,8 @@ int board_late_init(void) u32 hw_code; char buf[16]; + setup_dhcom_mac_from_fuse(); + hw_code = board_get_hwcode(); switch (get_cpu_type()) { -- 2.25.1

2 1

[PATCH v2] imx: imx8qm_rom7720_a1: update README
by Oliver Graute 23 Jun '20

23 Jun '20

Update README to extract firmware from scripts Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- board/advantech/imx8qm_rom7720_a1/README | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README index bff5712589..d3e3cec063 100644 --- a/board/advantech/imx8qm_rom7720_a1/README +++ b/board/advantech/imx8qm_rom7720_a1/README @@ -29,6 +29,17 @@ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin $ chmod +x firmware-imx-8.0.bin $ ./firmware-imx-8.0.bin +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 +$ tar -xf imx-sc-firmware-1.1.tar.bz2 +$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir) + +$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 +$ tar -xf firmware-imx-8.0.tar.bz2 +$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + Build U-Boot ============ -- 2.17.1

2 1

[PATCH 0/2] Enable all cache ways and Enable SiFive PWM driver
by Pragnesh Patel 23 Jun '20

23 Jun '20

Patch 1: enable all cache ways from U-Boot proper This patch enables all cache ways from U-Boot proper, earlier this was done by FSBL. (https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/mai…) L2 cache is of 2 MB (16 cache ways) and 1 cache way is of 128 KB. FSBL is located on the latest way of L2 cache. Therefore, FSBL can only enable the first 15 L2 cache ways to avoid corrupt itself. U-Boot proper enables all cache ways (16 cache ways) in this patch. Patch 2: Enable SiFive PWM driver This patch enables SiFive PWM driver for the SiFive Unleashed board. This series is rebase on - [v13] RISC-V SiFive FU540 support SPL This series depends on: [1] https://patchwork.ozlabs.org/patch/1275883 All these together is available for testing here [2] https://github.com/pragnesh26992/u-boot/tree/pwm Pragnesh Patel (2): riscv: sifive: fu540: enable all cache ways from U-Boot proper riscv: sifive: fu540: Enable SiFive PWM driver arch/riscv/cpu/fu540/Makefile | 1 + arch/riscv/cpu/fu540/cache.c | 53 +++++++++++++++++++++++ arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++ arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++ board/sifive/fu540/Kconfig | 2 + board/sifive/fu540/fu540.c | 10 ++++- 6 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/cpu/fu540/cache.c create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h -- 2.17.1

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[PATCH 0/7] Add support for CONFIG_API on RISC-V
by mhorne＠FreeBSD.org 22 Jun '20

22 Jun '20

From: Mitchell Horne <mhorne(a)FreeBSD.org> FreeBSD makes use of u-boot's CONFIG_API to provide a version of its standard bootloader for embedded architectures. This series adds the necessary support for the RISC-V architecture, along with some small fixes to the API demo program for 64-bit systems. Mitchell Horne (7): examples: generate demo.bin examples: rename __start to _start on MIPS examples: add a linker script for the API demo examples: fix the type of search_hint examples: fix incompatible type casts riscv: add CONFIG_API support api: enumerate virtio-blk devices api/Makefile | 1 + api/api_platform-riscv.c | 33 +++++++++++++++++++++++++++++++++ api/api_storage.c | 14 +++++++++++++- examples/api/Makefile | 10 +++++++--- examples/api/crt0.S | 25 +++++++++++++++++++++---- examples/api/demo.c | 21 +++++++++++---------- examples/api/demo.lds | 14 ++++++++++++++ examples/api/glue.c | 6 +++--- examples/api/glue.h | 2 +- include/api_public.h | 1 + 10 files changed, 105 insertions(+), 22 deletions(-) create mode 100644 api/api_platform-riscv.c create mode 100644 examples/api/demo.lds -- 2.26.1

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[RESEND][Patch v4] net: pfe_eth: Use spi_flash_read API to access flash memory
by Kuldeep Singh 22 Jun '20

22 Jun '20

Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- v4: -Rebase to top -Use complete firmware size -Return -ENODEV if flash probe fails v3: -Replace ret with 0 if flash probe fails v2: -Add return error code -Changes in displayed error log drivers/net/pfe_eth/pfe_firmware.c | 45 +++++++++++++++++++++++++++++++++++++- include/configs/ls1012a_common.h | 5 ++++- 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index 0493cfe..55e661c 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -16,13 +16,14 @@ #include <linux/bitops.h> #include <net/pfe_eth/pfe_eth.h> #include <net/pfe_eth/pfe_firmware.h> +#include <spi_flash.h> #ifdef CONFIG_CHAIN_OF_TRUST #include <fsl_validate.h> #endif #define PFE_FIRMWARE_FIT_CNF_NAME "config@1" -static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR; +static const void *pfe_fit_addr; /* * PFE elf firmware loader. @@ -163,6 +164,44 @@ static int pfe_fit_check(void) return ret; } +int pfe_spi_flash_init(void) +{ + struct spi_flash *pfe_flash; + int ret = 0; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + /* speed and mode will be read from DT */ + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, 0, 0, &new); + + pfe_flash = dev_get_uclass_priv(new); +#else + pfe_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE); +#endif + if (!pfe_flash) { + printf("SF: probe for pfe failed\n"); + return -ENODEV; + } + + ret = spi_flash_read(pfe_flash, + CONFIG_SYS_LS_PFE_FW_ADDR, + CONFIG_SYS_QE_FMAN_FW_LENGTH, + addr); + if (ret) + printf("SF: read for pfe failed\n"); + + pfe_fit_addr = addr; + spi_flash_free(pfe_flash); + + return ret; +} + /* * PFE firmware initialization. * Loads different firmware files from FIT image. @@ -187,6 +226,10 @@ int pfe_firmware_init(void) int ret = 0; int fw_count; + ret = pfe_spi_flash_init(); + if (ret) + goto err; + ret = pfe_fit_check(); if (ret) goto err; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 3bea9a9..06af8bf 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -36,8 +36,11 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) -/*SPI device */ +/* PFE */ #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000 + +/*SPI device */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 /* SATA */ -- 2.7.4

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[PATCH 1/3] ram: rk3328: only do data traning for cs0
by Kever Yang 21 Jun '20

21 Jun '20

No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> Signed-off-by: YouMin Chen <cym(a)rock-chips.com> --- drivers/ram/rockchip/sdram_rk3328.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 69521cef69..8329f4a352 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -377,16 +377,12 @@ static int sdram_init(struct dram_info *dram, printf("data training error\n"); return -1; } - if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { - printf("data training error\n"); - return -1; - } if (sdram_params->base.dramtype == DDR4) pctl_write_vrefdq(dram->pctl, 0x3, 5670, sdram_params->base.dramtype); - if (pre_init == 0) { + if (pre_init != 0) { rx_deskew_switch_adjust(dram); tx_deskew_switch_adjust(dram); } @@ -482,7 +478,7 @@ static int sdram_init_detect(struct dram_info *dram, memcpy(&sdram_ch, &sdram_params->ch, sizeof(struct rk3328_sdram_channel)); - sdram_init(dram, sdram_params, 1); + sdram_init(dram, sdram_params, 0); dram_detect_cap(dram, sdram_params, 0); /* modify bw, cs related timing */ @@ -495,7 +491,7 @@ static int sdram_init_detect(struct dram_info *dram, sdram_ch.noc_timings.ddrtiming.b.bwratio = 1; /* reinit sdram by real dram cap */ - sdram_init(dram, sdram_params, 0); + sdram_init(dram, sdram_params, 1); /* redetect cs1 row */ sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); -- 2.17.1

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[PATCH] video: ipuv3: remove some useless code to reduce binary size
by Anatolij Gustschin 19 Jun '20

19 Jun '20

To enable DM_VIDEO we must decrease binary size to fix build breakage for some boards, so drop not needed code. Also add !DM_VIDEO guards which can be later removed when last non DM users will be converted. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- drivers/video/imx/ipu_disp.c | 12 ------- drivers/video/imx/mxc_ipuv3_fb.c | 57 ++++++++++++-------------------- 2 files changed, 22 insertions(+), 47 deletions(-) diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c index c2f00bff18..45069897fa 100644 --- a/drivers/video/imx/ipu_disp.c +++ b/drivers/video/imx/ipu_disp.c @@ -1191,9 +1191,6 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, else bg_chan = 0; - if (!g_ipu_clk_enabled) - clk_enable(g_ipu_clk); - if (bg_chan) { reg = __raw_readl(DP_COM_CONF()); __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF()); @@ -1217,9 +1214,6 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, reg = __raw_readl(IPU_SRM_PRI2) | 0x8; __raw_writel(reg, IPU_SRM_PRI2); - if (!g_ipu_clk_enabled) - clk_disable(g_ipu_clk); - return 0; } @@ -1246,9 +1240,6 @@ int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) return -EINVAL; - if (!g_ipu_clk_enabled) - clk_enable(g_ipu_clk); - color_key_4rgb = 1; /* Transform color key from rgb to yuv if CSC is enabled */ if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || @@ -1286,8 +1277,5 @@ int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, reg = __raw_readl(IPU_SRM_PRI2) | 0x8; __raw_writel(reg, IPU_SRM_PRI2); - if (!g_ipu_clk_enabled) - clk_disable(g_ipu_clk); - return 0; } diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 4044473f99..2a0a355817 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -38,8 +38,10 @@ DECLARE_GLOBAL_DATA_PTR; static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); +#if !CONFIG_IS_ENABLED(DM_VIDEO) /* graphics setup */ static GraphicDevice panel; +#endif static struct fb_videomode const *gmode; static uint8_t gdisp; static uint32_t gpixfmt; @@ -120,27 +122,6 @@ static uint32_t bpp_to_pixfmt(struct fb_info *fbi) return pixfmt; } -/* - * Set fixed framebuffer parameters based on variable settings. - * - * @param info framebuffer information pointer - */ -static int mxcfb_set_fix(struct fb_info *info) -{ - struct fb_fix_screeninfo *fix = &info->fix; - struct fb_var_screeninfo *var = &info->var; - - fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; - - fix->type = FB_TYPE_PACKED_PIXELS; - fix->accel = FB_ACCEL_NONE; - fix->visual = FB_VISUAL_TRUECOLOR; - fix->xpanstep = 1; - fix->ypanstep = 1; - - return 0; -} - static int setup_disp_channel1(struct fb_info *fbi) { ipu_channel_params_t params; @@ -226,7 +207,6 @@ static int mxcfb_set_par(struct fb_info *fbi) ipu_disable_channel(mxc_fbi->ipu_ch); ipu_uninit_channel(mxc_fbi->ipu_ch); - mxcfb_set_fix(fbi); mem_len = fbi->var.yres_virtual * fbi->fix.line_length; if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) { @@ -499,6 +479,8 @@ static struct fb_info *mxcfb_init_fbinfo(void) return fbi; } +extern struct clk *g_ipu_clk; + /* * Probe routine for the framebuffer driver. It is called during the * driver binding process. The following functions are performed in @@ -512,16 +494,14 @@ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, { struct fb_info *fbi; struct mxcfb_info *mxcfbi; - int ret = 0; /* * Initialize FB structures */ fbi = mxcfb_init_fbinfo(); - if (!fbi) { - ret = -ENOMEM; - goto err0; - } + if (!fbi) + return -ENOMEM; + mxcfbi = (struct mxcfb_info *)fbi->par; if (!g_dp_in_use) { @@ -534,9 +514,11 @@ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, mxcfbi->ipu_di = disp; + if (!ipu_clk_enabled()) + clk_enable(g_ipu_clk); + ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80); ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0); - strcpy(fbi->fix.id, "DISP3 BG"); g_dp_in_use = 1; @@ -547,7 +529,8 @@ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, mxcfbi->ipu_di_pix_fmt = interface_pix_fmt; fb_videomode_to_var(&fbi->var, mode); fbi->var.bits_per_pixel = 16; - fbi->fix.line_length = fbi->var.xres * (fbi->var.bits_per_pixel / 8); + fbi->fix.line_length = fbi->var.xres_virtual * + (fbi->var.bits_per_pixel / 8); fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length; mxcfb_check_var(&fbi->var, fbi); @@ -555,14 +538,13 @@ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, /* Default Y virtual size is 2x panel size */ fbi->var.yres_virtual = fbi->var.yres * 2; - mxcfb_set_fix(fbi); - /* allocate fb first */ if (mxcfb_map_video_memory(fbi) < 0) return -ENOMEM; mxcfb_set_par(fbi); +#if !CONFIG_IS_ENABLED(DM_VIDEO) panel.winSizeX = mode->xres; panel.winSizeY = mode->yres; panel.plnSizeX = mode->xres; @@ -573,13 +555,12 @@ static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, panel.gdfBytesPP = 2; panel.gdfIndex = GDF_16BIT_565RGB; - +#endif +#ifdef DEBUG ipu_dump_registers(); +#endif return 0; - -err0: - return ret; } void ipuv3_fb_shutdown(void) @@ -604,6 +585,7 @@ void ipuv3_fb_shutdown(void) } } +#if !CONFIG_IS_ENABLED(DM_VIDEO) void *video_hw_init(void) { int ret; @@ -618,6 +600,7 @@ void *video_hw_init(void) return (void *)&panel; } +#endif int ipuv3_fb_init(struct fb_videomode const *mode, uint8_t disp, @@ -707,8 +690,12 @@ static int ipuv3_video_bind(struct udevice *dev) } static const struct udevice_id ipuv3_video_ids[] = { +#ifdef CONFIG_ARCH_MX6 { .compatible = "fsl,imx6q-ipu" }, +#endif +#ifdef CONFIG_ARCH_MX5 { .compatible = "fsl,imx53-ipu" }, +#endif { } }; -- 2.17.1

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