April 2020 - U-Boot

[PATCH v2] riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
by Pragnesh Patel 18 Apr '20

18 Apr '20

CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot, SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED() Signed-off-by: Pragnesh Patel <pragnesh.patel(a)sifive.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/riscv/cpu/ax25/cache.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 9f424198b4..9df629d23c 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -12,7 +12,7 @@ #include <asm/csr.h> #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) /* mcctlcommand */ #define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc @@ -47,7 +47,7 @@ void flush_dcache_all(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); #endif #endif @@ -68,7 +68,7 @@ void icache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x1\n\t" @@ -83,7 +83,7 @@ void icache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "fence.i\n\t" "csrr t1, mcache_ctl\n\t" @@ -99,7 +99,7 @@ void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" @@ -117,7 +117,7 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -137,7 +137,7 @@ int icache_status(void) int ret = 0; #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x01\n\t" @@ -156,7 +156,7 @@ int dcache_status(void) int ret = 0; #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x02\n\t" -- 2.17.1

1 1

[U-Boot] [PATCH v2 0/5] riscv: sifive/fu540: Enable SPI-NOR support
by Jagan Teki 18 Apr '20

18 Apr '20

This is v2 patchset, enable SPI-NOR flash on SiFive hifive-unleashed-a00 board, here is v1 [1]. Changes for v2: - use latest sifive commit from linux-next - fix typos in commit message - rebased on master patch 0001 - 02: support devicetree patch 0003: add is25wp256 chip patch 0004 - 05: enable spi-nor flash All tested in Sifive fuse540 hifive-unleashed-a00 board. [1] https://patchwork.ozlabs.org/cover/1168959/ Any inputs? Jagan. Jagan Teki (5): riscv: dts: Add hifive-unleashed-a00 dts from Linux sifive: fu540: Enable OF_SEPARATE mtd: spi-nor: ids: Add is25wp256 chip riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi sifive: fu540: Enable spi-nor flash support arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu540-c000.dtsi | 251 ++++++++++++++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 11 + arch/riscv/dts/hifive-unleashed-a00.dts | 96 +++++++ board/sifive/fu540/Kconfig | 3 + configs/sifive_fu540_defconfig | 3 +- doc/board/sifive/fu540.rst | 21 +- drivers/mtd/spi/spi-nor-ids.c | 2 + 8 files changed, 386 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts -- 2.18.0.321.gffc6fa0e3

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[PATCH v2 00/13] bugfix/improvements for IMX-based modules
by Igor Opaniuk 18 Apr '20

18 Apr '20

1. Enable relocation of fdt and initrd for all Toradex modules; 2. Add nfsboot wrapper to env for Verdin i.MX8M Mini 3. i.MX8M Mini EVK/Verdin: adjust dram size in case bl32 is used 4. Set gpr1 ENET_CLK_SEL for Colibri iMX6S/DL, which fixes PHY negotiation issues. 5. Colibri i.MX8QXP/QM pd_dma nodes should be accessible before U-Boot relocation. v2: - Applied R-b tags - Put all pending patches into one patch-series to easier track stuff Igor Opaniuk (13): ARM: dts: imx8qm-apalis: replace dm-spl with dm-pre-proper ARM: dts: imx8qxp-colibri: replace dm-spl with dm-pre-proper ARM: dts: imx8qm-apalis: dm-pre-proper for pd_dma nodes ARM: dts: imx8qxp-colibri: dm-pre-proper for pd_dma nodes colibri_imx6: set gpr1 ENET_CLK_SEL verdin-imx8mm: adjust dram size in case bl32 is used imx8mm_evk: adjust dram size in case bl32 is used verdin-imx8mm: add nfsboot wrapper to env colibri_vf: enable relocation of fdt and initrd colibri_imx7: enable relocation of fdt and initrd apalis_imx6: enable relocation of fdt and initrd colibri-imx6ull: enable relocation of fdt and initrd colibri_imx6: enable relocation of fdt and initrd arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 70 +++++++++++--------- arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 68 +++++++++++-------- board/freescale/imx8mm_evk/imx8mm_evk.c | 6 +- board/toradex/colibri_imx6/colibri_imx6.c | 3 + board/toradex/verdin-imx8mm/verdin-imx8mm.c | 7 +- include/configs/apalis_imx6.h | 2 - include/configs/colibri-imx6ull.h | 2 - include/configs/colibri_imx6.h | 2 - include/configs/colibri_imx7.h | 2 - include/configs/colibri_vf.h | 2 - include/configs/verdin-imx8mm.h | 6 ++ 11 files changed, 99 insertions(+), 71 deletions(-) -- 2.17.1

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[PATCH] imx8qxp_mek: Start with USDHC2 unpowered
by Fabio Estevam 18 Apr '20

18 Apr '20

After triggering a "reboot" command in Linux the following hang in SPL is observed: U-Boot SPL 2020.04 (Apr 15 2020 - 10:49:29 -0300) Normal Boot WDT: Not found! Trying to boot from MMC2_2 spl: mmc init failed with error: -70 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### This error happens because the CMD_ERR bit is set in the IRQ status register after booting from Linux. To ensure a fresh start, force the VMMC supply to get unpowered first. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- board/freescale/imx8qxp_mek/spl.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index cb4006eb2a..e4e4cbe716 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -12,9 +12,24 @@ #include <dm/uclass-internal.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> DECLARE_GLOBAL_DATA_PTR; +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19) +static iomux_cfg_t usdhc2_sd_pwr[] = { + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + void spl_board_init(void) { struct udevice *dev; @@ -32,6 +47,9 @@ void spl_board_init(void) timer_init(); + imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr)); + gpio_direction_output(USDHC2_SD_PWR, 0); + preloader_console_init(); puts("Normal Boot\n"); -- 2.17.1

3 2

[PATCH v2 1/2] mx7ulp: Remove duplicated definitions
by Fabio Estevam 18 Apr '20

18 Apr '20

These PMC0 definitions are already defined in the beginning of the file, so remove the duplication. Reported-by: Stefano Babic <sbabic(a)denx.de> Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- Changes since v1: - Newly introduced in this version. arch/arm/mach-imx/mx7ulp/soc.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 46484813d2..d8d691692c 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -193,10 +193,6 @@ const char *get_imx_type(u32 imxtype) return "7ULP"; } -#define PMC0_BASE_ADDR 0x410a1000 -#define PMC0_CTRL 0x28 -#define PMC0_CTRL_LDOEN BIT(31) - static bool ldo_mode_is_enabled(void) { unsigned int reg; -- 2.17.1

3 6

[PATCH 0/7] TQMa6x: upgrade board support to device model
by Michael Krummsdorf 18 Apr '20

18 Apr '20

This series provides the device trees and required configuration settings to advance board support to device model. The first step is to successfully compile and boot again while having access to essential interfaces (i.e. e-MMC, SD card, Ethernet, SPI NOR flash, USB Host). More features and interface support will be added with a future patch set. Markus Niebel (1): tqma6: resurrect support by supplying correct SYS_TEXT_BASE Michael Krummsdorf (6): arm: dt: imx6qdl: add tqma6[qdl] som on mba6 mainboard arch: arm: tqma6: apply default Kconfig for device model board: tqc: tqma6: mba6: apply default Kconfig for device model configs: tqma6x_mba6x: update default configs for device model board: tqc: tqma6: hw init code disabled for device model board: tqc: tqma6_mba6: switch to device model arch/arm/dts/Makefile | 4 + arch/arm/dts/imx6dl-mba6.dtsi | 18 +++ arch/arm/dts/imx6dl-mba6a.dts | 16 +++ arch/arm/dts/imx6dl-mba6b.dts | 16 +++ arch/arm/dts/imx6dl-tqma6a.dtsi | 14 ++ arch/arm/dts/imx6dl-tqma6b.dtsi | 14 ++ arch/arm/dts/imx6q-mba6.dtsi | 18 +++ arch/arm/dts/imx6q-mba6a.dts | 16 +++ arch/arm/dts/imx6q-mba6b.dts | 16 +++ arch/arm/dts/imx6q-tqma6a.dtsi | 14 ++ arch/arm/dts/imx6q-tqma6b.dtsi | 14 ++ arch/arm/dts/imx6qdl-mba6.dtsi | 207 ++++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-mba6a.dtsi | 39 ++++++ arch/arm/dts/imx6qdl-mba6b.dtsi | 45 ++++++ arch/arm/dts/imx6qdl-tqma6.dtsi | 211 +++++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-tqma6a.dtsi | 27 ++++ arch/arm/dts/imx6qdl-tqma6b.dtsi | 27 ++++ arch/arm/mach-imx/mx6/Kconfig | 11 ++ board/tqc/tqma6/Kconfig | 15 ++ board/tqc/tqma6/tqma6.c | 12 ++ board/tqc/tqma6/tqma6_mba6.c | 171 +---------------------- configs/tqma6dl_mba6_mmc_defconfig | 31 +++-- configs/tqma6dl_mba6_spi_defconfig | 31 +++-- configs/tqma6q_mba6_mmc_defconfig | 31 +++-- configs/tqma6q_mba6_spi_defconfig | 31 +++-- configs/tqma6s_mba6_mmc_defconfig | 31 +++-- configs/tqma6s_mba6_spi_defconfig | 31 +++-- configs/tqma6s_wru4_mmc_defconfig | 9 +- include/configs/tqma6.h | 9 +- include/configs/tqma6_wru4.h | 3 + 30 files changed, 867 insertions(+), 265 deletions(-) create mode 100644 arch/arm/dts/imx6dl-mba6.dtsi create mode 100644 arch/arm/dts/imx6dl-mba6a.dts create mode 100644 arch/arm/dts/imx6dl-mba6b.dts create mode 100644 arch/arm/dts/imx6dl-tqma6a.dtsi create mode 100644 arch/arm/dts/imx6dl-tqma6b.dtsi create mode 100644 arch/arm/dts/imx6q-mba6.dtsi create mode 100644 arch/arm/dts/imx6q-mba6a.dts create mode 100644 arch/arm/dts/imx6q-mba6b.dts create mode 100644 arch/arm/dts/imx6q-tqma6a.dtsi create mode 100644 arch/arm/dts/imx6q-tqma6b.dtsi create mode 100644 arch/arm/dts/imx6qdl-mba6.dtsi create mode 100644 arch/arm/dts/imx6qdl-mba6a.dtsi create mode 100644 arch/arm/dts/imx6qdl-mba6b.dtsi create mode 100644 arch/arm/dts/imx6qdl-tqma6.dtsi create mode 100644 arch/arm/dts/imx6qdl-tqma6a.dtsi create mode 100644 arch/arm/dts/imx6qdl-tqma6b.dtsi -- 2.17.1

2 14

[PATCH] mx6ulz_14x14_evk: Disable CONFIG_NET
by Fabio Estevam 18 Apr '20

18 Apr '20

Currently the following build warning is seen: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. =================================================== Since the mx6ulz-evk board does not have networking support, explicitly disable networking to avoid the board removal. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- configs/mx6ulz_14x14_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index b854c36c77..92d73a85c8 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -29,6 +29,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -- 2.17.1

2 1

[PATCH 1/2] mx6ul_evk: Move CONFIG_FEC_MXC to defconfig
by Fabio Estevam 18 Apr '20

18 Apr '20

CONFIG_FEC_MXC is supported in Kconfig, so it is preferred to move it to defconfig file. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- configs/mx6ul_14x14_evk_defconfig | 1 + include/configs/mx6ul_14x14_evk.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 4fd311d2fb..f72f050561 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_FEC_MXC=y CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 5cc15b6d2f..a35077ddb8 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -177,7 +177,6 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC #define CONFIG_FEC_ENET_DEV 1 #if (CONFIG_FEC_ENET_DEV == 0) -- 2.17.1

3 5

[PATCH] mx6ullevk: Enable Ethernet support
by Fabio Estevam 18 Apr '20

18 Apr '20

Add Ethernet support using DM_ETH. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- board/freescale/mx6ullevk/mx6ullevk.c | 47 +++++++++++++++++++++++++++ configs/mx6ull_14x14_evk_defconfig | 8 +++++ include/configs/mx6ullevk.h | 9 +++++ 3 files changed, 64 insertions(+) diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index e1eddbff95..3f1ecce10f 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -19,6 +19,7 @@ #include <fsl_esdhc_imx.h> #include <linux/sizes.h> #include <mmc.h> +#include <miiphy.h> DECLARE_GLOBAL_DATA_PTR; @@ -60,11 +61,57 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_FEC_MXC +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50MHz anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50MHz anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + return 0; } diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 2c69d8d6de..c16ecfab49 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -38,9 +38,17 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_FEC_MXC=y +CONFIG_DM_ETH=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 7cce911314..af335bcfff 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -166,4 +166,13 @@ #define FSL_QSPI_FLASH_SIZE SZ_32M #endif +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_ENET_DEV 1 +#if (CONFIG_FEC_ENET_DEV == 0) +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define CONFIG_ETHPRIME "eth1" +#endif +#endif + #endif -- 2.17.1

3 2

[PATCH v3] arm: imx6: configure NoC on i.MX6DQP
by Bernhard Messerklinger 18 Apr '20

18 Apr '20

The i.MX6DP and i.MX6QP incorporate NoC interconnect logic which needs to be configured in order to use external DDR memory. This patch enables the SPL to configure the necessary registers in accordance with the NXP engineering bulletin EB828. Co-developed-by: Filip Brozović <fbrozovic(a)gmail.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger(a)br-automation.com> --- This patch is a revised version of the patch "arm: imx6: configure NoC on i.MX6DQP" from the original author Filip Brozovic <fbrozovic(a)gmail.com>. It takes care of the review notes for the original patch. patchwork: https://patchwork.ozlabs.org/patch/670208/ mail-archive: https://lists.denx.de/pipermail/u-boot/2016-September/266667.html @Filip: I added the Co-Developed-by: tag, can you please reply with your Signed-off-by. @Maintainers: Can you please provide some feedback regarding this patch and the way I want to handle the authorship? Changes in v3: - Add Co-Developed-by tag for Filip Brozović Changes in v2: - Added missing link to lkml discussion arch/arm/include/asm/arch-mx6/mx6-ddr.h | 19 +++++ arch/arm/mach-imx/mx6/ddr.c | 96 +++++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 19d2f1d9c5..25168c9865 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -307,6 +307,25 @@ struct mx6dq_iomux_grp_regs { u32 grp_b6ds; }; +/* + * NoC scheduler registers - only on IMX6DQP + */ +#define MX6DQP_NOC_SCHED_BASE 0x00bb0000 +struct mx6dqp_noc_sched_regs { + u32 coreid; + u32 revid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 rlat; + u32 res1[4]; + u32 ipu1; + u32 ipu2; + u32 res2[2]; + u32 activate; + u32 res3[16]; +}; + #define MX6SDL_IOM_DDR_BASE 0x020e0400 struct mx6sdl_iomux_ddr_regs { u32 res1[25]; diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 6e5e40dd1a..3521d8eac7 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -936,6 +936,27 @@ void mx6sdl_dram_iocfg(unsigned width, mmdc1->entry = value; \ } while (0) +/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */ +#define BOOT_CFG3_DDR_MASK 0x30 +#define BOOT_CFG3_EXT_DDR_MASK 0x33 + +#define DDR_MMAP_NOC_SINGLE 0 +#define DDR_MMAP_NOC_DUAL 0x31 + +/* NoC ACTIVATE shifts */ +#define NOC_RD_SHIFT 0 +#define NOC_FAW_PERIOD_SHIFT 4 +#define NOC_FAW_BANKS_SHIFT 10 + +/* NoC DdrTiming shifts */ +#define NOC_ACT_TO_ACT_SHIFT 0 +#define NOC_RD_TO_MISS_SHIFT 6 +#define NOC_WR_TO_MISS_SHIFT 12 +#define NOC_BURST_LEN_SHIFT 18 +#define NOC_RD_TO_WR_SHIFT 21 +#define NOC_WR_TO_RD_SHIFT 26 +#define NOC_BW_RATIO_SHIFT 31 + /* * According JESD209-2B-LPDDR2: Table 103 * WL: write latency @@ -1225,6 +1246,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, { volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff; u32 val; u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; @@ -1517,6 +1540,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* Step 12: Configure and activate periodic refresh */ mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); + /* + * Step 13: i.MX6DQP only: If the NoC scheduler is enabled, + * configure it and disable MMDC arbitration/reordering (see EB828) + */ + if (is_mx6dqp() && + ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE || + (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) { + struct mx6dqp_noc_sched_regs *noc_sched = + (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE; + + /* + * These values are fixed based on integration parameters and + * should not be modified + */ + noc_sched->rlat = 0x00000040; + noc_sched->ipu1 = 0x00000020; + noc_sched->ipu2 = 0x00000020; + + noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) | + (tfaw << NOC_FAW_PERIOD_SHIFT) | + (trrd << NOC_RD_SHIFT); + noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0) + << NOC_BW_RATIO_SHIFT) | + ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) | + ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) | + (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */ + ((tcwl + twr + trp + trcd) + << NOC_WR_TO_MISS_SHIFT) | + ((trtp + trp + trcd - 4) + << NOC_RD_TO_MISS_SHIFT) | + (trc << NOC_ACT_TO_ACT_SHIFT); + + if (sysinfo->dsize == 2) { + if (ddr3_cfg->coladdr == 10) { + if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 4; + else + noc_sched->ddrconf = 0; + } else if (ddr3_cfg->coladdr == 11) { + noc_sched->ddrconf = 1; + } + } else { + if (ddr3_cfg->coladdr == 9) { + if (ddr3_cfg->rowaddr == 13) + noc_sched->ddrconf = 2; + else if (ddr3_cfg->rowaddr == 14) + noc_sched->ddrconf = 15; + } else if (ddr3_cfg->coladdr == 10) { + if (ddr3_cfg->rowaddr == 14 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 14; + else if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 9; + else + noc_sched->ddrconf = 3; + } else if (ddr3_cfg->coladdr == 11) { + if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 4; + else + noc_sched->ddrconf = 0; + } else if (ddr3_cfg->coladdr == 12) { + if (ddr3_cfg->rowaddr == 14) + noc_sched->ddrconf = 1; + } + } + + /* Disable MMDC arbitration/reordering */ + mmdc0->maarcr = 0x14420000; + } + /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; -- 2.25.1

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