April 2020 - U-Boot

[PATCH] lx2160a : Update environment variable.
by Meenakshi Aggarwal 27 Apr '20

27 Apr '20

Update environment variable for emmc boot. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> --- include/configs/lx2160a_common.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1907f93..6c3e647 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -225,6 +225,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "esbc_validate 0x80680000 ;" \ "fsl_mc start mc 0x80a00000 0x80e00000\0" +#define SD2_MC_INIT_CMD \ + "mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80640000 0x3200 0x20 && " \ + "mmc read 0x80680000 0x3400 0x20 && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000 ;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" + #define EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ @@ -292,11 +302,11 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "env exists secureboot && esbc_halt;" #define SD2_BOOTCOMMAND \ - "env exists mcinitcmd && mmcinfo; " \ + "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80d00000 0x6800 0x800; " \ "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x20 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + " && mmc read 0x806C0000 0x3600 0x20 " \ + "&& esbc_validate 0x806C0000;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80d00000;" \ "run distro_bootcmd;run emmc_bootcmd;" \ "env exists secureboot && esbc_halt;" -- 1.9.1

2 4

[PATCH 1/3] mips: mt76x8: ddr_cal: Rename dqs_test_valid() to dqs_test_error()
by Stefan Roese 27 Apr '20

27 Apr '20

This function returns "-1" (true) upon error. So the function name does not match its implementation which is confusing. This patch renames the function to dqs_test_error() which makes the code easier to read. Also change the return type to bool and return "true" or "false". Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Weijie Gao <weijie.gao(a)mediatek.com> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/mach-mtmips/ddr_cal.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c index 0ea7c7d5e1..b934c4a854 100644 --- a/arch/mips/mach-mtmips/ddr_cal.c +++ b/arch/mips/mach-mtmips/ddr_cal.c @@ -32,8 +32,8 @@ static inline void pref_op(int op, const volatile void *addr) __asm__ __volatile__("pref %0, 0(%1)" : : "i" (op), "r" (addr)); } -static inline int dqs_test_valid(void __iomem *memc, u32 memsize, u32 dqsval, - u32 bias) +static inline bool dqs_test_error(void __iomem *memc, u32 memsize, u32 dqsval, + u32 bias) { u32 *nca, *ca; u32 off; @@ -64,11 +64,11 @@ static inline int dqs_test_valid(void __iomem *memc, u32 memsize, u32 dqsval, for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++) { if (ca[i] != (u32)nca + i + bias) - return -1; + return true; } } - return 0; + return false; } static inline u32 dqs_find_max(void __iomem *memc, u32 memsize, u32 initval, @@ -79,7 +79,7 @@ static inline u32 dqs_find_max(void __iomem *memc, u32 memsize, u32 initval, do { dqsval = regval | (fieldval << shift); - if (dqs_test_valid(memc, memsize, dqsval, 3)) + if (dqs_test_error(memc, memsize, dqsval, 3)) break; fieldval++; @@ -96,7 +96,7 @@ static inline u32 dqs_find_min(void __iomem *memc, u32 memsize, u32 initval, while (fieldval > minval) { dqsval = regval | (fieldval << shift); - if (dqs_test_valid(memc, memsize, dqsval, 1)) { + if (dqs_test_error(memc, memsize, dqsval, 1)) { fieldval++; break; } -- 2.25.1

3 7

[RESEND PATCH v6 0/5] usb: host: dwc2: use driver model for PHY and CLOCK
by Patrick Delaunay 27 Apr '20

27 Apr '20

RESEND of V6, rebased on master http://patchwork.ozlabs.org/project/uboot/list/?series=163388 In this serie I update the DWC2 host driver to use the device tree information and the associated PHY and CLOCK drivers when they are availables. V6 is minor update of the first patch of the serie; I update some clk stub to return success after Simon Goldschmidt remarks on V5: http://patchwork.ozlabs.org/project/uboot/list/?series=162791 Benjamino also use this V6 serie to enable USB host for Odroid-C2. I test the V4 of this serie on stm32mp157c-ev1 board, with PHY and CLK support (V5 was a minor update). The U-CLASS are provided by: - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c - RESET by RCC reset driver = drivers/reset/stm32-reset.c And I activate the configuration +CONFIG_USB_DWC2=y PS: it is not the default configuration to avoid conflict with gadget driver To solve a binding issue, I also deactivate the gadget support: by default only one driver is bound to the usbotg_hs node with "snps,dwc2" compatible, and today it is the device one (the first in the driver list). WARNING: OTG with device or host support is not correctly handle by DWC2 driver (see example for dynamic OTG role in DWC3 driver). The tests executed on the stm32mp157c-ev1 target: STM32MP> usb start starting USB... Bus usb-otg@49000000: USB DWC2 Bus usbh-ehci@5800d000: USB EHCI 1.00 scanning bus usb-otg@49000000 for devices... 2 USB Device(s) found scanning bus usbh-ehci@5800d000 for devices... 3 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found STM32MP> usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 300mA) Verbatim STORE N GO 070731C8ACD7EE97 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 2mA) STM32MP> ls usb 0 <DIR> 4096 . <DIR> 4096 .. <DIR> 16384 lost+found <DIR> 4096 record 1490212 xipImage 21058006 vmlinux STM32MP> load usb 0 0xC0000000 vmlinux 21058006 bytes read in 10851 ms (1.9 MiB/s) Changes in v6: - return success in stub for clk_free/clk_enable/clk_disable/ clk_enable_bulk/clk_disable_bulk Changes in v5: - use ERR_PTR in clk_get_parent() - force bulk->count = 0 in clk_get_bulk to avoid issue for next call of clk_enable_bulk / clk_enable_bulk - update commit message - inverse logic for -ENOENT test on generic_phy_get_by_index result - Add some comments Changes in v4: - Add stub for all functions using 'struct clk' or 'struct clk_bulk' after remarks on v3 Changes in v3: - Add stub for clk_disable_bulk Changes in v2: - update dev_err - update commit message - change dev_err to dev_dbg for PHY function call - treat dwc2_shutdown_phy error - add clk_disable_bulk in dwc2_usb_remove Patrick Delaunay (5): dm: clk: add stub when CONFIG_CLK is deactivated usb: host: dwc2: add phy support usb: host: dwc2: add clk support usb: host: dwc2: force reset assert usb: host: dwc2: add trace to have clean usb start drivers/usb/host/dwc2.c | 100 ++++++++++++++++++++++++++++++++++++++- include/clk.h | 102 +++++++++++++++++++++++++++++++++++----- 2 files changed, 188 insertions(+), 14 deletions(-) -- 2.17.1

2 6

[PATCH v6] Add support for SoM "VoCore2".
by Mauro Condarelli 27 Apr '20

27 Apr '20

Small patch to add support for VoCore/VoCore2 board. VoCore is open hardware and runs OpenWrt/LEDE. It has WIFI, USB, UART, 20+ GPIOs but is only one inch square. It will help you to make a smart house, study embedded system or even make the tiniest router in the world. Details about this SoM can be found at "https://vocore.io/v2.html". Signed-off-by: Mauro Condarelli <mc5686(a)mclink.it> --- Changes in v6: - Added MAINTAINERS file. - Removed project-specific configs/vocore2_defconfig_ENV_IN_FAT. - Removed guard for SPL Serial definitions in include/configs/vocore2.h. - Removed Baudrate Table definition in include/configs/vocore2.h. - Moved board-specific DTS settingsto arch/mips/dts/vocore_vocore2.dts. - Added UART2 pin definitions to arch/mips/dts/vocore_vocore2.dts. - Removed unused mmc pin definition from arch/mips/dts/vocore_vocore2.dts. - Added select of SPL_UART2_SPIS_PINMUX in board choice. - Updated configs/vocore2_defconfig. Changes in v5: - Removed unneeded (and wrong) UART2 initialization in board.c - Added network setup. - Removed project-specific code. - Move back environment to SPI NOR. - Changes to environment default settings. - Rebase on current u-boot-mips/testing. Changes in v4: - Reverted some overzealous DTS cleaning. - Added support for bootcount. Changes in v3: - based on top of Weijie Gao patchset: "[v3,xx/20]Refactor the architecture parts of mt7628" Changes in v2: - Removed some dead code - Changed Author to my full name (no nick) - Removed unwanted fixup to .dts generation (not my call). - Fixed commit message - Fixed various variables/filenames to include Vendor name - Changed Vendor name (Vonger -> Vocore) arch/mips/dts/Makefile | 1 + arch/mips/dts/vocore_vocore2.dts | 85 ++++++++++++++++++++++++++ arch/mips/mach-mtmips/Kconfig | 10 +++ board/vocore/vocore2/Kconfig | 12 ++++ board/vocore/vocore2/MAINTAINERS | 7 +++ board/vocore/vocore2/Makefile | 3 + board/vocore/vocore2/board.c | 6 ++ configs/vocore2_defconfig | 101 +++++++++++++++++++++++++++++++ include/configs/vocore2.h | 54 +++++++++++++++++ 9 files changed, 279 insertions(+) create mode 100644 arch/mips/dts/vocore_vocore2.dts create mode 100644 board/vocore/vocore2/Kconfig create mode 100644 board/vocore/vocore2/MAINTAINERS create mode 100644 board/vocore/vocore2/Makefile create mode 100644 board/vocore/vocore2/board.c create mode 100644 configs/vocore2_defconfig create mode 100644 include/configs/vocore2.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index cbd0c8bc8b..f711e9fb59 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -23,6 +23,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f(a)st1704.dtb dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +dtb-$(CONFIG_BOARD_VOCORE2) += vocore_vocore2.dtb dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts new file mode 100644 index 0000000000..3502e4b8b7 --- /dev/null +++ b/arch/mips/dts/vocore_vocore2.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Mauro Condarelli <mc5686(a)mclink.it> + */ + +/dts-v1/; + +#include "mt7628a.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "vocore,vocore2", "ralink,mt7628a-soc"; + model = "VoCore2"; + + aliases { + serial0 = &uart2; + spi0 = &spi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; + leds { + compatible = "gpio-leds"; + + power { + label = "vocore:power"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + chosen { + bootargs = "console=ttyS2,115200"; + stdout-path = &uart2; + }; +}; + +&pinctrl { + state_default: pin_state { + p0led { + groups = "p0led_a"; + function = "led"; + }; + }; +}; + +&uart2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pwm_pins>; +}; + +&spi0 { + status = "okay"; + nor0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&eth { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&ephy_iot_mode>; + mediatek,poll-link-phy = <0>; +}; + +&mmc { + status = "okay"; + + bus-width = <4>; + max-frequency = <48000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_iot_mode>; +}; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index bcd635f438..6ca3b3aad3 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -83,6 +83,15 @@ config BOARD_MT7628_RFB SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host, 1 SDXC, 1 PCIe socket and JTAG pins. +config BOARD_VOCORE2 + bool "VoCore2" + depends on SOC_MT7628 + select SPL_SERIAL_SUPPORT + select SPL_UART2_SPIS_PINMUX + help + VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM + and 16 MiB of flash (SPI). + endchoice config SPL_UART2_SPIS_PINMUX @@ -96,5 +105,6 @@ config SPL_UART2_SPIS_PINMUX source "board/gardena/smart-gateway-mt7688/Kconfig" source "board/mediatek/mt7628/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" +source "board/vocore/vocore2/Kconfig" endmenu diff --git a/board/vocore/vocore2/Kconfig b/board/vocore/vocore2/Kconfig new file mode 100644 index 0000000000..baeff31b69 --- /dev/null +++ b/board/vocore/vocore2/Kconfig @@ -0,0 +1,12 @@ +if BOARD_VOCORE2 + +config SYS_BOARD + default "vocore2" + +config SYS_VENDOR + default "vocore" + +config SYS_CONFIG_NAME + default "vocore2" + +endif diff --git a/board/vocore/vocore2/MAINTAINERS b/board/vocore/vocore2/MAINTAINERS new file mode 100644 index 0000000000..8472351fe2 --- /dev/null +++ b/board/vocore/vocore2/MAINTAINERS @@ -0,0 +1,7 @@ +VOCORE_VOCORE2 BOARD +M: Mauro Condarelli <mc5686(a)mclink.it> +S: Maintained +F: board/vocore/vocore2 +F: include/configs/vocore2.h +F: configs/vocore2_defconfig +F: arch/mips/dts/vocore_vocore2.dts diff --git a/board/vocore/vocore2/Makefile b/board/vocore/vocore2/Makefile new file mode 100644 index 0000000000..70cd7a8e56 --- /dev/null +++ b/board/vocore/vocore2/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o diff --git a/board/vocore/vocore2/board.c b/board/vocore/vocore2/board.c new file mode 100644 index 0000000000..27e42d1414 --- /dev/null +++ b/board/vocore/vocore2/board.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Mauro Condarelli <mc5686(a)mclink.it> + * + * Nothing actually needed here + */ diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig new file mode 100644 index 0000000000..952d9d42de --- /dev/null +++ b/configs/vocore2_defconfig @@ -0,0 +1,101 @@ +CONFIG_MIPS=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x04e000 +CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c +CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_ARCH_MTMIPS=y +CONFIG_BOARD_VOCORE2=y +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_BOOT_GET_KBD=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_LOGLEVEL=8 +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_LICENSE=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDPARTS_DEFAULT="spi0.0:312k(u-boot),4k(env),4k(factory),2368k(kernel),-(filesystem)" +CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MT7628_ETH=y +CONFIG_PHY=y +CONFIG_MT76X8_USB_PHY=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=3 +CONFIG_SPI=y +CONFIG_MT7621_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +CONFIG_FS_EXT4=y +CONFIG_FAT_WRITE=y +CONFIG_LZMA=y +CONFIG_LZO=y diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h new file mode 100644 index 0000000000..8100e4dca7 --- /dev/null +++ b/include/configs/vocore2.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Mauro Condarelli <mc5686(a)mclink.it> + */ + +#ifndef __VOCORE2_CONFIG_H__ +#define __VOCORE2_CONFIG_H__ + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* SPL */ +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SPL_BSS_START_ADDR 0x80010000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#define CONFIG_SPL_MAX_SIZE 0x10000 + +/* Dummy value */ +#define CONFIG_SYS_UBOOT_BASE 0 + +/* Serial SPL */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CONFIG_CONS_INDEX 3 + +/* RAM */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 + +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_CBSIZE 512 + +/* U-Boot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +/* Environment settings */ + +#endif //__VOCORE2_CONFIG_H__ -- 2.25.0

3 2

[PATCH 00/26 v7] Refactor the architecture parts of mt7628
by Stefan Roese 27 Apr '20

27 Apr '20

This patch series are divided into two parts: The main part is to rewrite the whole architecture code of mt7628: * Lock parts of the d-cache for initial stack so the rest of the code can be reimplemented in C. * Memory controller & DDR initialization have been fully written to support detecting DDR size automatically. * DDR calibration has also been reimplemented with a clear logic. * Implemented a new sysreset driver to take advantage of the reset controller so we can drop the use of syscon-based sysreset to reduce size. The second part is to add SPL support for mt7628: * With SPL enabled we can build the ROM-bootable and RAM-bootable binary simultaneously, and we can drop RAM boot related configs and defconfig files. * Generate compressed u-boot.bin image for SPL to reduce size of final combined binary. * Enable DM support for SPL for a more flexible device probing. * Add a demo board (mt7628_rfb) aims at router application. Changes since v2: * Dropped a patch which removes unused parts of mt7628a.dtsi * Move lzma decompression support to common spl_nor.c * Move u-boot,dm-pre-reloc to u-boot-mt7628.dtsi Changes since v3: * Rebased on newest master branch * Add a test for binman etype u-boot-lzma-img to make sure binman passes 100% code coverage * Use u-boot-with-spl.bin for SPL-enabled output file * Remove unused code from spl_nor loader. Changes since v5: * Rebased on newest master branch * Made lzma decompressing support for legacy U-Boot images more generic, so that it can be easily integrated into other devices loaders as well Changes since v6: * Add spl_image_get_comp() to enable the compiler to optimize the switch/case statement away due to Dead Code Elimination as suggested by Daniel * Moved cache flush to MIPS specific file as suggested by Daniel Stefan Roese (6): spl: Extract legacy image handling into separate file spl: spl_legacy: Use IS_ENABLED() to remove #ifdef spl: spl_nor: Move legacy image loading into spl_legacy.c spl: spl_nor: Remove unused variable 'ret' warning mips: spl: Flush cache before jumping to U-Boot proper mips: mtmips: Increase CONFIG_SPL_SYS_MALLOC_F_LEN Weijie Gao (20): mips: add support to restore exception vector base before booting linux mips: mtmips: add predefined i-cache/d-cache size and linesize mips: add an option to support initialize SRAM for initial stack mips: start.S: avoid overwriting outside gd when clearing global data in stack sysreset: add reset controller based reboot driver mips: mtmips: make use of sysreset-resetctrl for mt7628 soc configs: enable CONFIG_RESTORE_EXCEPTION_VECTOR_BASE for all mtmips boards mips: add a mtmips-specific field to architecture-specific global data mips: add a option to support not reserving malloc space on initial stack mips: mtmips: rewrite lowlevel codes of mt7628 dts: mtmips: add alternative pinmux node for uart2 mips: enable support for appending dtb to spl binary mips: add an option to enable u_boot_list section for SPL loaders in u-boot-spl.lds lib: enable lzma decompression support for SPL build Makefile: add support to generate LZMA compressed u-boot image tools: binman: add etype file for u-boot-lzma-img spl: spl_legacy: Add lzma decompression support for legacy image mips: mtmips: add SPL support mips: mtmips: enable SPL for all boards mips: mtmips: add support for mt7628-rfb Makefile | 19 + arch/mips/Kconfig | 66 ++++ arch/mips/cpu/start.S | 16 +- arch/mips/cpu/u-boot-spl.lds | 4 +- arch/mips/dts/Makefile | 1 + arch/mips/dts/mediatek,mt7628-rfb.dts | 67 ++++ arch/mips/dts/mt7628-u-boot.dtsi | 56 +++ arch/mips/dts/mt7628a.dtsi | 17 +- arch/mips/include/asm/global_data.h | 3 + arch/mips/include/asm/u-boot-mips.h | 2 + arch/mips/lib/Makefile | 1 + arch/mips/lib/bootm.c | 3 + arch/mips/lib/spl.c | 21 ++ arch/mips/lib/traps.c | 19 + arch/mips/mach-mtmips/Kconfig | 135 +++---- arch/mips/mach-mtmips/Makefile | 8 +- arch/mips/mach-mtmips/cpu.c | 58 +--- arch/mips/mach-mtmips/ddr_cal.c | 211 +++++++++++ arch/mips/mach-mtmips/ddr_calibrate.c | 309 ----------------- arch/mips/mach-mtmips/ddr_init.c | 194 +++++++++++ arch/mips/mach-mtmips/include/mach/ddr.h | 52 +++ arch/mips/mach-mtmips/include/mach/mc.h | 180 ++++++++++ arch/mips/mach-mtmips/include/mach/serial.h | 13 + arch/mips/mach-mtmips/lowlevel_init.S | 328 ------------------ arch/mips/mach-mtmips/mt7628/Makefile | 6 + arch/mips/mach-mtmips/mt7628/ddr.c | 173 +++++++++ arch/mips/mach-mtmips/mt7628/init.c | 109 ++++++ arch/mips/mach-mtmips/mt7628/lowlevel_init.S | 161 +++++++++ arch/mips/mach-mtmips/mt7628/mt7628.h | 104 ++++++ arch/mips/mach-mtmips/mt7628/serial.c | 34 ++ arch/mips/mach-mtmips/mt76xx.h | 32 -- arch/mips/mach-mtmips/spl.c | 44 +++ board/gardena/smart-gateway-mt7688/board.c | 2 + board/mediatek/mt7628/Kconfig | 12 + board/mediatek/mt7628/MAINTAINERS | 7 + board/mediatek/mt7628/Makefile | 3 + board/mediatek/mt7628/board.c | 8 + common/spl/Makefile | 1 + common/spl/spl.c | 56 +-- common/spl/spl_legacy.c | 131 +++++++ common/spl/spl_nor.c | 27 +- ...gardena-smart-gateway-mt7688-ram_defconfig | 74 ---- .../gardena-smart-gateway-mt7688_defconfig | 14 +- configs/linkit-smart-7688-ram_defconfig | 65 ---- configs/linkit-smart-7688_defconfig | 14 +- configs/mt7628_rfb_defconfig | 46 +++ drivers/sysreset/Kconfig | 6 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_resetctl.c | 48 +++ .../configs/gardena-smart-gateway-mt7688.h | 21 +- include/configs/linkit-smart-7688.h | 22 +- include/configs/mt7628.h | 56 +++ include/spl.h | 13 + lib/Kconfig | 5 + lib/Makefile | 1 + tools/binman/README.entries | 15 + tools/binman/etype/u_boot_lzma_img.py | 28 ++ tools/binman/ftest.py | 7 + tools/binman/test/156_u_boot_lzma_img.dts | 11 + 59 files changed, 2108 insertions(+), 1032 deletions(-) create mode 100644 arch/mips/dts/mediatek,mt7628-rfb.dts create mode 100644 arch/mips/dts/mt7628-u-boot.dtsi create mode 100644 arch/mips/lib/spl.c create mode 100644 arch/mips/mach-mtmips/ddr_cal.c delete mode 100644 arch/mips/mach-mtmips/ddr_calibrate.c create mode 100644 arch/mips/mach-mtmips/ddr_init.c create mode 100644 arch/mips/mach-mtmips/include/mach/ddr.h create mode 100644 arch/mips/mach-mtmips/include/mach/mc.h create mode 100644 arch/mips/mach-mtmips/include/mach/serial.h delete mode 100644 arch/mips/mach-mtmips/lowlevel_init.S create mode 100644 arch/mips/mach-mtmips/mt7628/Makefile create mode 100644 arch/mips/mach-mtmips/mt7628/ddr.c create mode 100644 arch/mips/mach-mtmips/mt7628/init.c create mode 100644 arch/mips/mach-mtmips/mt7628/lowlevel_init.S create mode 100644 arch/mips/mach-mtmips/mt7628/mt7628.h create mode 100644 arch/mips/mach-mtmips/mt7628/serial.c delete mode 100644 arch/mips/mach-mtmips/mt76xx.h create mode 100644 arch/mips/mach-mtmips/spl.c create mode 100644 board/mediatek/mt7628/Kconfig create mode 100644 board/mediatek/mt7628/MAINTAINERS create mode 100644 board/mediatek/mt7628/Makefile create mode 100644 board/mediatek/mt7628/board.c create mode 100644 common/spl/spl_legacy.c delete mode 100644 configs/gardena-smart-gateway-mt7688-ram_defconfig delete mode 100644 configs/linkit-smart-7688-ram_defconfig create mode 100644 configs/mt7628_rfb_defconfig create mode 100644 drivers/sysreset/sysreset_resetctl.c create mode 100644 include/configs/mt7628.h create mode 100644 tools/binman/etype/u_boot_lzma_img.py create mode 100644 tools/binman/test/156_u_boot_lzma_img.dts -- 2.26.2

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[PATCH] imx: Fix imx8m FIT script issue
by Ye Li 27 Apr '20

27 Apr '20

The FIT config node has reversed ATF and u-boot: ATF is set to firmware but u-boot is set to loadable. This script can work previously because spl fit driver wrongly appends fdt to all loadable images. With the issue fixed, the u-boot in loadable does not have fdt appended and fails to work. So correct script by moving u-boot to firmware and ATF to loadable. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- arch/arm/mach-imx/mkimage_fit_atf.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh index ad81d5e..dd1ca5a 100755 --- a/arch/arm/mach-imx/mkimage_fit_atf.sh +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh @@ -116,8 +116,8 @@ if [ -f $BL32 ]; then cat << __CONF_SECTION_EOF config@$cnt { description = "$(basename $dtname .dtb)"; - firmware = "atf@1"; - loadables = "uboot@1", "tee@1"; + firmware = "uboot@1"; + loadables = "atf@1", "tee@1"; fdt = "fdt@$cnt"; }; __CONF_SECTION_EOF @@ -125,8 +125,8 @@ else cat << __CONF_SECTION1_EOF config@$cnt { description = "$(basename $dtname .dtb)"; - firmware = "atf@1"; - loadables = "uboot@1"; + firmware = "uboot@1"; + loadables = "atf@1"; fdt = "fdt@$cnt"; }; __CONF_SECTION1_EOF -- 2.7.4

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[PATCH v2 0/7] Arm Juno board OF_CONTROL upgrade
by Andre Przywara 27 Apr '20

27 Apr '20

Hi, a small update, addressing Tom's comments on patch 1 (which is the only one changed). This removes fdt_high and initrd_high, to allow U-Boot moving those images around. Despite the fix nature of patch 1, this changes some behaviour, so it's definitely *NOT* 2020.04 material anymore. Cheers, Andre ------------ The Juno port in U-Boot didn't see much love lately, so it has fallen a bit behind. We already get a build warning for using an old network driver, but there is more: - The port is using hardcoded information, even though we have quite decent DTs available to find things at runtime. - There is no support for USB or PCI, which pretty much limits the board to load a kernel from flash (yuck!) or TFTP (at least!). - Probably because of this, newer features like UEFI support don't work properly. - There are minor things like less-than-ideal default load addresses and missing reset support. This series is the first part of fixing this. The main part is to switch the board port to use OF_CONTROL, so U-Boot will use a DT to configure itself at runtime. This requires some update to the PL011 driver first (patch 2/7), and allows us to simply enable USB in the defconfig (patch 6/7). USB requires two "usb reset" calls after the initial "usb start" to recognise any devices, not sure why this is. But eventually I am able to load grub from a USB hard drive and do a full featured Ubuntu UEFI boot from there (with a distro kernel). Patches 1, 3, and 7 are mere fixes, patch 4/7 does the actual OF_CONTROL conversion. I also have some proper DM_PCI compliant driver in an advanced state, which allows to load from a SATA hard disk. Unfortunately there is no sky2 network driver in U-Boot, so the Gigabit Ethernet chip connected to PCI will not work easily. I will post this once this is cleaned up and tested. Converting the smc network driver to DM_ETH is on my list as well, but the code is shared with some U-Boot *application* code, also used by some PowerPC boards, so that's not really a low hanging fruit. But it would remove the deprecation warning. Cheers, Andre Changelog v1 ... v2: - drop fdt_high and initrd_high variables - rename initrd_addr to ramdisk_addr_r P.S. In case you want to test this without flashing it, you can chainload U-Boot from an existing U-Boot installation: $ mkimage -A arm64 -O u-boot -T standalone -C none -a 0xe0000000 -e 0xe0000000 -d u-boot.bin -n U-Boot /srv/tftp/u-boot-juno.img VExpress64# tftpboot 0xe0000000 u-boot-juno.img VExpress64# bootm Andre Przywara (7): arm: juno: Fix Juno address variables uart: pl011: Add proper DM clock support arm: juno: Fix UART clock rate arm: juno: Enable OF_CONTROL arm: juno: Use PSCI based reset arm: juno: enable USB arm: vexpress64: Remove unneeded CONFIG_ check arch/arm/Kconfig | 11 ++++++ board/armltd/vexpress64/Kconfig | 7 ++++ board/armltd/vexpress64/vexpress64.c | 61 ++++++++++++++++++++++++++++++++-- configs/vexpress_aemv8a_juno_defconfig | 9 +++-- drivers/serial/serial_pl01x.c | 10 +++++- include/configs/vexpress_aemv8a.h | 41 +++++++++++------------ 6 files changed, 110 insertions(+), 29 deletions(-) -- 2.14.5

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[PATCH 0/6] boards: lx2160aqds: transition to CONFIG_DM_ETH
by Ioana Ciornei 27 Apr '20

27 Apr '20

This patch set targets to add support for CONFIG_DM_ETH for the NXP LX2160AQDS board. The main focus is on changing the DTS based on the SERDES protocol used. In order to accomplish this, the MULTI_DTB_FIT feature is employed and the appropriate DTS is chosed on boot from a list of predefined files. The possible DTS filenames for the board have a standard format that describes for which SERDES protocol combinations it can be used. For example, the 'fsl-lx2160a-qds-19-11-x.dtb' can be used for a LX2160AQDS board which is configured as follows: * SERDES block #1 - protocol 19 * SERDES block #2 - protocol 11 * SERDES block #3 - any protocol Any unnecessary configurations made for the DPAA2 ethernet devices in the board files are compiled out when CONFIG_DM_ETH is enabled. This is because any information necessary is available in its associated DTS node. This patch set depends on another series that adds support for DM_ETH in the ldpaa_eth driver and the RDB boards: https://patchwork.ozlabs.org/project/uboot/list/?series=165158 Ioana Ciornei (6): arm: dts: lx2160a: add any missing dpmac nodes arm: dts: lx2160aqds: add MDIO slots arm: dts: lx2160aqds: add nodes describing possible mezzanine cards board: lx2160aqds: transition to DM_ETH board: lx2160aqds: implement board_fit_config_name_match configs: lx2160aqds_tfa_defconfig: enable DM_ETH and related arch/arm/dts/Makefile | 10 +- arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 ++ arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 ++++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi | 39 +++++ arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi | 55 ++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100 +++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 +++++++++ arch/arm/dts/fsl-lx2160a-qds.dts | 67 +------- arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 86 +++++++++- board/freescale/lx2160a/eth_lx2160aqds.c | 119 +++++++++++++ board/freescale/lx2160a/lx2160a.c | 5 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 8 + configs/lx2160aqds_tfa_defconfig | 8 + 21 files changed, 895 insertions(+), 66 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi -- 2.17.1

3 14

[PATCH v1 00/49] add support for broadcom NS3 soc
by Rayagonda Kokatanur 27 Apr '20

27 Apr '20

This patch series adds support for Broadcom Northstar 3 SoC. NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors targeting a broad range of networking applications. Abhishek Shah (1): board: ns3: add api to save boot parameters passed from BL31 Bharat Gooty (2): include/configs: ns3: add env variables for Linux boot include/configs: ns3: add support for flashing images Bharat Kumar Reddy Gooty (3): board: ns3: program GIC LPI tables board: ns3: limit U-boot relocation within 16MB memory cmd: bcm: add command for chimp hand shake Corneliu Doban (1): cmd: gpt: add eMMC and GPT support Pramod Kumar (4): arm: dts: ns3: add emmc node arm: dts: ns3: add sp805 watchdog node board: ns3: add FIT image its file board: ns3: add development keys used in FIT Rajesh Ravi (1): board: ns3: default reset type to L3 Ray Jui (1): board: ns3: define ddr memory layout Rayagonda Kokatanur (27): board: ns3: add support for Broadcom Northstar 3 arm: cpu: armv8: add L3 memory flush support configs: ns3: enable clock subsystem arm: dts: ns3: add clock dt node configs: ns3: enable pinctrl driver dt-bindings: pinctrl: add ns3 pads definition arm: dts: ns3: add pinctrl node arm: dts: ns3: add gpio node gpio: do not include <asm/arch/gpio.h> on TARGET_BCMNS3 configs: ns3: enable BCM IPROC mmc driver configs: ns3: enable mmc commands arm: dts: ns3: add qspi node dt-bindings: memory: ns3: add memory definitions arm: dts: ns3: add i2c node configs: ns3: enable gpt commands configs: ns3: enable EXT4 and FAT fs support configs: ns3: enable sp805 watchdog driver board: ns3: start sp805 watchdog service dt-bindings: memory: ns3: update GIC LPI address configs: ns3: enable GIC ITS LPI table programing dt-bindings: memory: ns3: add ddr memory definition configs: ns3: enable FIT config configs: ns3: enable PXE boot command configs: ns3: enable RPMB configs: ns3: enable tee and optee driver configs: ns3: env in mmc board: ns3: check chimp handshake status Sheetal Tigadoli (1): common: ns3: add error logging support Srinath Mannam (1): arm: dts: ns3: add PAXB PCIe host and phy node Trac Hoang (2): board: ns3: add generic MCU IPC command send API cmd: bcm: add nitro boot command Vikas Gupta (3): board: ns3: add optee based bnxt fw load driver arm: dts: ns3: add optee node cmd: bcm: add nitro image load commands Vladimir Olovyannikov (2): board: ns3: kconfig: extend board kconfig with specific commands cmd: bcm: add broadcom error log setup command arch/arm/Kconfig | 10 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/bcmns3/Makefile | 5 + arch/arm/cpu/armv8/bcmns3/lowlevel.S | 99 ++ arch/arm/dts/Makefile | 2 + arch/arm/dts/ns3-board.dts | 105 ++ arch/arm/dts/ns3-clock.dtsi | 34 + arch/arm/dts/ns3-pinctrl.dtsi | 321 +++++++ arch/arm/dts/ns3.dtsi | 265 ++++++ arch/arm/include/asm/arch-bcmns3/bl33_info.h | 26 + arch/arm/include/asm/gpio.h | 2 +- board/broadcom/bcmns3/Kconfig | 25 + board/broadcom/bcmns3/Makefile | 7 + board/broadcom/bcmns3/chimp_optee.c | 154 +++ board/broadcom/bcmns3/fit/keys/dev.crt | 21 + board/broadcom/bcmns3/fit/keys/dev.key | 28 + board/broadcom/bcmns3/fit/multi.its | 59 ++ board/broadcom/bcmns3/mcu_cmd.c | 49 + board/broadcom/bcmns3/mcu_cmd.h | 13 + board/broadcom/bcmns3/ns3.c | 263 +++++ cmd/Kconfig | 2 + cmd/Makefile | 2 + cmd/bcm/Kconfig | 12 + cmd/bcm/Makefile | 7 + cmd/bcm/chimp_boot.c | 36 + cmd/bcm/chimp_handshake.c | 32 + cmd/bcm/elog.h | 64 ++ cmd/bcm/logsetup.c | 432 +++++++++ cmd/bcm/nitro_image_load.c | 99 ++ cmd/gpt.c | 95 ++ common/Kconfig | 8 + common/Makefile | 1 + common/bcm_elog.c | 49 + common/console.c | 22 + configs/bcm_ns3_defconfig | 57 ++ include/bcm_elog.h | 37 + include/brcm/chimp.h | 48 + include/configs/bcm_ns3.h | 901 ++++++++++++++++++ include/dt-bindings/memory/bcm-ns3-mc.h | 65 ++ .../dt-bindings/pinctrl/brcm,pinctrl-ns3.h | 41 + 40 files changed, 3498 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv8/bcmns3/Makefile create mode 100644 arch/arm/cpu/armv8/bcmns3/lowlevel.S create mode 100644 arch/arm/dts/ns3-board.dts create mode 100644 arch/arm/dts/ns3-clock.dtsi create mode 100644 arch/arm/dts/ns3-pinctrl.dtsi create mode 100644 arch/arm/dts/ns3.dtsi create mode 100644 arch/arm/include/asm/arch-bcmns3/bl33_info.h create mode 100644 board/broadcom/bcmns3/Kconfig create mode 100644 board/broadcom/bcmns3/Makefile create mode 100644 board/broadcom/bcmns3/chimp_optee.c create mode 100644 board/broadcom/bcmns3/fit/keys/dev.crt create mode 100644 board/broadcom/bcmns3/fit/keys/dev.key create mode 100644 board/broadcom/bcmns3/fit/multi.its create mode 100644 board/broadcom/bcmns3/mcu_cmd.c create mode 100644 board/broadcom/bcmns3/mcu_cmd.h create mode 100644 board/broadcom/bcmns3/ns3.c create mode 100644 cmd/bcm/Kconfig create mode 100644 cmd/bcm/Makefile create mode 100644 cmd/bcm/chimp_boot.c create mode 100644 cmd/bcm/chimp_handshake.c create mode 100644 cmd/bcm/elog.h create mode 100644 cmd/bcm/logsetup.c create mode 100644 cmd/bcm/nitro_image_load.c create mode 100644 common/bcm_elog.c create mode 100644 configs/bcm_ns3_defconfig create mode 100644 include/bcm_elog.h create mode 100644 include/brcm/chimp.h create mode 100644 include/configs/bcm_ns3.h create mode 100644 include/dt-bindings/memory/bcm-ns3-mc.h create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h -- 2.17.1

1 49

[PATCH 1/3] env: mmc: allow support of mmc_get_env_dev with OF_CONTROL
by Patrick Delaunay 27 Apr '20

27 Apr '20

Use the weak function mmc_get_env_dev in mmc_offset_try_partition function to allow dynamic selection of mmc device to use and no more use directly the define CONFIG_SYS_MMC_ENV_DEV. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- env/mmc.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/env/mmc.c b/env/mmc.c index 251ad07d7c..902cca23ad 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -24,14 +24,25 @@ DECLARE_GLOBAL_DATA_PTR; +#if !defined(CONFIG_SYS_MMC_ENV_DEV) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +__weak int mmc_get_env_dev(void) +{ + return CONFIG_SYS_MMC_ENV_DEV; +} + #if CONFIG_IS_ENABLED(OF_CONTROL) static inline int mmc_offset_try_partition(const char *str, s64 *val) { disk_partition_t info; struct blk_desc *desc; int len, i, ret; + char dev_str[4]; - ret = blk_get_device_by_str("mmc", STR(CONFIG_SYS_MMC_ENV_DEV), &desc); + snprintf(dev_str, sizeof(dev_str), "%d", mmc_get_env_dev()); + ret = blk_get_device_by_str("mmc", dev_str, &desc); if (ret < 0) return (ret); @@ -114,11 +125,6 @@ __weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) return 0; } -__weak int mmc_get_env_dev(void) -{ - return CONFIG_SYS_MMC_ENV_DEV; -} - #ifdef CONFIG_SYS_MMC_ENV_PART __weak uint mmc_get_env_part(struct mmc *mmc) { -- 2.17.1

4 10