April 2020 - U-Boot

[PATCH v3] rockchip: Enable SF distro bootcmd
by Jagan Teki 28 Apr '20

28 Apr '20

Enable SPI flash(SF) distro boot command in Rockchip. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Cc: Tom Rini <trini(a)konsulko.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v3: - Don't use SF distro px30 include/configs/rk3399_common.h | 1 + include/configs/rockchip-common.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 01a9174bd2..f0ae6e67a7 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -60,6 +60,7 @@ #endif #include <config_distro_bootcmd.h> +#include <environment/distro/sf.h> #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index b55e09a9ca..2d5d29849d 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -41,11 +41,26 @@ #define BOOT_TARGET_DHCP(func) #endif +#if CONFIG_IS_ENABLED(CMD_SF) + #define BOOT_TARGET_SF(func) func(SF, sf, 0) +#else + #define BOOT_TARGET_SF(func) +#endif + +#ifndef CONFIG_ROCKCHIP_PX30 +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) \ + BOOT_TARGET_SF(func) +#else #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) +#endif #ifdef CONFIG_ARM64 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" -- 2.17.1

2 1

[PATCH v2 0/6] rk3399: Sync linux v5.7-rc1 dts(i)
by Jagan Teki 28 Apr '20

28 Apr '20

This would help to add new boards along with new drivers like DWC3, PCIe on rk3399 platform. So, add v5.7-rc1 linux-next dts(i) files on rk3399 platform. Changes for v2: - keep roc-rk3399-pc dc_12v changes to -u-boot.dtsi [1] https://patchwork.ozlabs.org/project/uboot/cover/20200425105319.12009-1-jag… Any inputs? Jagan. Jagan Teki (5): arm64: dts: rk3399-puma: Move u-boot properties into -u-boot.dtsi arm64: dts: rk3399-evb: Move u-boot properties into -u-boot.dtsi clk: rk3399: Set empty for HCLK_SD assigned-clocks arm64: dts: rk3399: Sync v5.7-rc1 from Linux arm: dts: rk3399: Sync roc-pc-mezzanine from v5.7-rc1 Suniel Mahesh (1): rk3399: Add ROC-RK3399-PC Mezzanine board arch/arm/dts/Makefile | 1 + arch/arm/dts/cros-ec-keyboard.dtsi | 10 +- arch/arm/dts/cros-ec-sbs.dtsi | 39 +- arch/arm/dts/rk3399-evb-u-boot.dtsi | 8 + arch/arm/dts/rk3399-evb.dts | 522 ++++++++---- arch/arm/dts/rk3399-ficus.dts | 6 + arch/arm/dts/rk3399-firefly.dts | 251 ++++-- arch/arm/dts/rk3399-gru-bob.dts | 16 +- arch/arm/dts/rk3399-gru-chromebook.dtsi | 40 +- arch/arm/dts/rk3399-gru-kevin.dts | 34 +- arch/arm/dts/rk3399-gru.dtsi | 90 +- arch/arm/dts/rk3399-khadas-edge.dtsi | 3 + arch/arm/dts/rk3399-leez-p710.dts | 36 +- arch/arm/dts/rk3399-nanopc-t4.dts | 47 +- arch/arm/dts/rk3399-nanopi4.dtsi | 66 +- arch/arm/dts/rk3399-orangepi.dts | 79 +- arch/arm/dts/rk3399-puma-u-boot.dtsi | 31 +- arch/arm/dts/rk3399-puma.dtsi | 578 +++++-------- .../dts/rk3399-roc-pc-mezzanine-u-boot.dtsi | 6 + arch/arm/dts/rk3399-roc-pc-mezzanine.dts | 93 ++ arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 36 + arch/arm/dts/rk3399-roc-pc.dts | 3 +- arch/arm/dts/rk3399-roc-pc.dtsi | 35 +- arch/arm/dts/rk3399-rock-pi-4.dts | 129 +++ arch/arm/dts/rk3399-rock960.dts | 49 ++ arch/arm/dts/rk3399-rock960.dtsi | 13 +- arch/arm/dts/rk3399-rockpro64.dts | 751 +---------------- arch/arm/dts/rk3399-rockpro64.dtsi | 797 ++++++++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 1 + arch/arm/dts/rk3399.dtsi | 583 ++++++++----- board/firefly/roc-pc-rk3399/MAINTAINERS | 2 + configs/roc-pc-mezzanine-rk3399_defconfig | 67 ++ drivers/clk/rockchip/clk_rk3399.c | 1 + 33 files changed, 2763 insertions(+), 1660 deletions(-) create mode 100644 arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-roc-pc-mezzanine.dts create mode 100644 arch/arm/dts/rk3399-rockpro64.dtsi create mode 100644 configs/roc-pc-mezzanine-rk3399_defconfig -- 2.17.1

2 13

[PATCH 4/4] mach-sunxi: Add SPI-NAND SPL-Support
by Benedikt-Alexander Mokroß 28 Apr '20

28 Apr '20

This patch uses the refactored sunxi SPI-SPL driver from the previous patches of this series to add support for SPL booting from SPI-NAND. SPI-NAND-Boot is supported by, at least, the V3s. Signed-off-by: Benedikt-Alexander Mokroß <u-boot(a)bamkrs.de> --- arch/arm/mach-sunxi/spl/spi/Kconfig | 16 + arch/arm/mach-sunxi/spl/spi/Makefile | 1 + .../mach-sunxi/spl/spi/spl_spi_sunxi_nand.c | 497 ++++++++++++++++++ 3 files changed, 678 insertions(+) create mode 100644 arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi_nand.c diff --git a/arch/arm/mach-sunxi/spl/spi/Kconfig b/arch/arm/mach-sunxi/spl/spi/Kconfig index 04e2e506d3..ef14e14ea7 100644 --- a/arch/arm/mach-sunxi/spl/spi/Kconfig +++ b/arch/arm/mach-sunxi/spl/spi/Kconfig @@ -8,6 +8,22 @@ config SPL_SPI_SUNXI_NOR sunxi SPI-NOR Flash. It uses the same method as the boot ROM, so does not need any extra configuration. +config SPL_SPI_SUNXI_NAND + bool "Support for SPI-NAND Flash on Allwinner SoCs in SPL" + depends on MACH_SUN8I_V3S + help + Enable support for SPI-NAND Flash. This option allows SPL to read from + sunxi SPI-NAND Flash. It uses the same method as the boot ROM, so does + not need any extra configuration. + +config SPL_SPI_SUNXI_NAND_USE_GENERIC2K_ON_UNKNOWN + bool "Generic SPI-NAND config with 2K page-size" + depends on SPL_SPI_SUNXI_NAND + default n + help + If no known spi-nand is found, try with generic settings for spi-nand with a + page-size of 2K. + choice prompt "SPI Clockdivider" depends on SPL_SPI_SUNXI diff --git a/arch/arm/mach-sunxi/spl/spi/Makefile b/arch/arm/mach-sunxi/spl/spi/Makefile index 52e58a3c65..696f436e98 100644 --- a/arch/arm/mach-sunxi/spl/spi/Makefile +++ b/arch/arm/mach-sunxi/spl/spi/Makefile @@ -10,6 +10,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o +obj-$(CONFIG_SPL_SPI_SUNXI_NAND) += spl_spi_sunxi_nand.o obj-$(CONFIG_SPL_SPI_SUNXI_NOR) += spl_spi_sunxi_nor.o endif diff --git a/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi_nand.c b/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi_nand.c new file mode 100644 index 0000000000..66cec60839 --- /dev/null +++ b/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi_nand.c @@ -0,0 +-1,497 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Benedikt-Alexander Mokroß <u-boot(a)bamkrs.de> + */ + +#include "spl_spi_sunxi.h" + +/*****************************************************************************/ + +#define DUMMY_BURST_BYTE 0x00 + +#ifndef CONFIG_SPL_SPINAND_SUNXI_SPL_SIZE +#define CONFIG_SPL_SPINAND_SUNXI_SPL_SIZE 0x6000 +#endif +#ifndef CONFIG_SPL_SPINAND_SUNXI_UBOOT_PADDING +#define CONFIG_SPL_SPINAND_SUNXI_UBOOT_PADDING 0x2000 +#endif +#ifndef CONFIG_SPL_SPINAND_SUNXI_PAGESIZE +#define CONFIG_SPL_SPINAND_SUNXI_PAGESIZE 2048 +#endif +#ifndef CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SYS_SPI_U_BOOT_OFFS (CONFIG_SPL_SPINAND_SUNXI_SPL_SIZE * (CONFIG_SPL_SPINAND_SUNXI_PAGESIZE / 1024)) + CONFIG_SPL_SPINAND_SUNXI_UBOOT_PADDING +#endif + +/*****************************************************************************/ + +struct sunxi_nand_config { + const char *name; + u32 jedec_id; + u32 page_mask; + u8 page_shift; + u32 addr_mask; + u8 addr_shift; +}; + +/*****************************************************************************/ + +static const char *sunxi_spl_name = "sunxi SPI-NAND"; + +/** + * List of known NANDS. For now, all of them are generic 2k devices. + */ +static struct sunxi_nand_config sunxi_known_nands[] = { + { + .name = "Macronix MX35LF1GE4AB", + .jedec_id = 0x00C212C2, /* MX35LFxGE4AB repeat the C2x2 over and over again */ + .page_mask = 0x00FFFFFF, + .page_shift = 11, + .addr_mask = 0x7FF, + .addr_shift = 0, + }, + { + .name = "Macronix MX35LF2GE4AB", + .jedec_id = 0x00C222C2, + .page_mask = 0x00FFFFFF, + .page_shift = 11, + .addr_mask = 0x7FF, + .addr_shift = 0, + }, + { + .name = "Winbond W25N01GVxxIG", + .jedec_id = 0x00EFAA21, + .page_mask = 0x0000FFFF, + .page_shift = 11, + .addr_mask = 0x7FF, + .addr_shift = 0, + }, + { + .name = "GigaDevice GD5F1GQ4RCxxG", + .jedec_id = 0x00C8B148, /* 3.3v */ + .page_mask = 0x00FFFFFF, + .page_shift = 11, + .addr_mask = 0x7FF, + .addr_shift = 0, + }, + { + .name = "GigaDevice GD5F1GQ4RCxxG", + .jedec_id = 0x00C8A148, /* 1.8V */ + .page_mask = 0x00FFFFFF, + .page_shift = 11, + .addr_mask = 0x7FF, + .addr_shift = 0, + }, + + { /* Sentinel */ + .name = NULL, + } +}; + +#ifdef CONFIG_SPL_SPI_SUNXI_NAND_USE_GENERIC2K_ON_UNKNOWN +/** + * Generic 2k device-configuration + */ +static struct sunxi_nand_config sunxi_generic_nand_config = { + .name = "Generic 2K SPI-NAND", + .jedec_id = 0xFFFFFFFF, + .page_mask = 0x00FFFFFF, + .page_shift = 11, + .addr_mask = 0x7FF, + .addr_shift = 0, +}; +#endif + +/* + * Enumerate all known nands and return the config if found. + * Returns NULL if none is found or if CONFIG_SPL_SPI_SUNXI_NAND_USE_GENERIC2K_ON_UNKNOWN + * is set, returns a generic configuration compatible to most standard 2k Page-Size SPI-NANDs + */ +static struct sunxi_nand_config *sunxi_spinand_enumerate(u32 jedec_id) +{ + struct sunxi_nand_config *ptr = sunxi_known_nands; + + while (ptr->name) { + if (jedec_id == ptr->jedec_id) { + return ptr; + } + ++ptr; + } +#ifdef CONFIG_SPL_SPI_SUNXI_NAND_USE_GENERIC2K_ON_UNKNOWN + return &sunxi_generic_nand_config; +#else + return NULL; +#endif +} + +/*****************************************************************************/ + +#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ + +/** + * Load a page in devices cache + */ +static void sunxi_spi0_load_page(struct sunxi_nand_config *config, u32 addr, ulong spi_ctl_reg, + ulong spi_ctl_xch_bitmask, + ulong spi_fifo_reg, + ulong spi_tx_reg, + ulong spi_rx_reg, + ulong spi_bc_reg, + ulong spi_tc_reg, + ulong spi_bcc_reg) { + /* Read Page in Cache */ + u8 status = 0x01; + + addr = addr >> (config->page_shift); + addr = addr & config->page_mask; + + writel(4, spi_bc_reg); /* Burst counter (total bytes) */ + writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ + if (spi_bcc_reg) + writel(4, spi_bcc_reg); /* SUN6I also needs this */ + + /* Send the Read Data Bytes (13h) command header */ + writeb(0x13, spi_tx_reg); + writeb((u8)(addr >> 16), spi_tx_reg); + writeb((u8)(addr >> 8), spi_tx_reg); + writeb((u8)(addr), spi_tx_reg); + + /* Start the data transfer */ + setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); + + /* Wait till all bytes are send */ + while ((readl(spi_fifo_reg) & 0x7F0000) > 0) + ; + + /* wait till all bytes are read */ + while ((readl(spi_fifo_reg) & 0x7F) < 4) + ; + + /* Discard the 4 empty bytes from our send */ + readl(spi_rx_reg); + + /* Wait until page loaded */ + do { + /* tCS = 100ns + tRD_ECC 70ns -> 200ns wait */ + ndelay(200); + + /* Poll */ + writel(2 + 1, spi_bc_reg); /* Burst counter (total bytes) */ + writel(2, spi_tc_reg); /* Transfer counter (bytes to send) */ + if (spi_bcc_reg) + writel(2, spi_bcc_reg); /* SUN6I also needs this */ + /* Send the Read Status Bytes (0FC0h) command header */ + writeb(0x0F, spi_tx_reg); + writeb(0xC0, spi_tx_reg); + + /* Start the data transfer */ + setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); + + while ((readl(spi_fifo_reg) & 0x7F) < 2 + 1) + ; + + /* skip 2 since we send 2 */ + readb(spi_rx_reg); + readb(spi_rx_reg); + + status = readb(spi_rx_reg); + + } while ((status & 0x01) == 0x01); +} + +static void spi0_load_page(struct sunxi_nand_config *config, u32 addr) +{ + uintptr_t base = sunxi_spi0_base_address(); + + if (is_sun6i_gen_spi()) { + sunxi_spi0_load_page(config, addr, + base + SUN6I_SPI0_TCR, + SUN6I_TCR_XCH, + base + SUN6I_SPI0_FIFO_STA, + base + SUN6I_SPI0_TXD, + base + SUN6I_SPI0_RXD, + base + SUN6I_SPI0_MBC, + base + SUN6I_SPI0_MTC, + base + SUN6I_SPI0_BCC); + } else { + sunxi_spi0_load_page(config, addr, + base + SUN4I_SPI0_CTL, + SUN4I_CTL_XCH, + base + SUN4I_SPI0_FIFO_STA, + base + SUN4I_SPI0_TX, + base + SUN4I_SPI0_RX, + base + SUN4I_SPI0_BC, + base + SUN4I_SPI0_TC, + 0); + } +} + +/** + * Read data from devices cache + */ +static void sunxi_spi0_read_cache(struct sunxi_nand_config *config, u8 *buf, u32 addr, u32 bufsize, + ulong spi_ctl_reg, + ulong spi_ctl_xch_bitmask, + ulong spi_fifo_reg, + ulong spi_tx_reg, + ulong spi_rx_reg, + ulong spi_bc_reg, + ulong spi_tc_reg, + ulong spi_bcc_reg) +{ + addr = addr >> (config->addr_shift); + addr = addr & config->addr_mask; + + writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */ + writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ + if (spi_bcc_reg) + writel(4, spi_bcc_reg); /* SUN6I also needs this */ + + /* Send the Read Data Bytes (0Bh) command header */ + writeb(0x0B, spi_tx_reg); + writeb((u8)((addr >> 8)), spi_tx_reg); + writeb((u8)(addr), spi_tx_reg); + writeb(DUMMY_BURST_BYTE, spi_tx_reg); + + /* Start the data transfer */ + setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); + + /* Wait until everything is received in the RX FIFO */ + while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize) + ; + + /* Skip 4 bytes since we send 4 */ + readl(spi_rx_reg); + + /* Read the data */ + while (bufsize-- > 0) + *buf++ = readb(spi_rx_reg); + + /* tSHSL time is up to 100 ns in various SPI flash datasheets */ + ndelay(100); +} + +static void spi0_read_cache(struct sunxi_nand_config *config, void *buf, u32 addr, u32 len) +{ + uintptr_t base = sunxi_spi0_base_address(); + + if (is_sun6i_gen_spi()) { + sunxi_spi0_read_cache(config, buf, addr, len, + base + SUN6I_SPI0_TCR, + SUN6I_TCR_XCH, + base + SUN6I_SPI0_FIFO_STA, + base + SUN6I_SPI0_TXD, + base + SUN6I_SPI0_RXD, + base + SUN6I_SPI0_MBC, + base + SUN6I_SPI0_MTC, + base + SUN6I_SPI0_BCC); + } else { + sunxi_spi0_read_cache(config, buf, addr, len, + base + SUN4I_SPI0_CTL, + SUN4I_CTL_XCH, + base + SUN4I_SPI0_FIFO_STA, + base + SUN4I_SPI0_TX, + base + SUN4I_SPI0_RX, + base + SUN4I_SPI0_BC, + base + SUN4I_SPI0_TC, + 0); + } +} + +/** + * Load (bulk) data to cache an read it + * Handles chunking to SPI's buffsize + */ +static void spi0_read_data(struct sunxi_nand_config *config, void *buf, u32 addr, u32 len) +{ + u8 *buf8 = buf; + u32 chunk_len; + u32 curr_page; + u32 last_page = (addr >> (config->page_shift)) & config->page_mask; + + /* Load first page */ + spi0_load_page(config, addr); + + while (len > 0) { + /* Check if new data must be loaded in cache */ + curr_page = (addr >> (config->page_shift)) & config->page_mask; + if (curr_page > last_page) { + spi0_load_page(config, addr); + last_page = curr_page; + } + + /* Chunk to SPI-Buffers max size */ + chunk_len = len; + if (chunk_len > SPI_READ_MAX_SIZE) { + chunk_len = SPI_READ_MAX_SIZE; + } + + /* Check if chunk length exceeds page */ + if ((((addr + chunk_len) >> (config->page_shift)) & config->page_mask) > curr_page) { + chunk_len = ((curr_page + 1) << (config->page_shift)) - addr; + } + + /* Read data from cache */ + spi0_read_cache(config, buf8, addr, chunk_len); + len -= chunk_len; + buf8 += chunk_len; + addr += chunk_len; + } +} + +/** + * Read ID Bytes register + */ +static u32 sunxi_spi0_read_id(ulong spi_ctl_reg, + ulong spi_ctl_xch_bitmask, + ulong spi_fifo_reg, + ulong spi_tx_reg, + ulong spi_rx_reg, + ulong spi_bc_reg, + ulong spi_tc_reg, + ulong spi_bcc_reg) +{ + u8 idbuf[3]; + + writel(2 + 3, spi_bc_reg); /* Burst counter (total bytes) */ + writel(2, spi_tc_reg); /* Transfer counter (bytes to send) */ + if (spi_bcc_reg) + writel(2, spi_bcc_reg); /* SUN6I also needs this */ + + /* Send the Read ID Bytes (9Fh) command header */ + writeb(0x9F, spi_tx_reg); + writeb(DUMMY_BURST_BYTE, spi_tx_reg); + + /* Start the data transfer */ + setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); + + /* Wait until everything is received in the RX FIFO */ + while ((readl(spi_fifo_reg) & 0x7F) < 2 + 3) + ; + + /* Skip 2 bytes */ + readb(spi_rx_reg); + readb(spi_rx_reg); + + /* Read the data */ + //while (bufsize-- > 0) + idbuf[0] = readb(spi_rx_reg); + idbuf[1] = readb(spi_rx_reg); + idbuf[2] = readb(spi_rx_reg); + + /* tSHSL time is up to 100 ns in various SPI flash datasheets */ + ndelay(100); + + return idbuf[2] | (idbuf[1] << 8) | (idbuf[0] << 16); +} + +static u32 spi0_read_id(void) +{ + uintptr_t base = sunxi_spi0_base_address(); + + if (is_sun6i_gen_spi()) { + return sunxi_spi0_read_id( + base + SUN6I_SPI0_TCR, + SUN6I_TCR_XCH, + base + SUN6I_SPI0_FIFO_STA, + base + SUN6I_SPI0_TXD, + base + SUN6I_SPI0_RXD, + base + SUN6I_SPI0_MBC, + base + SUN6I_SPI0_MTC, + base + SUN6I_SPI0_BCC); + } else { + return sunxi_spi0_read_id( + base + SUN4I_SPI0_CTL, + SUN4I_CTL_XCH, + base + SUN4I_SPI0_FIFO_STA, + base + SUN4I_SPI0_TX, + base + SUN4I_SPI0_RX, + base + SUN4I_SPI0_BC, + base + SUN4I_SPI0_TC, + 0); + } +} + +static ulong spi_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) +{ + spi0_read_data((struct sunxi_nand_config *)load->priv, buf, sector, count); + + return count; +} + +/*****************************************************************************/ + +static int spl_spi_nand_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + int ret = 0; + u32 id = 0; + struct image_header *header; + struct sunxi_nand_config *config; + + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + + sunxi_spi0_init(); + id = spi0_read_id(); + + /* + * If we receive only zeros, there is most definetly no device attached. + */ + if (id == 0) { + sunxi_spi0_deinit(); + printf("%s: Received only zeros on jedec_id probe, assuming no spi-nand attached.\n", sunxi_spl_name); + return -1; + } + + /* + * Check if device is known and compatible. + */ + config = sunxi_spinand_enumerate(id); + if (!config) { + sunxi_spi0_deinit(); + printf("%s: Unknown chip %x\n", sunxi_spl_name, id); + return -1; + } + + printf("%s: Found %s (%x)\n", sunxi_spl_name, config->name, id); + + /* + * Read the header data from the image and parse it for validity. + */ + spi0_read_data(config, (void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); + if (image_check_hcrc(header)) { + printf("%s: u-boot hcrc OK!\n", sunxi_spl_name); + + /* If it is an FIT-Image, load as FIT, if not, parse header normaly */ + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("%s: Found FIT image\n", sunxi_spl_name); + load.dev = NULL; + load.priv = (void *)config; + load.filename = NULL; + load.bl_len = 1; + load.read = spi_load_read; + ret = spl_load_simple_fit(spl_image, &load, CONFIG_SYS_SPI_U_BOOT_OFFS, header); + + } else { + ret = spl_parse_image_header(spl_image, header); + if (ret) { + printf("%s: spl_parse_image_header: %x\n", sunxi_spl_name, ret); + sunxi_spi0_deinit(); + return ret; + } + /* + * If everything is fine, read the rest of u-boot and start + */ + spi0_read_data(config, (void *)spl_image->load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size); + return 0; + } + } + printf("%s: u-boot hcrc ERROR!\n", sunxi_spl_name); + sunxi_spi0_deinit(); + return -1; +} + +/* Use priority 0 to override the default if it happens to be linked in */ +SPL_LOAD_IMAGE_METHOD("sunxi SPI-NAND", 0, BOOT_DEVICE_SPI, spl_spi_nand_load_image); -- 2.20.1

1 0

[PATCH 3/4] mach-sunxi: Configurable SPI clockdivider in SPL
by Benedikt-Alexander Mokroß 28 Apr '20

28 Apr '20

This patch adds a configurable spi clockdivider. In the original version, the divider is set to /4 to mimic the BROMs behaviour. However, in many cases this can be changed to /2 or no divider at all to speed up the booting process. Signed-off-by: Benedikt-Alexander Mokroß <u-boot(a)bamkrs.de> --- arch/arm/mach-sunxi/spl/spi/Kconfig | 18 ++++++++++++++++++ arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c | 10 +++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/spl/spi/Kconfig b/arch/arm/mach-sunxi/spl/spi/Kconfig index f92b80583f..2edc7c0917 100644 --- a/arch/arm/mach-sunxi/spl/spi/Kconfig +++ b/arch/arm/mach-sunxi/spl/spi/Kconfig @@ -9,4 +9,22 @@ config SPL_SPI_SUNXI_NOR sunxi SPI-NOR Flash. It uses the same method as the boot ROM, so does not need any extra configuration. +choice + prompt "SPI Clockdivider of Allwinner SoCs in SPL" + depends on SPL_SPI_SUNXI + ---help--- + Select which clock divider should be used for spi clock + +config SPL_SPI_SUNXI_DIV_4 + bool "Clock / 4" + default y + +config SPL_SPI_SUNXI_DIV_2 + bool "Clock / 2" + +config SPL_SPI_SUNXI_DIV_NONE + bool "No clock divider" + +endchoice + endif diff --git a/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c index 2f1d40dcfe..fd5f84a90c 100644 --- a/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl/spi/spl_spi_sunxi.c @@ -69,8 +69,16 @@ void sunxi_spi0_enable_clock(void) setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Clock divider */ - writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? + if (IS_ENABLED(CONFIG_SPL_SPI_SUNXI_DIV_4)) + writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + else if (IS_ENABLED(CONFIG_SPL_SPI_SUNXI_DIV_2)) + writel(SPI0_CLK_DIV_BY_2, base + (is_sun6i_gen_spi() ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + else + writel(SPI0_CLK_DIV_NONE, base + (is_sun6i_gen_spi() ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL)); + /* 24MHz from OSC24M */ writel((1 << 31), CCM_SPI0_CLK); -- 2.20.1

1 0

[PATCH 2/4] mach-sunxi: V3s SPI-SPL
by Benedikt-Alexander Mokroß 28 Apr '20

28 Apr '20

This patch adds support for the Allwinner V3s to SPL_SPI_SUNXI (nothing changed code-wise, only Kconfig). Signed-off-by: Benedikt-Alexander Mokroß <u-boot(a)bamkrs.de> --- arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl/spi/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index f03ce8c9db..7a0f0956c3 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -994,7 +994,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUN8I_V3S help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl/spi/Kconfig b/arch/arm/mach-sunxi/spl/spi/Kconfig index 2f19174d55..f92b80583f 100644 --- a/arch/arm/mach-sunxi/spl/spi/Kconfig +++ b/arch/arm/mach-sunxi/spl/spi/Kconfig @@ -2,7 +2,7 @@ if SPL_SPI_SUNXI config SPL_SPI_SUNXI_NOR bool "Support for SPI-NOR Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUN8I_V3S default y help Enable support for SPI-NOR Flash. This option allows SPL to read from -- 2.20.1

1 0

[PATCH] imx: Add support for i.MX8MM Beacon EmbeddedWorks devkit.
by Adam Ford 28 Apr '20

28 Apr '20

Beacon EmbeddedWorks, formerly known as Logic PD, is releasing a devkit based on the i.MX8M Mini SoC consisting of baseboard + SOM. It supports eMMC on the SOM, microSD on the baseboard, various GPIO, the PINCTRL, and UART. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- The device tree files are pulled from Shawn Guo's imx branch destined for Linux 5.8 and have already been removed, but the ddrc node was deleted. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 59a2713cb2..249d446f69 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -730,7 +730,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-verdin.dtb \ imx8mn-ddr4-evk.dtb \ imx8mq-evk.dtb \ - imx8mp-evk.dtb + imx8mp-evk.dtb \ + imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi new file mode 100644 index 0000000000..baa5f997d0 --- /dev/null +++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + leds { + compatible = "gpio-leds"; + + led0 { + label = "gen_led0"; + gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + default-state = "none"; + }; + + led1 { + label = "gen_led1"; + gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + default-state = "none"; + }; + + led2 { + label = "gen_led2"; + gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + default-state = "none"; + }; + + led3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led3>; + label = "heartbeat"; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_espi2>; + cs-gpios = <&gpio5 9 0>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,at25160bn", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + pagesize = <32>; + size = <2048>; + address-width = <16>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + clock-names = "xclk"; + DCVDD-supply = <&reg_audio>; + DBVDD-supply = <&reg_audio>; + AVDD-supply = <&reg_audio>; + CPVDD-supply = <&reg_audio>; + MICVDD-supply = <&reg_audio>; + PLLVDD-supply = <&reg_audio>; + SPKVDD1-supply = <&reg_audio>; + SPKVDD2-supply = <&reg_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + pca6416_0: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6414>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_led3: led3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 + >; + }; + + pinctrl_pcal6414: pcal6414-gpio { + fsl,pins = < + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi new file mode 100644 index 0000000000..a05e81eeec --- /dev/null +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pca6416_0 { + compatible = "ti,tca6416"; +}; + +&pca6416_1 { + compatible = "ti,tca6416"; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx8mm-beacon-kit.dts b/arch/arm/dts/imx8mm-beacon-kit.dts new file mode 100644 index 0000000000..74a7b0cc10 --- /dev/null +++ b/arch/arm/dts/imx8mm-beacon-kit.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "imx8mm.dtsi" +#include "imx8mm-beacon-som.dtsi" +#include "imx8mm-beacon-baseboard.dtsi" + +/ { + model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; + compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi new file mode 100644 index 0000000000..801bd02eae --- /dev/null +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + clocks = <&osc_32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + eeprom@50 { + compatible = "microchip, at24c64d", "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x50>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + clocks = <&osc_32k>; + clock-names = "extclk"; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + cap-power-off-card; + pm-ignore-notify; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 58f1758ab6..6f6e63472f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -56,6 +56,12 @@ config TARGET_VERDIN_IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_IMX8MM_BEACON + bool "imx8mm Beacon Embedded devkit" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + endchoice source "board/freescale/imx8mq_evk/Kconfig" @@ -63,5 +69,6 @@ source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" source "board/toradex/verdin-imx8mm/Kconfig" +source "board/beacon/imx8mm/Kconfig" endif diff --git a/board/beacon/imx8mm/Kconfig b/board/beacon/imx8mm/Kconfig new file mode 100644 index 0000000000..df3125eae9 --- /dev/null +++ b/board/beacon/imx8mm/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8MM_BEACON + +config SYS_BOARD + default "imx8mm" + +config SYS_VENDOR + default "beacon" + +config SYS_CONFIG_NAME + default "imx8mm_beacon" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/beacon/imx8mm/Makefile b/board/beacon/imx8mm/Makefile new file mode 100644 index 0000000000..7d83895de8 --- /dev/null +++ b/board/beacon/imx8mm/Makefile @@ -0,0 +1,19 @@ +# +# Copyright 2020 Compass Electronics Group, LLC +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_beacon.o +obj-y += ../../freescale/common/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX8M_4G_LPDDR4 +obj-y += lpddr4_timing_4g.o +else +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +endif + +endif diff --git a/board/beacon/imx8mm/README b/board/beacon/imx8mm/README new file mode 100644 index 0000000000..6dc916fc10 --- /dev/null +++ b/board/beacon/imx8mm/README @@ -0,0 +1,37 @@ +U-Boot for the Beacon EmbeddedWorks Devkit + +Quick Start +=========== +- Build the ARM Trusted firmware binary +- Get ddr fimware +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +====================================== +Note: srctree is U-Boot source directory + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ git checkout imx_4.19.35_1.0.0 +$ make PLAT=imx8mm bl31 ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- +$ cp build/imx8mm/release/bl31.bin $(srctree) + +Get the DDR firmware +==================== +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin +$ chmod +x firmware-imx-8.5.bin +$ ./firmware-imx-8.5 +$ cp firmware-imx-8.5/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Build U-Boot +============ +$ make imx8mm_beacon_defconfig +$ make flash.bin ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000 + +Burn U-Boot to microSD Card +=========================== +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +==== +Set Boot switch to SD boot diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c new file mode 100644 index 0000000000..e82e8b78d8 --- /dev/null +++ b/board/beacon/imx8mm/imx8mm_beacon.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} diff --git a/board/beacon/imx8mm/lpddr4_timing.c b/board/beacon/imx8mm/lpddr4_timing.c new file mode 100644 index 0000000000..8e48b9d81b --- /dev/null +++ b/board/beacon/imx8mm/lpddr4_timing.c @@ -0,0 +1,1980 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa1080020 }, + { DDRC_RFSHTMG(0), 0x005b00d2 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG2(0), 0x0000170A }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + { DDRC_DBICTL(0), 0x00000001 }, + + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x0000001f }, + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP2(0), 0x00000000 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x07070707 }, + { DDRC_ADDRMAP7(0), 0x00000f0f }, + + /* performance setting */ + { DDRC_SCHED(0), 0x29001701 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x04000030 }, + { DDRC_PERFLPR1(0), 0x900093e7 }, + { DDRC_PERFWR1(0), 0x20005574 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCFGQOS0_0(0), 0x02100e07 }, + { DDRC_PCFGQOS1_0(0), 0x00620096 }, + { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, + { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + + /* frequency P1&P2 */ + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310000 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, + + /* boot start point */ + { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + + { 0x200b2, 0x1d4 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + + { 0x20025, 0x0 }, + { 0x2002d, LPDDR4_PHY_DMIPinPresent }, + { 0x12002d, LPDDR4_PHY_DMIPinPresent }, + { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), +}; diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c new file mode 100644 index 0000000000..72b1166ced --- /dev/null +++ b/board/beacon/imx8mm/spl.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <cpu_func.h> +#include <hang.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8mm_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/arch/ddr.h> + +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> + +#include <power/pmic.h> +#include <power/bd71837.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + default: + return BOOT_DEVICE_NONE; + } +} + +static void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +static int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@4b", &dev); + if (ret == -ENODEV) { + puts("No pmic\n"); + return 0; + } + if (ret != 0) + return ret; + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); + +#ifndef CONFIG_IMX8M_LPDDR4 + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); +#endif + + /* lock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); + + return 0; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + puts("resetting ...\n"); + + reset_cpu(WDOG1_BASE_ADDR); + + return 0; +} diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig new file mode 100644 index 0000000000..5355119ded --- /dev/null +++ b/configs/imx8mm_beacon_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_IMX8MM_BEACON=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SMBIOS_PRODUCT_NAME="imx8mmn" +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_SPL_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_CONS_INDEX=2 +CONFIG_DM_SERIAL=y +# CONFIG_SPL_DM_SERIAL is not set +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_SMBIOS_MANUFACTURER="logicpd" diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h new file mode 100644 index 0000000000..21102d3c14 --- /dev/null +++ b/include/configs/imx8mm_beacon.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +#ifndef __IMX8MM_BEACON_H +#define __IMX8MM_BEACON_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE SZ_8K +#endif + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x930000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate}" \ + " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ + " ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run finduuid; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* USDHC */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* FEC*/ +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC +#define IMX_FEC_BASE 0x30BE0000 + +#endif -- 2.25.1

2 7

Support for Pinebook Pro v2
by Peter Robinson 28 Apr '20

28 Apr '20

It took a little longer than I planned, took me a little bit to get it working with the upstream device tree that landed in 5.7-rc1 but it's there now. Tested with Fedora 32. Peter

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[PATCH 00/12] Enable DM_ETH on the DPAA1 ARM platforms
by Madalin Bucur 28 Apr '20

28 Apr '20

This patch set enables DM_ETH on the DPAA1 ARM platforms. The required changes are added to the LS104x device trees and LS104xARDB device trees. Changes to the fm driver introduce DM ETH and DM MDIO support while still preserving the legacy functionality. A compilation error related to CONFIG_NAND_BOOT revealed during validation of the changes is also addressed. Madalin Bucur (12): ARM: dts: add QorIQ DPAA 1 FMan v3 device tree nodes ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1043A ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1046A ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDB driver: net: fm: change init_phy() param driver: net: fm: separate receive buffer free code driver: net: fm: add DM MDIO support driver: net: fm: add DM ETH support net: fm: fix compilation issue configs: enable DM_ETH support for LS1043ARDB configs: enable DM_ETH support for LS1046ARDB arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 + arch/arm/dts/fsl-ls1043-post.dtsi | 48 +++ arch/arm/dts/fsl-ls1043a-rdb.dts | 81 +++++ arch/arm/dts/fsl-ls1043a.dtsi | 2 +- arch/arm/dts/fsl-ls1046-post.dtsi | 49 +++ arch/arm/dts/fsl-ls1046a-rdb.dts | 67 ++++ arch/arm/dts/fsl-ls1046a.dtsi | 2 +- arch/arm/dts/qoriq-fman3-0-10g-0.dtsi | 44 +++ arch/arm/dts/qoriq-fman3-0-10g-1.dtsi | 44 +++ arch/arm/dts/qoriq-fman3-0-1g-0.dtsi | 43 +++ arch/arm/dts/qoriq-fman3-0-1g-1.dtsi | 43 +++ arch/arm/dts/qoriq-fman3-0-1g-2.dtsi | 43 +++ arch/arm/dts/qoriq-fman3-0-1g-3.dtsi | 43 +++ arch/arm/dts/qoriq-fman3-0-1g-4.dtsi | 43 +++ arch/arm/dts/qoriq-fman3-0-1g-5.dtsi | 43 +++ arch/arm/dts/qoriq-fman3-0.dtsi | 82 +++++ board/freescale/ls1043ardb/ls1043ardb.c | 2 + board/freescale/ls1046afrwy/ls1046afrwy.c | 2 + board/freescale/ls1046aqds/ls1046aqds.c | 2 + board/freescale/ls1046ardb/ls1046ardb.c | 2 + configs/ls1043ardb_SECURE_BOOT_defconfig | 3 + configs/ls1043ardb_defconfig | 3 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 3 + configs/ls1043ardb_nand_defconfig | 3 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 3 + configs/ls1043ardb_sdcard_defconfig | 3 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 3 + configs/ls1043ardb_tfa_defconfig | 3 + configs/ls1046ardb_emmc_defconfig | 3 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 3 + configs/ls1046ardb_qspi_defconfig | 3 + configs/ls1046ardb_qspi_spl_defconfig | 3 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 3 + configs/ls1046ardb_sdcard_defconfig | 3 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 3 + configs/ls1046ardb_tfa_defconfig | 3 + drivers/net/fm/eth.c | 433 +++++++++++++++++++++--- drivers/net/fm/fm.c | 82 +++++ drivers/net/fm/fm.h | 23 ++ drivers/net/fm/init.c | 2 + drivers/net/fm/memac.c | 1 + drivers/net/fm/memac_phy.c | 139 +++++++- include/fsl_mdio.h | 1 + 43 files changed, 1365 insertions(+), 51 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1043-post.dtsi create mode 100644 arch/arm/dts/fsl-ls1046-post.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-10g-0.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-10g-1.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-1g-0.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-1g-1.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-1g-2.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-1g-3.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-1g-4.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0-1g-5.dtsi create mode 100644 arch/arm/dts/qoriq-fman3-0.dtsi -- 2.1.0

3 14

[PATCH v6 00/17] RISC-V SiFive FU540 support SPL
by Pragnesh Patel 28 Apr '20

28 Apr '20

This series add support for SPL to FU540.U-Boot SPL can boot from L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=sifive/fu540 O=build_dir I=install_dir FW_DYNAMIC=y install 2) cp install_dir/platform/sifive/fu540/firmware/fw_dynamic.bin <u-boot-dir>/ 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) ZSBL loads the U-boot SPL(u-boot-spl.bin) from a partition with GUID type 5B193300-FC78-40CD-8002-E86C45580B47 sudo dd if=spl/u-boot-spl.bin of=/dev/sdc4 bs=1M 7) U-boot SPL expects a u-boot FIT image(u-boot.itb) from 1st partition(/dev/sdc1) of SD card irrespective of GUID sudo dd if=u-boot.itb of=/dev/sdc1 bs=1M Thanks to Yash Shah <yash.shah(a)sifive.com> for testing the series. Changes in v6: - Typo Correction - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi Dual Licensed - Sync Hifive unleashed dts from Linux - Add arch/riscv/fu540 for FU540 specific code Changes in v5: - Return read/write bytes for sifive_otp_read and sifive_otp_write - Correct Palmer's email address Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Pragnesh Patel (17): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: Add clock initialization for SPL riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux sifive: dts: fu540: Enable gpio in U-Boot SPL riscv: sifive: fu540: add SPL configuration configs: fu540: Add config options for U-Boot SPL sifive: dts: fu540: Enable L2 Cache in U-Boot riscv: sifive: fu540: enable all cache ways from u-boot proper sifive: fix palmer's email address doc: update FU540 RISC-V documentation arch/riscv/Makefile | 1 + arch/riscv/cpu/u-boot-spl.lds | 1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 79 + arch/riscv/dts/fu540-c000.dtsi | 37 +- ...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 27 + arch/riscv/dts/hifive-unleashed-a00.dts | 9 + arch/riscv/fu540/Makefile | 10 + arch/riscv/fu540/cache.c | 58 + arch/riscv/fu540/spl.c | 30 + arch/riscv/include/asm/arch-generic/cache.h | 14 + arch/riscv/include/asm/arch-generic/gpio.h | 3 + arch/riscv/include/asm/arch-generic/spl.h | 14 + board/sifive/fu540/Kconfig | 10 + board/sifive/fu540/MAINTAINERS | 2 +- board/sifive/fu540/Makefile | 4 + board/sifive/fu540/fu540.c | 143 +- board/sifive/fu540/spl.c | 72 + common/spl/Kconfig | 6 + configs/sifive_fu540_defconfig | 11 + doc/board/sifive/fu540.rst | 409 ++++- drivers/clk/sifive/fu540-prci.c | 218 ++- drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/sifive-otp.c | 255 +++ drivers/mmc/Kconfig | 1 + drivers/ram/Kconfig | 7 + drivers/ram/Makefile | 2 + drivers/ram/sifive/Kconfig | 8 + drivers/ram/sifive/Makefile | 6 + drivers/ram/sifive/sdram_fu540.c | 399 +++++ include/configs/sifive-fu540.h | 18 + lib/Makefile | 1 + 33 files changed, 3241 insertions(+), 111 deletions(-) create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi create mode 100644 arch/riscv/fu540/Makefile create mode 100644 arch/riscv/fu540/cache.c create mode 100644 arch/riscv/fu540/spl.c create mode 100644 arch/riscv/include/asm/arch-generic/cache.h create mode 100644 arch/riscv/include/asm/arch-generic/spl.h create mode 100644 board/sifive/fu540/spl.c create mode 100644 drivers/misc/sifive-otp.c create mode 100644 drivers/ram/sifive/Kconfig create mode 100644 drivers/ram/sifive/Makefile create mode 100644 drivers/ram/sifive/sdram_fu540.c -- 2.17.1

3 75

[PATCH] Azure/GitLab: Update to latest Docker image
by Tom Rini 28 Apr '20

28 Apr '20

This provides a newer ARC toolchain along with being based on a newer Ubuntu bionic tag. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- .azure-pipelines.yml | 2 +- .gitlab-ci.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index d3e7b4dd0209..a043d2922bb1 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -1,7 +1,7 @@ variables: windows_vm: vs2017-win2016 ubuntu_vm: ubuntu-18.04 - ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200311-10Apr2020 + ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 08bdf81e74d3..55bde3d86bf5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found at: # https://gitlab.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:bionic-20200311-10Apr2020 +image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020 # We run some tests in different order, to catch some failures quicker. stages: -- 2.17.1

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