April 2020 - U-Boot

[PATCH v2 0/2] add brcm iproc gpio driver
by Rayagonda Kokatanur 30 Apr '20

30 Apr '20

Add support for broadcom iproc gpio driver. Changes from v1: -Address review comments from Simon Glass, Use dev_read_...() instead of fdtdec_...(). Rayagonda Kokatanur (2): drivers: gpio: add broadcom iproc gpio driver support gpio: do not include <asm/arch/gpio.h> on TARGET_BCMNS3 arch/arm/include/asm/gpio.h | 2 +- drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/iproc_gpio.c | 259 ++++++++++++++++++++++++++++++++++++ 4 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 drivers/gpio/iproc_gpio.c -- 2.17.1

2 5

[PATCH v4 0/9] x86: Improve support for chain-loading U-Boot
by Simon Glass 30 Apr '20

30 Apr '20

This little series adds a few checks into the code to allow better operation when booting a build from a previous-state loader such as coreboot. At present we have a 'coreboot' target but this runs very different code from the bare-metal targets, such as coral. There is very little in common between them. It is useful to be able to boot the same U-Boot on a device, with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. This series allows U-Boot to detect that it ran from coreboot and automatically do the right thing. This series makes the most important changes to allow the same u-boot.bin for coral to boot after coreboot (by itself) or bare metal (via TPL->SPL). Changes in v4: - Rename flag to GD_FLG_SKIP_LL_INIT - Add new patch to move coreboot-table detection into common code - Rename flag to GD_FLG_SKIP_LL_INIT - Split this patch into two - Update to use locate_coreboot_table() Changes in v3: - Add a new patch with a gd flag for chain loading - Add new patch to detect running from coreboot Changes in v2: - Drop the other check in interrupt_init() which is not needed now - Drop patch 'dm: Avoid initing built-in devices when chain loading' Simon Glass (9): x86: fsp: Allow skipping init code when chain loading x86: apl: Skip init code when chain loading x86: cpu: Skip init code when chain loading pci: Avoid auto-config when chain loading board: Add a gd flag for chain loading x86: Move coreboot-table detection into common code x86: Add a way to detect running from coreboot x86: Use the existing stack when chain-loading x86: Add documentation for the chain-load feature arch/x86/cpu/apollolake/fsp_s.c | 2 ++ arch/x86/cpu/coreboot/tables.c | 24 +++++++++------------- arch/x86/cpu/cpu.c | 4 +++- arch/x86/cpu/i386/cpu.c | 27 +++++++++++++++++++++++++ arch/x86/cpu/i386/interrupt.c | 6 ++++-- arch/x86/cpu/start_from_spl.S | 16 +++++++++++++-- arch/x86/include/asm/coreboot_tables.h | 7 +++++++ arch/x86/lib/fsp/fsp_dram.c | 8 ++++++++ arch/x86/lib/fsp/fsp_graphics.c | 3 +++ arch/x86/lib/fsp2/fsp_dram.c | 10 +++++++++ arch/x86/lib/fsp2/fsp_init.c | 2 +- arch/x86/lib/init_helpers.c | 3 +++ doc/arch/x86.rst | 28 ++++++++++++++++++++++++++ drivers/pci/pci-uclass.c | 4 ++-- include/asm-generic/global_data.h | 1 + include/init.h | 2 +- 16 files changed, 123 insertions(+), 24 deletions(-) -- 2.26.2.303.gf8c07b1a785-goog

3 21

[PATCH] rk3399: Enable SF distro bootcmd
by Jagan Teki 30 Apr '20

30 Apr '20

Enable SPI flash(SF) distro boot command in rk3399. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Cc: Kever Yang <kever.yang(a)rock-chips.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- include/configs/rk3399_common.h | 1 + include/configs/rockchip-common.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 01a9174bd2..f0ae6e67a7 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -60,6 +60,7 @@ #endif #include <config_distro_bootcmd.h> +#include <environment/distro/sf.h> #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index b55e09a9ca..bf8c60d6dd 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -41,11 +41,26 @@ #define BOOT_TARGET_DHCP(func) #endif +#if CONFIG_IS_ENABLED(CMD_SF) + #define BOOT_TARGET_SF(func) func(SF, sf, 0) +#else + #define BOOT_TARGET_SF(func) +#endif + +#ifdef CONFIG_ROCKCHIP_RK3399 +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) \ + BOOT_TARGET_SF(func) +#else #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) +#endif #ifdef CONFIG_ARM64 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" -- 2.17.1

2 2

[PATCH v3 0/5] cmd: bind allow to bind driver with driver_data
by Patrice Chotard 30 Apr '20

30 Apr '20

- fix the bind command - add a bind command test - add bind command documentation Changes in v3: - fix typo - add bind/unbind parameters description and how to find them Changes in v2: - add a bind command test - add bind command documentation in doc/driver/model/bind.rst - simplify patch 1 by using lists_bind_fdt() Patrice Chotard (5): cmd: bind: allow to bind driver with driver data sandbox: phy: add driver_data for bind test cmd sandbox: dts: Add compatible string for bind-test node test/py: Update test_bind doc: add bind/unbind command documentation arch/sandbox/dts/test.dts | 1 + cmd/bind.c | 5 ++-- doc/driver-model/bind.rst | 49 ++++++++++++++++++++++++++++++++++++++ doc/driver-model/index.rst | 1 + drivers/phy/sandbox-phy.c | 18 +++++++++++++- test/py/tests/test_bind.py | 18 +++++++------- 6 files changed, 80 insertions(+), 12 deletions(-) create mode 100644 doc/driver-model/bind.rst -- 2.17.1

3 7

[RFC PATCH v3] arch: x86: apl: Read FSP-M configuration from device-tree
by Bernhard Messerklinger 30 Apr '20

30 Apr '20

Move FSP-M configuration to the device-tree like it's already done for other SoCs (Baytrail). Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger(a)br-automation.com> --- With this patch I moved the FSP-M configuration to the device-tree based on the Baytrail boards. Changes in v3: Added doc binding file Added fspm prefix to some variables Changes in v2: Added commit notes arch/x86/cpu/apollolake/fsp_m.c | 341 ++++++++++++------ arch/x86/dts/chromebook_coral.dts | 35 ++ .../asm/arch-apollolake/fsp/fsp_m_upd.h | 165 +++++++++ .../fsp/fsp2/apollolake/fsp-m.txt | 312 ++++++++++++++++ 4 files changed, 733 insertions(+), 120 deletions(-) create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 5308af8ed4..81004fba6f 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -12,21 +12,6 @@ #include <asm/fsp2/fsp_internal.h> #include <dm/uclass-internal.h> -/* - * ODT settings: - * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B, - * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A - * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW. - * - * Note that the enum values correspond to the interpreted UPD fields - * within Ch[3:0]_OdtConfig parameters. - */ -enum { - ODT_A_B_HIGH_LOW = 0 << 1, - ODT_A_B_HIGH_HIGH = 1 << 1, - N_WR_24 = 1 << 5, -}; - /* * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. * There are four physical LPDDR4 channels, each 32-bits wide. There are two @@ -67,122 +52,238 @@ struct lpddr4_swizzle_cfg { struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS]; }; -static void setup_sdram(struct fsp_m_config *cfg, - const struct lpddr4_swizzle_cfg *swizzle_cfg) -{ - const struct lpddr4_chan_swizzle_cfg *sch; - /* Number of bytes to copy per DQS */ - const size_t sz = DQ_BITS_PER_DQS; - int chan; - - cfg->memory_down = 1; - cfg->scrambler_support = 1; - cfg->channel_hash_mask = 0x36; - cfg->slice_hash_mask = 9; - cfg->interleaved_mode = 2; - cfg->channels_slices_enable = 0; - cfg->min_ref_rate2x_enable = 0; - cfg->dual_rank_support_enable = 1; - - /* LPDDR4 is memory down so no SPD addresses */ - cfg->dimm0_spd_address = 0; - cfg->dimm1_spd_address = 0; - - for (chan = 0; chan < 4; chan++) { - struct fsp_ram_channel *ch = &cfg->chan[chan]; - - ch->rank_enable = 1; - ch->device_width = 1; - ch->dram_density = 2; - ch->option = 3; - ch->odt_config = ODT_A_B_HIGH_HIGH; - } - - /* - * CH0_DQB byte lanes in the bit swizzle configuration field are - * not 1:1. The mapping within the swizzling field is: - * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] - * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] - * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] - * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH0B]; - memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz); - memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz); - - /* - * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH0A]; - memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz); - memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz); - - sch = &swizzle_cfg->phys[LP4_PHYS_CH1B]; - memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz); - memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz); - - /* - * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH1A]; - memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz); - memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz); -} - int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) { struct fsp_m_config *cfg = &upd->config; struct fspm_arch_upd *arch = &upd->arch; + char chx_buf[30]; + const struct lpddr4_chan_swizzle_cfg *sch; + const struct lpddr4_swizzle_cfg *swizzle_cfg; + const size_t sz = DQ_BITS_PER_DQS; + bool tmp; + const u8 *gpio_table_pins; + const char *oem_file; arch->nvs_buffer_ptr = NULL; prepare_mrc_cache(upd); arch->stack_base = (void *)0xfef96000; arch->boot_loader_tolum_size = 0; - arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; - cfg->serial_debug_port_type = 2; - cfg->serial_debug_port_device = 2; - cfg->serial_debug_port_stride_size = 2; - cfg->serial_debug_port_address = 0; - - cfg->package = 1; - /* Don't enforce a memory size limit */ - cfg->memory_size_limit = 0; - cfg->low_memory_max_value = 2048; /* 2 GB */ - /* No restrictions on memory above 4GiB */ - cfg->high_memory_max_value = 0; - - /* Always default to attempt to use saved training data */ - cfg->disable_fast_boot = 0; - - const u8 *swizzle_data; - - swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle", - LP4_NUM_BYTE_LANES * - DQ_BITS_PER_DQS * - LP4_NUM_PHYS_CHANNELS); - if (!swizzle_data) - return log_msg_ret("Cannot read swizzel data", -EINVAL); - - setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data); - - cfg->pre_mem_gpio_table_ptr = 0; - cfg->profile = 0xb; - cfg->msg_level_mask = 0; - - /* other */ - cfg->skip_cse_rbp = 1; - cfg->periodic_retraining_disable = 0; - cfg->enable_s3_heci2 = 0; + cfg->serial_debug_port_type = dev_read_u32_default(dev, + "fspm,serial-debug-port-type", + SERIAL_DEBUG_PORT_TYPE_MMIO); + cfg->serial_debug_port_device = dev_read_u32_default(dev, + "fspm,serial-debug-port-device", + SERIAL_DEBUG_PORT_DEVICE_UART2); + if (cfg->serial_debug_port_device == SERIAL_DEBUG_PORT_DEVICE_EXTERNAL) + cfg->serial_debug_port_address = dev_read_u32_default(dev, + "fspm,serial-debug-port-address", + 0); + cfg->serial_debug_port_stride_size = dev_read_u32_default(dev, + "fspm,serial-debug-port-stride-size", + SERIAL_DEBUG_PORT_STRIDE_SIZE_4); + cfg->mrc_fast_boot = !dev_read_bool(dev, "fspm,disable-mrc-fast-boot"); + cfg->igd = !dev_read_bool(dev, "fspm,disable-igd"); + if (cfg->igd) { + cfg->igd_dvmt50_pre_alloc = dev_read_u32_default(dev, + "fspm,igd-dvmt50-pre-alloc", + IGD_DVMT_50_PRE_ALLOC_64M); + cfg->igd_aperture_size = dev_read_u32_default(dev, + "fspm,aperture-size", + IGD_APERTURE_SIZE_128M); + cfg->gtt_size = dev_read_u32_default(dev, "fspm,gtt-size", + GTT_SIZE_8M); + cfg->primary_video_adaptor = dev_read_u32_default(dev, + "fspm,primary-video-adaptor", + PRIMARY_VIDEO_ADAPTER_AUTO); + } + cfg->package = dev_read_u32_default(dev, "fspm,package", + PACKAGE_SODIMM); + cfg->profile = dev_read_u32_default(dev, "fspm,profile", + PROFILE_DDR3_1600_11_11_11); + cfg->memory_down = dev_read_u32_default(dev, "fspm,memory-down", + MEMORY_DOWN_NO); + if (cfg->memory_down & MEMORY_DOWN_YES) { + cfg->ddr3_l_page_size = dev_read_u32_default(dev, + "fspm,ddr3l-page-size", 1); + cfg->ddr3_lasr = dev_read_bool(dev, "fspm,enable-ddr3-lasr"); + } + cfg->scrambler_support = dev_read_bool(dev, + "fspm,enable-scrambler-support"); + tmp = dev_read_bool(dev, "fspm,enable-interleaved-mode"); + cfg->interleaved_mode = (tmp == 0) ? INTERLEAVED_MODE_DISABLE : + INTERLEAVED_MODE_ENABLE; + cfg->channel_hash_mask = dev_read_u32_default(dev, + "fspm,channel-hash-mask", + 0); + cfg->slice_hash_mask = dev_read_u32_default(dev, + "fspm,slice-hash-mask", 0); + cfg->channels_slices_enable = dev_read_bool(dev, + "fspm,enable-channels-slices"); + cfg->min_ref_rate2x_enable = dev_read_bool(dev, + "fspm,enable-min-ref-rate2x"); + cfg->dual_rank_support_enable = !dev_read_bool(dev, + "fspm,disable-dual-rank-support"); + tmp = dev_read_bool(dev, "fspm,enable-rmt-mode"); + cfg->rmt_mode = (tmp == 0) ? RMT_MODE_DISABLE : RMT_MODE_ENABLE; + cfg->memory_size_limit = dev_read_u32_default(dev, + "fspm,memory-size-limit", 0); + cfg->low_memory_max_value = dev_read_u32_default(dev, + "fspm,low-memory-max-value", 0); + cfg->high_memory_max_value = dev_read_u32_default(dev, + "fspm,high-memory-max-value", + 0); + cfg->disable_fast_boot = dev_read_bool(dev, "fspm,disable-fast-boot"); + cfg->dimm0_spd_address = 0; + cfg->dimm1_spd_address = 0; + if (!(cfg->memory_down & MEMORY_DOWN_YES)) { + cfg->dimm0_spd_address = dev_read_u32_default(dev, + "fspm,dimm0-spd-address", 0xa0); + cfg->dimm1_spd_address = dev_read_u32_default(dev, + "fspm,dimm1-spd-address", 0xa4); + } + if (cfg->memory_down != 0) { + for (int i = 0; i < FSP_DRAM_CHANNELS; i++) { + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-enable-rank", i); + cfg->chan[i].rank_enable = dev_read_bool(dev, chx_buf); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-device-width", i); + cfg->chan[i].device_width = dev_read_u32_default(dev, + chx_buf, 0); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-dram-density", i); + cfg->chan[i].dram_density = dev_read_u32_default(dev, + chx_buf, 0); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-option", i); + cfg->chan[i].option = dev_read_u32_default(dev, chx_buf, + 0); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-odt-config", i); + cfg->chan[i].odt_config = dev_read_u32_default(dev, + chx_buf, + 0); + cfg->chan[i].tristate_clk1 = 0; + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-enable-mode2-n", i); + cfg->chan[i].mode2_n = dev_read_u32_default(dev, + chx_buf, + CHX_MODE2N_AUTO); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-odt-levels", i); + cfg->chan[i].odt_levels = dev_read_u32_default(dev, + chx_buf, + CHX_ODT_LEVELS_CONNECTED_TO_SOC); + } + } + cfg->rmt_check_run = dev_read_bool(dev, + "fspm,rmt-degrade-margin-check"); + cfg->rmt_margin_check_scale_high_threshold = dev_read_u32_default(dev, + "fspm,rmt-margin-check-scale-high-threshold", + 0); + swizzle_cfg = (const struct lpddr4_swizzle_cfg *)dev_read_u8_array_ptr( + dev, "lpddr4-swizzle", + LP4_NUM_BYTE_LANES * + DQ_BITS_PER_DQS * + LP4_NUM_PHYS_CHANNELS); + + if (swizzle_cfg) { + /* + * CH0_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0B]; + memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz); + memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz); + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are + * 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0A]; + memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz); + memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz); + sch = &swizzle_cfg->phys[LP4_PHYS_CH1B]; + memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz); + memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz); + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are + * 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH1A]; + memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz); + memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz); + } + cfg->msg_level_mask = dev_read_u32_default(dev, "fspm,msg-level-mask", + 0); + memset(cfg->pre_mem_gpio_table_pin_num, 0, + sizeof(cfg->pre_mem_gpio_table_pin_num)); + gpio_table_pins = dev_read_u8_array_ptr(dev, + "fspm,pre-mem-gpio-table-pin-num", + sizeof(gpio_table_pins)); + if (gpio_table_pins) + memcpy(cfg->pre_mem_gpio_table_pin_num, gpio_table_pins, + sizeof(gpio_table_pins)); + cfg->pre_mem_gpio_table_ptr = dev_read_u32_default(dev, + "fspm,pre-mem-gpio-table-ptr", + 0); + cfg->pre_mem_gpio_table_entry_num = dev_read_u32_default(dev, + "fspm,pre-mem-gpio-table-entry-num", + 0); + cfg->enhance_port8xh_decoding = !dev_read_bool(dev, + "fspm,disable-enhance-port8xh-decoding"); + cfg->spd_write_enable = dev_read_bool(dev, "fspm,enable-spd-write"); + cfg->oem_loading_base = dev_read_u32_default(dev, + "fspm,oem-loading-base", + 0); + memset(cfg->oem_file_name, 0, sizeof(cfg->oem_file_name)); + oem_file = dev_read_string(dev, "fspm,oem-file-name"); + if (oem_file) + memcpy(cfg->oem_file_name, oem_file, + sizeof(cfg->oem_file_name)); + cfg->mrc_data_saving = dev_read_bool(dev, + "fspm,enable_mrc-data-saving"); + cfg->e_mmc_trace_len = dev_read_bool(dev, "fspm,emmc-trace-len-short"); + cfg->skip_cse_rbp = dev_read_bool(dev, "fspm,enable-skip-cse-rbp"); + cfg->npk_en = dev_read_u32_default(dev, "fspm,enable-npk", NPK_EN_AUTO); + cfg->fw_trace_en = !dev_read_bool(dev, "fspm,disable-fw-trace"); + cfg->fw_trace_destination = dev_read_u32_default(dev, + "fspm,fw-trace-destination", + FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI); + cfg->recover_dump = dev_read_bool(dev, "fspm,enable-recover-dump"); + cfg->msc0_wrap = dev_read_u32_default(dev, "fspm,msc0-wrap", + MSC_X_WRAP_1); + cfg->msc1_wrap = dev_read_u32_default(dev, "fspm,msc1-wrap", + MSC_X_WRAP_1); + cfg->msc0_size = dev_read_u32_default(dev, "fspm,msc0-size", + MSC_X_SIZE_0M); + cfg->msc1_size = dev_read_u32_default(dev, "fspm,msc1-size", + MSC_X_SIZE_0M); + cfg->pti_mode = dev_read_u32_default(dev, "fspm,pti-mode", PTI_MODE_x4); + cfg->pti_training = dev_read_u32_default(dev, "fspm,pti-training", 0); + cfg->pti_speed = dev_read_u32_default(dev, "fspm,pti-speed", + PTI_SPEED_QUARTER); + cfg->punit_mlvl = dev_read_u32_default(dev, "fspm,punit-mlvl", 0); + cfg->pmc_mlvl = dev_read_u32_default(dev, "fspm,pmc-mlvl", 0); + cfg->sw_trace_en = dev_read_bool(dev, "fspm,enable-sw-trace"); + cfg->periodic_retraining_disable = dev_read_bool(dev, + "fspm,disable-periodic-retraining"); + cfg->enable_reset_system = dev_read_bool(dev, + "fspm,enable-reset-system"); + cfg->enable_s3_heci2 = !dev_read_bool(dev, "fspm,disable-s3-heci2"); return 0; } diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index af52e11c89..a205430abf 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -21,6 +21,7 @@ #include <asm/arch-apollolake/iomap.h> #include <asm/arch-apollolake/pm.h> #include <dt-bindings/clock/intel-clock.h> +#include <asm/arch-apollolake/fsp/fsp_m_upd.h> / { model = "Google Coral"; @@ -436,6 +437,40 @@ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ >; + fspm,package = <PACKAGE_BGA>; + fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; + fspm,memory-down = <MEMORY_DOWN_YES>; + fspm,enable-scrambler-support; + fspm,enable-interleaved-mode = <INTERLEAVED_MODE_ENABLE>; + fspm,channel-hash-mask = <0x36>; + fspm,slice-hash-mask = <0x9>; + fspm,low-memory-max-value = <2048>; + fspm,ch0-enable-rank; + fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch1-enable-rank; + fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch2-enable-rank; + fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch3-enable-rank; + fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,enable-skip-cse-rbp; + lpddr4-swizzle = /bits/ 8 < /* LP4_PHYS_CH0A */ diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h index 93bee5b2d1..2151290c69 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -7,6 +7,7 @@ #ifndef __ASM_ARCH_FSP_M_UDP_H #define __ASM_ARCH_FSP_M_UDP_H +#ifndef __ASSEMBLY__ #include <asm/fsp2/fsp_api.h> #define FSP_DRAM_CHANNELS 4 @@ -119,5 +120,169 @@ struct __packed fspm_upd { u8 unused_upd_space2[158]; u16 upd_terminator; }; +#endif + +#define SERIAL_DEBUG_PORT_TYPE_NONE 0 +#define SERIAL_DEBUG_PORT_TYPE_IO 1 +#define SERIAL_DEBUG_PORT_TYPE_MMIO 2 + +#define SERIAL_DEBUG_PORT_DEVICE_UART0 0 +#define SERIAL_DEBUG_PORT_DEVICE_UART1 1 +#define SERIAL_DEBUG_PORT_DEVICE_UART2 2 +#define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3 + +#define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0 +#define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2 + +#define IGD_DVMT_50_PRE_ALLOC_64M 0x02 +#define IGD_DVMT_50_PRE_ALLOC_96M 0x03 +#define IGD_DVMT_50_PRE_ALLOC_128M 0x04 +#define IGD_DVMT_50_PRE_ALLOC_160M 0x05 +#define IGD_DVMT_50_PRE_ALLOC_192M 0x06 +#define IGD_DVMT_50_PRE_ALLOC_224M 0x07 +#define IGD_DVMT_50_PRE_ALLOC_256M 0x08 +#define IGD_DVMT_50_PRE_ALLOC_288M 0x09 +#define IGD_DVMT_50_PRE_ALLOC_320M 0x0a +#define IGD_DVMT_50_PRE_ALLOC_352M 0x0b +#define IGD_DVMT_50_PRE_ALLOC_384M 0x0c +#define IGD_DVMT_50_PRE_ALLOC_416M 0x0d +#define IGD_DVMT_50_PRE_ALLOC_448M 0x0e +#define IGD_DVMT_50_PRE_ALLOC_480M 0x0f +#define IGD_DVMT_50_PRE_ALLOC_512M 0x10 + +#define IGD_APERTURE_SIZE_128M 0x1 +#define IGD_APERTURE_SIZE_256M 0x2 +#define IGD_APERTURE_SIZE_512M 0x3 + +#define GTT_SIZE_2M 1 +#define GTT_SIZE_4M 2 +#define GTT_SIZE_8M 3 + +#define PRIMARY_VIDEO_ADAPTER_AUTO 0 +#define PRIMARY_VIDEO_ADAPTER_IGD 2 +#define PRIMARY_VIDEO_ADAPTER_PCI 3 + +#define PACKAGE_SODIMM 0 +#define PACKAGE_BGA 1 +#define PACKAGE_BGA_MIRRORED 2 +#define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3 + +#define PROFILE_WIO2_800_7_8_8 0x1 +#define PROFILE_WIO2_1066_9_10_10 0x2 +#define PROFILE_LPDDR3_1066_8_10_10 0x3 +#define PROFILE_LPDDR3_1333_10_12_12 0x4 +#define PROFILE_LPDDR3_1600_12_15_15 0x5 +#define PROFILE_LPDDR3_1866_14_17_17 0x6 +#define PROFILE_LPDDR3_2133_16_20_20 0x7 +#define PROFILE_LPDDR4_1066_10_10_10 0x8 +#define PROFILE_LPDDR4_1600_14_15_15 0x9 +#define PROFILE_LPDDR4_2133_20_20_20 0xa +#define PROFILE_LPDDR4_2400_24_22_22 0xb +#define PROFILE_LPDDR4_2666_24_24_24 0xc +#define PROFILE_LPDDR4_2933_28_27_27 0xd +#define PROFILE_LPDDR4_3200_28_29_29 0xe +#define PROFILE_DDR3_1066_6_6_6 0xf +#define PROFILE_DDR3_1066_7_7_7 0x10 +#define PROFILE_DDR3_1066_8_8_8 0x11 +#define PROFILE_DDR3_1333_7_7_7 0x12 +#define PROFILE_DDR3_1333_8_8_8 0x13 +#define PROFILE_DDR3_1333_9_9_9 0x14 +#define PROFILE_DDR3_1333_10_10_10 0x15 +#define PROFILE_DDR3_1600_8_8_8 0x16 +#define PROFILE_DDR3_1600_9_9_9 0x17 +#define PROFILE_DDR3_1600_10_10_10 0x18 +#define PROFILE_DDR3_1600_11_11_11 0x19 +#define PROFILE_DDR3_1866_10_10_10 0x1a +#define PROFILE_DDR3_1866_11_11_11 0x1b +#define PROFILE_DDR3_1866_12_12_12 0x1c +#define PROFILE_DDR3_1866_13_13_13 0x1d +#define PROFILE_DDR3_2133_11_11_11 0x1e +#define PROFILE_DDR3_2133_12_12_12 0x1f +#define PROFILE_DDR3_2133_13_13_13 0x20 +#define PROFILE_DDR3_2133_14_14_14 0x21 +#define PROFILE_DDR4_1333_10_10_10 0x22 +#define PROFILE_DDR4_1600_10_10_10 0x23 +#define PROFILE_DDR4_1600_11_11_11 0x24 +#define PROFILE_DDR4_1600_12_12_12 0x25 +#define PROFILE_DDR4_1866_12_12_12 0x26 +#define PROFILE_DDR4_1866_13_13_13 0x27 +#define PROFILE_DDR4_1866_14_14_14 0x28 +#define PROFILE_DDR4_2133_14_14_14 0x29 +#define PROFILE_DDR4_2133_15_15_15 0x2a +#define PROFILE_DDR4_2133_16_16_16 0x2b +#define PROFILE_DDR4_2400_15_15_15 0x2c +#define PROFILE_DDR4_2400_16_16_16 0x2d +#define PROFILE_DDR4_2400_17_17_17 0x2e +#define PROFILE_DDR4_2400_18_18_18 0x2f + +#define MEMORY_DOWN_NO 0 +#define MEMORY_DOWN_YES 1 +#define MEMORY_DOWN_MD_SODIMM 2 +#define MEMORY_DOWN_LPDDR4 3 + +#define INTERLEAVED_MODE_DISABLE 0 +#define INTERLEAVED_MODE_ENABLE 2 + +#define RMT_MODE_DISABLE 0 +#define RMT_MODE_ENABLE 3 + +#define CHX_DEVICE_WIDTH_X8 0 +#define CHX_DEVICE_WIDTH_X16 1 +#define CHX_DEVICE_WIDTH_X32 2 +#define CHX_DEVICE_WIDTH_X64 3 + +#define CHX_DEVICE_DENSITY_4GB 0 +#define CHX_DEVICE_DENSITY_6GB 1 +#define CHX_DEVICE_DENSITY_8GB 2 +#define CHX_DEVICE_DENSITY_12GB 3 +#define CHX_DEVICE_DENSITY_16GB 4 +#define CHX_DEVICE_DENSITY_2GB 5 + +#define CHX_OPTION_RANK_INTERLEAVING 0x1 +#define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2 +#define CHX_OPTION_CH1_CLK_DISABLE 0x4 +#define CHX_OPTION_ADDRESS_MAP_2KB 0x10 + +#define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1 +#define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2 +#define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10 + +#define CHX_MODE2N_AUTO 0 +#define CHX_MODE2N_FORCE 1 + +#define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0 +#define CHX_ODT_LEVELS_HELD_HIGH 0x1 + +#define NPK_EN_DISABLE 0 +#define NPK_EN_ENABLE 1 +#define NPK_EN_DEBUGGER 2 +#define NPK_EN_AUTO 3 + +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1 +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2 +#define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3 +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4 + +#define MSC_X_WRAP_0 0 +#define MSC_X_WRAP_1 1 + +#define MSC_X_SIZE_0M 0 +#define MSC_X_SIZE_1M 1 +#define MSC_X_SIZE_8M 2 +#define MSC_X_SIZE_64M 3 +#define MSC_X_SIZE_128M 4 +#define MSC_X_SIZE_256M 5 +#define MSC_X_SIZE_512M 6 +#define MSC_X_SIZE_1GB 7 + +#define PTI_MODE_0 0 +#define PTI_MODE_x4 1 +#define PTI_MODE_x8 2 +#define PTI_MODE_x12 3 +#define PTI_MODE_x16 4 + +#define PTI_SPEED_FULL 0 +#define PTI_SPEED_HALF 1 +#define PTI_SPEED_QUARTER 2 #endif diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt new file mode 100644 index 0000000000..a6683c387f --- /dev/null +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt @@ -0,0 +1,312 @@ +* Intel FSP-M configuration + +This configuration applies to the FSP-M for the Intel Apollo Lake SoC. +The FSP-M can be found on https://github.com/IntelFsp/FSP. +For detailed information see FSP/ApolloLakeFspBinPkg/Docs. +If no configuration parameters are set the default FSP-M configuration is set. +For example Memory Fast Boot is an enable option in the FSP which is enabled by +default, so the configuration option is named fspm,disable-mrc-fast-boot. + +Required properties: +- fspm,package: Specifies CA Mapping for all technologies + 0x0: SODIMM (default) + 0x1: BGA + 0x2: BGA mirrored (LPDDR3 only) + 0x3: SODIMM/UDIMM with Rank 1 Mirrored (DDR3L) +- fspm,profile: Profile list + 0x01: WIO2_800_7_8_8 + 0x02: WIO2_1066_9_10_10 + 0x03: LPDDR3_1066_8_10_10 + 0x04: LPDDR3_1333_10_12_12 + 0x05: LPDDR3_1600_12_15_15 + 0x06: LPDDR3_1866_14_17_17 + 0x07: LPDDR3_2133_16_20_20 + 0x08: LPDDR4_1066_10_10_10 + 0x09: LPDDR4_1600_14_15_15 + 0x0A: LPDDR4_2133_20_20_20 + 0x0B: LPDDR4_2400_24_22_22 + 0x0C: LPDDR4_2666_24_24_24 + 0x0D: LPDDR4_2933_28_27_27 + 0x0E: LPDDR4_3200_28_29_29 + 0x0F: DDR3_1066_6_6_6 + 0x10: DDR3_1066_7_7_7 + 0x11: DDR3_1066_8_8_8 + 0x12: DDR3_1333_7_7_7 + 0x13: DDR3_1333_8_8_8 + 0x14: DDR3_1333_9_9_9 + 0x15: DDR3_1333_10_10_10 + 0x16: DDR3_1600_8_8_8 + 0x17: DDR3_1600_9_9_9 + 0x18: DDR3_1600_10_10_10 + 0x19: DDR3_1600_11_11_11 (default) + 0x1A: DDR3_1866_10_10_10 + 0x1B: DDR3_1866_11_11_11 + 0x1C: DDR3_1866_12_12_12 + 0x1D: DDR3_1866_13_13_13 + 0x1E: DDR3_2133_11_11_11 + 0x1F: DDR3_2133_12_12_12 + 0x20: DDR3_2133_13_13_13 + 0x21: DDR3_2133_14_14_14 + 0x22: DDR4_1333_10_10_10 + 0x23: DDR4_1600_10_10_10 + 0x24: DDR4_1600_11_11_11 + 0x25: DDR4_1600_12_12_12 + 0x26: DDR4_1866_12_12_12 + 0x27: DDR4_1866_13_13_13 + 0x28: DDR4_1866_14_14_14 + 0x29: DDR4_2133_14_14_14 + 0x2A: DDR4_2133_15_15_15 + 0x2B: DDR4_2133_16_16_16 + 0x2C: DDR4_2400_15_15_15 + 0x2D: DDR4_2400_16_16_16 + 0x2E: DDR4_2400_17_17_17 + 0x2F: DDR4_2400_18_18_18 +- fspm,memory-down: + 0x0: No (default) + 0x1: Yes + 0x2: 1MD+SODIMM (for DDR3L only) ACRD + 0x3: 1x32 LPDDR4 + +Optional properties: +- fspm,serial-debug-port-address: Debug Serial Port Base Address +- fspm,serial-debug-port-type: Debug Serial Port Type + 0: NONE + 1: I/O + 2: MMIO (default) +- fspm,serial-debug-port-device: Serial Port Debug Device + 0: SOC UART0 + 1: SOC UART1 + 2: SOC UART2 (default) + 3: External Device +- fspm,serial-debug-port-stride-size: Debug Serial Port Stride Size + 0: 1 + 2: 4 (default) +- fspm,disable-mrc-fast-boot: Disable Memory Fast Boot +- fspm,disable-igd: Disable Integrated Graphics Device +- fspm,igd-dvmt50-pre-alloc: DVMT Pre-Allocated + 0x02: 64 MB (default) + 0x03: 96 MB + 0x04: 128 MB + 0x05: 160 MB + 0x06: 192 MB + 0x07: 224 MB + 0x08: 256 MB + 0x09: 288 MB + 0x0A: 320 MB + 0x0B: 352 MB + 0x0C: 384 MB + 0x0D: 416 MB + 0x0E: 448 MB + 0x0F: 480 MB + 0x10: 512 MB +- fspm,aperture-size: Aperture Size + 0x1: 128 MB (default) + 0x2: 256 MB + 0x3: 512 MB +- fspm,gtt-size: GTT Size + 0x1: 2 MB + 0x2: 4 MB + 0x3: 8 MB (default) +- fspm,primary-video-adaptor: Primary Display + 0x0: AUTO (default) + 0x2: IGD + 0x3: PCI +- fspm,ddr3l-page-size: DDR3LPageSize + 0x1: 1KB (default) + 0x2: 2KB +- fspm,enable-ddr3-lasr: Enable DDR3LASR +- fspm,enable-scrambler-support: Enable ScramblerSupport +- fspm,enable-interleaved-mode: Enable InterleavedMode +- fspm,channel-hash-mask: ChannelHashMask +- fspm,fspm,slice-hash-mask: SliceHashMask +- fspm,enable-channels-slices: Enable ChannelsSlices +- fspm,enable-min-ref-rate2x: Enable MinRefRate2x +- fspm,disable-dual-rank-support: Enable DualRankSupport +- fspm,enable-rmt-mode: Enable RmtMode +- fspm,memory-size-limit: MemorySizeLimit +- fspm,low-memory-max-value: LowMemoryMaxValue +- fspm,high-memory-max-value: HighMemoryMaxValue +- fspm,disable-fast-boot: Disable FastBoot +- fspm,dimm0-spd-address: DIMM0 SPD Address +- fspm,dimm1-spd-address: DIMM1 SPD Address +- fspm,chX-enable-rank: Must be set to enable rank (X = 0-3) +- fspm,chX-device-width: DRAM device width per DRAM channel (X = 0-3) + 0: x8 + 1: x16 + 2: x32 + 3: x64 +- fspm,chX-dram-density: Must specify the DRAM device density (X = 0-3) + 0: 4Gb + 1: 6Gb + 2: 8Gb + 3: 12Gb + 4: 16Gb + 5: 2Gb +- fspm,chX-option: Channel options (X = 0-3) +- fspm,chX-odt-config: Channel Odt Config (X = 0-3) +- fspm,chX-force-mode2-n: Force 2N Mode (X = 0-3) + 0x0: Auto + 0x1: Force 2N CMD Timing Mode +- fspm,chX-odt-levels: Channel Odt Levels (X = 0-3) + 0: ODT Connected to SoC + 1: ODT held high +- fspm,rmt-degrade-margin-check: Enable RMT degrade margin check +- fspm,rmt-margin-check-scale-high-threshold: Percentage used to determine the + margin tolerances +- lpddr4-swizzle: Channels PHY to DUnit DQ mapping +- fspm,msg-level-mask: Mask out debug messages +- fspm,pre-mem-gpio-table-pin-num: PreMem GPIO Pin Number for each table +- fspm,pre-mem-gpio-table-ptr: PreMem GPIO Table Pointer +- fspm,pre-mem-gpio-table-entry-num: PreMem GPIO Table Entry Number +- fspm,disable-enhance-port8xh-decoding: Disable Enhance the port 8xh decoding +- fspm,enable-spd-write: MRC Training Data Saving +- fspm,oem-loading-base: OEM File Loading Address +- fspm,oem-file-name: OEM File Name to Load +- fspm,mrc-data-saving-ptr: +- fspm,emmc-trace-len-short: Select eMMC trace length to load OEM file short +- fspm,enable-skip-cse-rbp: Skip CSE RBP to support zero sized IBB +- fspm,enable-npk: + 0: Disable + 1: Enable + 2: Debugger + 3: Auto (default) +- fspm,disable-fw-trace: Disable FW Trace +- fspm,fw-trace-destination: FW Trace Destination + 1: NPK_TRACE_TO_MEMORY + 2: NPK_TRACE_TO_DCI + 3: NPK_TRACE_TO_BSSB + 4: NPK_TRACE_TO_PTI (default) +- fspm,enable-recover-dump: NPK Recovery Dump +- fspm,msc0-wrap: Memory Region 0 Buffer WrapAround + 0: n0-warp + 1: n1-warp (default) +- fspm,msc1-wrap: Memory Region 0 Buffer WrapAround + 0: n0-warp + 1: n1-warp (default) +- fspm,msc0-size: Memory Region 0 Buffer Size + 0: 0MB (default) + 1: 1MB + 2: 8MB + 3: 64MB + 4: 128MB + 5: 256MB + 6: 512MB + 7: 1GB +- fspm,msc1-size: Memory Region 0 Buffer Size + 0: 0MB (default) + 1: 1MB + 2: 8MB + 3: 64MB + 4: 128MB + 5: 256MB + 6: 512MB + 7: 1GB +- fspm,pti-mode: PTI Mode + 0: 0ff + 1: x4 (default) + 2: x8 + 3: x12 + 4: x16 +- fspm,pti-training: PTI Training + 0: off (default) + 1-6: 1-6 +- fspm,pti-speed: + 0: full + 1: half + 2: quarter (default) +- fspm,punit-mlvl: Punit Message Level + 0: + 1: (default) + 2-4: 2-4 +- fspm,pmc-mlvl: Punit Message Level + 0: + 1: (default) + 2-4: 2-4 +- fspm,enable-sw-trace: Enable SW Trace +- fspm,disable-periodic-retraining: Disable Periodic Retraining +- fspm,enable-reset-system: Enable Reset System +- fspm,disable-s3-heci2: Enable HECI2 in S3 resume path + +Example: + +&host_bridge { + fspm,package = <PACKAGE_BGA>; + fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; + fspm,memory-down = <MEMORY_DOWN_YES>; + fspm,enable-scrambler-support; + fspm,enable-interleaved-mode; + fspm,channel-hash-mask = <0x36>; + fspm,slice-hash-mask = <0x9>; + fspm,low-memory-max-value = <2048>; + fspm,ch0-enable-rank; + fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch1-enable-rank; + fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch2-enable-rank; + fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch3-enable-rank; + fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,enable-skip-cse-rbp; + + lpddr4-swizzle = /bits/ 8 < + /* LP4_PHYS_CH0A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 6 7 5 4 3 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 12 10 11 13 14 8 9 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 16 22 23 20 18 17 19 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 30 28 29 25 24 26 27 31 + + /* LP4_PHYS_CH0B */ + /* DQA[0:7] pins of LPDDR4 module */ + 7 3 5 2 6 0 1 4 + /* DQA[8:15] pins of LPDDR4 module */ + 9 14 12 13 10 11 8 15 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 22 23 16 19 17 18 21 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 28 24 26 27 29 30 31 25 + + /* LP4_PHYS_CH1A */ + + /* DQA[0:7] pins of LPDDR4 module */ + 2 1 6 7 5 4 3 0 + /* DQA[8:15] pins of LPDDR4 module */ + 11 10 8 9 12 15 13 14 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 17 23 19 16 21 22 20 18 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 31 29 26 25 28 27 24 30 + + /* LP4_PHYS_CH1B */ + + /* DQA[0:7] pins of LPDDR4 module */ + 4 3 7 5 6 1 0 2 + /* DQA[8:15] pins of LPDDR4 module */ + 15 9 8 11 14 13 12 10 + /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ + 20 23 22 21 18 19 16 17 + /* DQB[7:15] pins of LPDDR4 module with offset of 16 */ + 25 28 30 31 26 27 24 29>; +}; + + -- 2.25.1

2 2

[RFC PATCH v2 0/2] Move FSP-S configuration to device-tree
by Bernhard Messerklinger 30 Apr '20

30 Apr '20

This patch series moves the configuration of FPS-S for Apollo Lake based SoCs from the code to the device-tree. This is similar to the previous patch series for FSP-M. If wanted, I can also send FSP-M and FSP-S patch as a single series. Changes in v2: Remove FSP-M binding file Bernhard Messerklinger (2): arch: x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled arch: x86: apl: Read FSP-S configuration from device-tree arch/x86/cpu/apollolake/fsp_s.c | 1084 +++++++++++------ arch/x86/dts/chromebook_coral.dts | 35 +- .../asm/arch-apollolake/fsp/fsp_s_upd.h | 268 ++++ .../fsp/fsp2/apollolake/fsp-s.txt | 485 ++++++++ 4 files changed, 1497 insertions(+), 375 deletions(-) create mode 100644 doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt -- 2.26.0

2 9

[PATCH v2 0/5] cmd: bind allow to bind driver with driver_data
by Patrice Chotard 30 Apr '20

30 Apr '20

- fix the bind command - add a bind command test - add bind command documentation Changes in v2: - add a bind command test - add bind command documentation in doc/driver/model/bind.rst - simplify patch 1 by using lists_bind_fdt() Patrice Chotard (5): cmd: bind: allow to bind driver with driver data sandbox: phy: add driver_data for bind test cmd sandbox: dts: Add compatible string for bind-test node test/py: Update test_bind doc: add bind/unbind command documentation arch/sandbox/dts/test.dts | 1 + cmd/bind.c | 5 +++-- doc/driver-model/bind.rst | 32 ++++++++++++++++++++++++++++++++ doc/driver-model/index.rst | 1 + drivers/phy/sandbox-phy.c | 18 +++++++++++++++++- test/py/tests/test_bind.py | 18 +++++++++--------- 6 files changed, 63 insertions(+), 12 deletions(-) create mode 100644 doc/driver-model/bind.rst -- 2.17.1

3 12

[PATCH] ARM: zynq: Fix invalid check on NAND_CMD_NONE.
by Michal Simek 30 Apr '20

30 Apr '20

From: Patrick van Gelder <patrick.vangelder(a)nl.bosch.com> The end_cmd field in the variables cmd_phase_addr and data_phase_addr contains the value 0xFF when the end_cmd equals NAND_CMD_NONE. This should be 0x00. This is caused by comparing NAND_CMD_NONE (int) with end_cmd (u8). end_cmd will be promoted by the int value -1 and therefore is not equal to 0xFF. Solved by casting NAND_CMD_NONE to u8 which will avoid int promotion. Signed-off-by: Patrick van Gelder <patrick.vangelder(a)nl.bosch.com> Reviewed-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/mtd/nand/raw/zynq_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 0aea83dac0e6..394129741831 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -845,7 +845,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) end_cmd_valid = 1; - if (curr_cmd->end_cmd == NAND_CMD_NONE) + if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE) end_cmd = 0x0; else end_cmd = curr_cmd->end_cmd; -- 2.26.2

2 1

[PATCH] xilinx: Make Xilinx custom distro boot commands more verbose
by Michal Simek 30 Apr '20

30 Apr '20

Extend description of Xilinx custom boot commands to make clear what runs and what failed. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_versal.h | 12 ++++++++---- include/configs/xilinx_zynqmp.h | 9 ++++++--- include/configs/zynq-common.h | 12 ++++++++---- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index dec5001b5fe4..0c259a181f10 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -109,7 +109,8 @@ #define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ "bootcmd_xspi0=sf probe 0 0 0 && " \ "sf read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo XSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ "xspi " @@ -117,7 +118,8 @@ #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " @@ -126,8 +128,10 @@ #define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \ - "$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \ - "echo SCRIPT FAILED: continuing...;\0" + "$script_size_f; dfu 0 ram 0 && " \ + "echo DFU: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo DFU: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ "dfu_usb " diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 010738363d13..eddc2b402006 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -160,7 +160,8 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \ "sf read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -168,7 +169,8 @@ #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "= nand info && " \ "nand read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -176,7 +178,8 @@ #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 4ccc31e37655..a93172b02cd6 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -152,7 +152,8 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=sf probe 0 0 0 && " \ "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo QSPI: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ "qspi " @@ -160,7 +161,8 @@ #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ "bootcmd_nand=nand info && " \ "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NAND: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ "nand " @@ -168,7 +170,8 @@ #define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ "script_offset_nor=0xE2FC0000\0" \ "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" + "echo NOR: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo NOR: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ "nor " @@ -176,7 +179,8 @@ #define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) #define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" #define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ "jtag " -- 2.26.0

2 1

[PATCH] ARM: zynq: Change SYS_MALLOC_LEN in zynq_cse_nand_defconfig
by Michal Simek 30 Apr '20

30 Apr '20

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> nand_scan_tail() function allocates memory dynamically for struct nand_buffers which needs ~21kbytes of memory. But the memory alloted with CONFIG_SYS_MALLOC_LEN is 4k which is insufficient. Increase CONFIG_SYS_MALLOC_LEN to 32Kbytes from which struct nand_buffers uses ~21kbytes & remaining memory is used for other. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/zynq_cse_nand_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 2b58c461c390..80a427d905d3 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x100000 -CONFIG_SYS_MALLOC_LEN=0x1000 +CONFIG_SYS_MALLOC_LEN=0x8000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y -- 2.26.0

2 1