February 2020 - U-Boot

[PATCH 0/3] clk: Fix ETH initialization on i.MX6Q boards using CCF
by Lukasz Majewski 24 Feb '20

24 Feb '20

This short patch series fixes boards, which after the commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") were required to support in CCF 'ipg' (i.e. IMX6QDL_CLK_ENET) and 'ptp' (i.e. IMX6QDL_CLK_ENET_REF) clocks during ETH initialization. Lack of those clocks supported in CCF resulted in non-functional ETH. Lukasz Majewski (3): clk: imx6: Add definition for IMX6QDL_CLK_ENET clock clk: imx: Add support for pllv3 enet clock clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock drivers/clk/imx/clk-imx6q.c | 8 ++++++++ drivers/clk/imx/clk-pllv3.c | 25 +++++++++++++++++++++++++ 2 files changed, 33 insertions(+) -- 2.20.1

1 3

[PATCH v1 0/2] display proper CPU frequency on hifive-unleashed
by Sagar Shrikant Kadam 24 Feb '20

24 Feb '20

U-Boot cmd "cpu detail" shows wrong values, as the current cpu driver is fetching cpu_freq by reading the dt node property "clock-frequency". There should be a fallback mechanism to handle a case where this property if not present in DT it should be read from the prci driver. This patch series uses the clk_get_rate method to fetch proper core clock frequency. The series is based on U-Boot commit f2a73d6867ef ("Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm") Thanks to Vincent Chen <vincent.chen(a)sifive.com> for testing this patch. =>-----------------------Log for reference------------------------ => cpu detail 0: cpu@1 rv64imafdc ID = 1, freq = 4.30 GHz <= Before patch 1: cpu@2 rv64imafdc ID = 2, freq = 4.30 GHz 2: cpu@3 rv64imafdc ID = 3, freq = 4.30 GHz 3: cpu@4 rv64imafdc ID = 4, freq = 4.30 GHz ................................................................. => cpu detail 0: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz <= After patch 1: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz 2: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz 3: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz Sagar Shrikant Kadam (2): fu540: prci: add request and free clock handlers cpu: clk: riscv: populate proper CPU core clk frequency drivers/clk/sifive/fu540-prci.c | 24 ++++++++++++++++++++++++ drivers/cpu/riscv_cpu.c | 39 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) -- 2.7.4

4 8

[PATCH] arm: imx6: configure NoC on i.MX6DQP
by Bernhard Messerklinger 24 Feb '20

24 Feb '20

The i.MX6DP and i.MX6QP incorporate NoC interconnect logic which needs to be configured in order to use external DDR memory. This patch enables the SPL to configure the necessary registers in accordance with the NXP engineering bulletin EB828. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger(a)br-automation.com> --- This patch is a revised version of the patch "arm: imx6: configure NoC on i.MX6DQP" from the original author Filip Brozovic <fbrozovic(a)gmail.com>. It takes care of the review notes for the original patch. patchwork: https://patchwork.ozlabs.org/patch/670208/ mail-archive: https://lists.denx.de/pipermail/u-boot/2016-September/266667.html I'm not sure how to handle a patch which is based on a patch from another author. Guidance from the maintainers regarding this question would be welcome. My assumption would be that this can be solved by adding "Co-Developed-by:" and "Signed-off-by:" lines to this patch for Filip Brozovic (see [1] for a discussion of this topic on LKML). Filip, would this be ok for you? arch/arm/include/asm/arch-mx6/mx6-ddr.h | 19 +++++ arch/arm/mach-imx/mx6/ddr.c | 96 +++++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 19d2f1d9c5..25168c9865 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -307,6 +307,25 @@ struct mx6dq_iomux_grp_regs { u32 grp_b6ds; }; +/* + * NoC scheduler registers - only on IMX6DQP + */ +#define MX6DQP_NOC_SCHED_BASE 0x00bb0000 +struct mx6dqp_noc_sched_regs { + u32 coreid; + u32 revid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 rlat; + u32 res1[4]; + u32 ipu1; + u32 ipu2; + u32 res2[2]; + u32 activate; + u32 res3[16]; +}; + #define MX6SDL_IOM_DDR_BASE 0x020e0400 struct mx6sdl_iomux_ddr_regs { u32 res1[25]; diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 6e5e40dd1a..3521d8eac7 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -936,6 +936,27 @@ void mx6sdl_dram_iocfg(unsigned width, mmdc1->entry = value; \ } while (0) +/* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */ +#define BOOT_CFG3_DDR_MASK 0x30 +#define BOOT_CFG3_EXT_DDR_MASK 0x33 + +#define DDR_MMAP_NOC_SINGLE 0 +#define DDR_MMAP_NOC_DUAL 0x31 + +/* NoC ACTIVATE shifts */ +#define NOC_RD_SHIFT 0 +#define NOC_FAW_PERIOD_SHIFT 4 +#define NOC_FAW_BANKS_SHIFT 10 + +/* NoC DdrTiming shifts */ +#define NOC_ACT_TO_ACT_SHIFT 0 +#define NOC_RD_TO_MISS_SHIFT 6 +#define NOC_WR_TO_MISS_SHIFT 12 +#define NOC_BURST_LEN_SHIFT 18 +#define NOC_RD_TO_WR_SHIFT 21 +#define NOC_WR_TO_RD_SHIFT 26 +#define NOC_BW_RATIO_SHIFT 31 + /* * According JESD209-2B-LPDDR2: Table 103 * WL: write latency @@ -1225,6 +1246,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, { volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff; u32 val; u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; @@ -1517,6 +1540,79 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* Step 12: Configure and activate periodic refresh */ mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); + /* + * Step 13: i.MX6DQP only: If the NoC scheduler is enabled, + * configure it and disable MMDC arbitration/reordering (see EB828) + */ + if (is_mx6dqp() && + ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE || + (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) { + struct mx6dqp_noc_sched_regs *noc_sched = + (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE; + + /* + * These values are fixed based on integration parameters and + * should not be modified + */ + noc_sched->rlat = 0x00000040; + noc_sched->ipu1 = 0x00000020; + noc_sched->ipu2 = 0x00000020; + + noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) | + (tfaw << NOC_FAW_PERIOD_SHIFT) | + (trrd << NOC_RD_SHIFT); + noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0) + << NOC_BW_RATIO_SHIFT) | + ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) | + ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) | + (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */ + ((tcwl + twr + trp + trcd) + << NOC_WR_TO_MISS_SHIFT) | + ((trtp + trp + trcd - 4) + << NOC_RD_TO_MISS_SHIFT) | + (trc << NOC_ACT_TO_ACT_SHIFT); + + if (sysinfo->dsize == 2) { + if (ddr3_cfg->coladdr == 10) { + if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 4; + else + noc_sched->ddrconf = 0; + } else if (ddr3_cfg->coladdr == 11) { + noc_sched->ddrconf = 1; + } + } else { + if (ddr3_cfg->coladdr == 9) { + if (ddr3_cfg->rowaddr == 13) + noc_sched->ddrconf = 2; + else if (ddr3_cfg->rowaddr == 14) + noc_sched->ddrconf = 15; + } else if (ddr3_cfg->coladdr == 10) { + if (ddr3_cfg->rowaddr == 14 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 14; + else if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 9; + else + noc_sched->ddrconf = 3; + } else if (ddr3_cfg->coladdr == 11) { + if (ddr3_cfg->rowaddr == 15 && + sysinfo->ncs == 2) + noc_sched->ddrconf = 4; + else + noc_sched->ddrconf = 0; + } else if (ddr3_cfg->coladdr == 12) { + if (ddr3_cfg->rowaddr == 14) + noc_sched->ddrconf = 1; + } + } + + /* Disable MMDC arbitration/reordering */ + mmdc0->maarcr = 0x14420000; + } + /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; -- 2.25.1

1 0

[U-Boot] [PATCH 1/4 v4] watchdog: Implement generic watchdog_reset() version
by Stefan Roese 23 Feb '20

23 Feb '20

This patch tries to implement a generic watchdog_reset() function that can be used by all boards that want to service the watchdog device in U-Boot. This watchdog servicing is enabled via CONFIG_WATCHDOG. Without this approach, new boards or platforms needed to implement a board specific version of this functionality, mostly copy'ing the same code over and over again into their board or platforms code base. With this new generic function, the scattered other functions are now removed to be replaced by the generic one. The new version also enables the configuration of the watchdog timeout via the DT "timeout-sec" property (if enabled via CONFIG_OF_CONTROL). This patch also adds a new flag to the GD flags, to flag that the watchdog is ready to use and adds the pointer to the watchdog device to the GD. This enables us to remove the global "watchdog_dev" variable, which was prone to cause problems because of its potentially very early use in watchdog_reset(), even before the BSS is cleared. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: "Marek Behún" <marek.behun(a)nic.cz> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Maxim Sloyko <maxims(a)google.com> Cc: Erik van Luijk <evanluijk(a)interact.nl> Cc: Ryder Lee <ryder.lee(a)mediatek.com> Cc: Weijie Gao <weijie.gao(a)mediatek.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: "Álvaro Fernández Rojas" <noltari(a)gmail.com> Cc: Philippe Reynes <philippe.reynes(a)softathome.com> Cc: Christophe Leroy <christophe.leroy(a)c-s.fr> --- This patch depends on the following patch: [1] watchdog: Handle SPL build with watchdog disabled https://patchwork.ozlabs.org/patch/1074098/ We have a few boards that have CONFIG_WDT (DM watchdog driver) enabled and CONFIG_WATCHDOG (U-Boot watchdog servicing) disabled. This might lead to a watchdog reboot, if the board does not boot fast enough into some OS (like Linux) which services the watchdog. With this patch now, the watchdog is started on all those boards (if found via the DT) and also serviced as this patch also "implies" CONFIG_WATCHDOG. If this is not desired, then please send a patch to disable CONFIG_WATCHDOG for this board. Here the list of those boards with their maintainers: taurus: Heiko Schocher <hs(a)denx.de> smartweb: Heiko Schocher <hs(a)denx.de> ast2500: Maxim Sloyko <maxims(a)google.com> picosam9g45: Erik van Luijk <evanluijk(a)interact.nl> mt7623n_bpir2: Ryder Lee <ryder.lee(a)mediatek.com> Weijie Gao <weijie.gao(a)mediatek.com> mt7629_rfb: Ryder Lee <ryder.lee(a)mediatek.com> Weijie Gao <weijie.gao(a)mediatek.com> bitmain_antminer_s9: Michal Simek <monstr(a)monstr.eu> sandbox64: Simon Glass <sjg(a)chromium.org> sandbox: Simon Glass <sjg(a)chromium.org> comtrend_ct5361_ram: "Álvaro Fernández Rojas" <noltari(a)gmail.com> netgear_cg3100d_ram: "Álvaro Fernández Rojas" <noltari(a)gmail.com> bcm968380gerg_ram: Philippe Reynes <philippe.reynes(a)softathome.com> bcm963158_ram: Philippe Reynes <philippe.reynes(a)softathome.com> bcm968580xref_ram: Philippe Reynes <philippe.reynes(a)softathome.com> MCR3000: Christophe Leroy <christophe.leroy(a)c-s.fr> Thanks, Stefan v4: - No change v3: - Use already available CONFIG_WATCHDOG_TIMEOUT_MSECS option vs the newly introduced WDT_DEFAULT_TIMEOUT default timeout value (if not provided via DT property). - Guard initr_watchdog by CONFIG_WDT instead of CONFIG_WATCHDOG && CONFIG_WDT as suggested by Michal. This makes it possible to enable and start the U-Boot watchdog without enabling the U-Boot watchdog servicing. - Add imply CONFIG_WATCHDOG to CONFIG_WDT, as this restores the current behaviour to use the U-Boot watchdog servicing feature, if the DM watchdog is enabled (CONFIG_WDT). If this is not desired, CONFIG_WATCHDOG can be disabled in the board defconfig. - Remove CONFIG_WATCHDOG from include/configs/turris_omnia.h v2: - Rename watchdog_start() to initr_watchdog() and move it to board_r.c. This way its only called once, after the DM subsystem has bound all watchdog drivers. This enables the use of the currently implemented logic of using the correct watchdog in U-Boot (via alias etc). arch/mips/mach-mt7620/cpu.c | 36 ---------------- board/CZ.NIC/turris_mox/turris_mox.c | 30 -------------- board/CZ.NIC/turris_omnia/turris_omnia.c | 35 ---------------- .../microblaze-generic/microblaze-generic.c | 40 ------------------ board/xilinx/zynq/board.c | 39 ------------------ board/xilinx/zynqmp/zynqmp.c | 39 ------------------ common/board_r.c | 41 +++++++++++++++++++ drivers/watchdog/Kconfig | 1 + drivers/watchdog/wdt-uclass.c | 26 ++++++++++++ include/asm-generic/global_data.h | 4 ++ include/configs/turris_omnia.h | 5 --- 11 files changed, 72 insertions(+), 224 deletions(-) diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c index fe74f26a54..fcd0484a6d 100644 --- a/arch/mips/mach-mt7620/cpu.c +++ b/arch/mips/mach-mt7620/cpu.c @@ -69,28 +69,6 @@ int print_cpuinfo(void) return 0; } -#ifdef CONFIG_WATCHDOG -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; - -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ - static ulong next_reset; - ulong now; - - if (!watchdog_dev) - return; - - now = get_timer(0); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - next_reset = now + 1000; /* reset every 1000ms */ - wdt_reset(watchdog_dev); - } -} -#endif - int arch_misc_init(void) { /* @@ -103,19 +81,5 @@ int arch_misc_init(void) flush_dcache_range(gd->bd->bi_memstart, gd->bd->bi_memstart + gd->ram_size - 1); -#ifdef CONFIG_WATCHDOG - /* Init watchdog */ - if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { - debug("Watchdog: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Watchdog: Not found!\n"); - return 0; - } - } - - wdt_start(watchdog_dev, 60000, 0); /* 60 seconds */ - printf("Watchdog: Started\n"); -#endif - return 0; } diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 96cb9c7e5c..8a4872343b 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -119,41 +119,11 @@ int board_fix_fdt(void *blob) } #endif -#ifdef CONFIG_WDT_ARMADA_37XX -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; - -void watchdog_reset(void) -{ - static ulong next_reset; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 100000; - } -} -#endif - int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_WDT_ARMADA_37XX - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - printf("Cannot find Armada 3720 watchdog!\n"); - } else { - printf("Enabling Armada 3720 watchdog (3 minutes timeout).\n"); - wdt_start(watchdog_dev, 180000, 0); - } -#endif - return 0; } diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index c7f6479a0c..8101cfd88a 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -364,25 +364,12 @@ static bool disable_mcu_watchdog(void) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif - int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; #ifndef CONFIG_SPL_BUILD -# ifdef CONFIG_WDT_ORION - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Cannot find Armada 385 watchdog!\n"); - } else { - puts("Enabling Armada 385 watchdog.\n"); - wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); - } -# endif - if (disable_mcu_watchdog()) puts("Disabled MCU startup watchdog.\n"); @@ -392,28 +379,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_WATCHDOG -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -# if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) - static ulong next_reset = 0; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -# endif -} -#endif - int board_late_init(void) { #ifndef CONFIG_SPL_BUILD diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 28c9efa3a2..ba82292e35 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */ - ulong ram_base; int dram_init_banksize(void) @@ -43,44 +39,8 @@ int dram_init(void) return 0; }; -#ifdef CONFIG_WDT -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -#if !defined(CONFIG_SPL_BUILD) - ulong now; - static ulong next_reset; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -#endif /* !CONFIG_SPL_BUILD */ -} -#endif /* CONFIG_WDT */ - int board_late_init(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) - watchdog_dev = NULL; - - if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { - debug("Watchdog: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Watchdog: Not found!\n"); - return 0; - } - } - - wdt_start(watchdog_dev, 0, 0); - puts("Watchdog: Started\n"); -#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */ #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE) int ret; diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index ea26aad16f..6857f2c0b8 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -18,10 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { @@ -31,19 +27,6 @@ int board_early_init_f(void) int board_init(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) - if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { - debug("Watchdog: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Watchdog: Not found!\n"); - return 0; - } - } - - wdt_start(watchdog_dev, 0, 0); - puts("Watchdog: Started\n"); -# endif - return 0; } @@ -127,25 +110,3 @@ int dram_init(void) return 0; } #endif - -#if defined(CONFIG_WATCHDOG) -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -# if !defined(CONFIG_SPL_BUILD) - static ulong next_reset; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -# endif -} -#endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index db27247850..1c12891b82 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif - #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ !defined(CONFIG_SPL_BUILD) static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; @@ -340,44 +336,9 @@ int board_init(void) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) - if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { - debug("Watchdog: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Watchdog: Not found!\n"); - return 0; - } - } - - wdt_start(watchdog_dev, 0, 0); - puts("Watchdog: Started\n"); -#endif - return 0; } -#ifdef CONFIG_WATCHDOG -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -# if !defined(CONFIG_SPL_BUILD) - static ulong next_reset; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -# endif -} -#endif - int board_early_init_r(void) { u32 val; diff --git a/common/board_r.c b/common/board_r.c index 472987d5d5..d457b6715f 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -48,6 +48,7 @@ #include <linux/compiler.h> #include <linux/err.h> #include <efi_loader.h> +#include <wdt.h> DECLARE_GLOBAL_DATA_PTR; @@ -621,6 +622,43 @@ static int initr_bedbug(void) } #endif +#if defined(CONFIG_WDT) +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define CONFIG_WATCHDOG_TIMEOUT_MSECS (60 * 1000) +#endif +#define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) + +static int initr_watchdog(void) +{ + u32 timeout = WATCHDOG_TIMEOUT_SECS; + + /* + * Init watchdog: This will call the probe function of the + * watchdog driver, enabling the use of the device + */ + if (uclass_get_device_by_seq(UCLASS_WDT, 0, + (struct udevice **)&gd->watchdog_dev)) { + debug("WDT: Not found by seq!\n"); + if (uclass_get_device(UCLASS_WDT, 0, + (struct udevice **)&gd->watchdog_dev)) { + printf("WDT: Not found!\n"); + return 0; + } + } + + if (CONFIG_IS_ENABLED(OF_CONTROL)) { + timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec", + WATCHDOG_TIMEOUT_SECS); + } + + wdt_start(gd->watchdog_dev, timeout * 1000, 0); + gd->flags |= GD_FLG_WDT_READY; + printf("WDT: Started (%ds timeout)\n", timeout); + + return 0; +} +#endif + static int run_main_loop(void) { #ifdef CONFIG_SANDBOX @@ -670,6 +708,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_DM initr_dm, #endif +#if defined(CONFIG_WDT) + initr_watchdog, +#endif #if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \ defined(CONFIG_SANDBOX) board_init, /* Setup chipselects */ diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 34e78beb2a..82080d3867 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -51,6 +51,7 @@ config ULP_WATCHDOG config WDT bool "Enable driver model for watchdog timer drivers" depends on DM + imply WATCHDOG help Enable driver model for watchdog timer. At the moment the API is very simple and only supports four operations: diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 23b7e3360d..bbfac4f0f9 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -10,6 +10,8 @@ #include <dm/device-internal.h> #include <dm/lists.h> +DECLARE_GLOBAL_DATA_PTR; + int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { const struct wdt_ops *ops = device_get_ops(dev); @@ -63,6 +65,30 @@ int wdt_expire_now(struct udevice *dev, ulong flags) return ret; } +#if defined(CONFIG_WATCHDOG) +/* + * Called by macro WATCHDOG_RESET. This function be called *very* early, + * so we need to make sure, that the watchdog driver is ready before using + * it in this function. + */ +void watchdog_reset(void) +{ + static ulong next_reset; + ulong now; + + /* Exit if GD is not ready or watchdog is not initialized yet */ + if (!gd || !(gd->flags & GD_FLG_WDT_READY)) + return; + + /* Do not reset the watchdog too often */ + now = get_timer(0); + if (now > next_reset) { + next_reset = now + 1000; /* reset every 1000ms */ + wdt_reset(gd->watchdog_dev); + } +} +#endif + static int wdt_post_bind(struct udevice *dev) { #if defined(CONFIG_NEEDS_MANUAL_RELOC) diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 78dcf40bff..d16f50f677 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -133,6 +133,9 @@ typedef struct global_data { struct spl_handoff *spl_handoff; # endif #endif +#if defined(CONFIG_WDT) + struct udevice *watchdog_dev; +#endif } gd_t; #endif @@ -161,5 +164,6 @@ typedef struct global_data { #define GD_FLG_ENV_DEFAULT 0x02000 /* Default variable flag */ #define GD_FLG_SPL_EARLY_INIT 0x04000 /* Early SPL init is done */ #define GD_FLG_LOG_READY 0x08000 /* Log system is ready for use */ +#define GD_FLG_WDT_READY 0x10000 /* Watchdog is ready for use */ #endif /* __ASM_GENERIC_GBL_DATA_H */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 038f6398eb..78e3cf2ff4 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -29,11 +29,6 @@ #define CONFIG_SPL_I2C_MUX #define CONFIG_SYS_I2C_MVTWSI -/* Watchdog support */ -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) -# define CONFIG_WATCHDOG -#endif - /* SPI NOR flash default params, used by sf commands */ #define CONFIG_SPI_FLASH_SPANSION -- 2.21.0

3 9

[PATCH v3 00/13] Add DM/DTS support for omap video driver
by Dario Binacchi 23 Feb '20

23 Feb '20

Changes: - Fix coding style - Refactor some parts of the driver - Add support for driver model and device-tree - Update the boards device-tree - Add device-tree binding documentation Changes in v3: - Add panel to the root node so that the dts linux file of the board does not need to be updated. Changes in v2: - Use GENMASK macro too - Use GENMASK macro - Use GENMASK macro for clock divisor mask - Move clock enabling sequence to arch/arm/mach-omap2/ - Create a Kconfig symbol for CONFIG_AM335X_LCD - Change subject line in: arm: dts: am335x: - Move 'u-boot,dm-pre-reloc' property in *-u-boot.dtsi files for boards tha support Linux Dario Binacchi (13): video: omap: use BIT() and GENMASK() macros video: omap: add missing bitfield masks video: omap: fix coding style on use of spaces video: omap: fix bitfields order video: omap: rename LCD controller registers video: omap: fix debug message video: omap: add loop exit conditions to the dpll setup video: omap: create two routines to set the pixel clock rate video: omap: add support for DM/DTS arm: dts: am335x: add 'u-boot,dm-pre-reloc' to panel fdt: video: omap: add framebuffer and panel bindings video: omap: fix pixel-per-line bitfield setting board: brxre1: fix building errors arch/arm/dts/am335x-brppt1-mmc.dts | 2 + arch/arm/dts/am335x-brppt1-nand.dts | 2 + arch/arm/dts/am335x-brppt1-spi.dts | 2 + arch/arm/dts/am335x-brsmarc1.dts | 1 + arch/arm/dts/am335x-brxre1.dts | 2 + arch/arm/dts/am335x-evm-u-boot.dtsi | 6 + arch/arm/dts/am335x-evmsk-u-boot.dtsi | 12 + arch/arm/dts/am335x-guardian-u-boot.dtsi | 4 + arch/arm/dts/am335x-pdu001-u-boot.dtsi | 4 + arch/arm/dts/am335x-pxm50-u-boot.dtsi | 12 + arch/arm/dts/am335x-rut-u-boot.dtsi | 12 + arch/arm/dts/da850-evm-u-boot.dtsi | 4 + arch/arm/mach-omap2/am33xx/clock_am33xx.c | 4 + board/BuR/common/br_resetc.c | 2 +- board/BuR/common/bur_common.h | 3 + board/BuR/common/common.c | 2 +- .../video/tilcdc/panel.txt | 66 ++ .../video/tilcdc/tilcdc.txt | 82 +++ drivers/video/Kconfig | 6 + drivers/video/am335x-fb.c | 567 +++++++++++++++--- drivers/video/am335x-fb.h | 16 +- include/configs/brxre1.h | 2 + 22 files changed, 713 insertions(+), 100 deletions(-) create mode 100644 arch/arm/dts/am335x-evmsk-u-boot.dtsi create mode 100644 arch/arm/dts/am335x-pxm50-u-boot.dtsi create mode 100644 arch/arm/dts/am335x-rut-u-boot.dtsi create mode 100644 doc/device-tree-bindings/video/tilcdc/panel.txt create mode 100644 doc/device-tree-bindings/video/tilcdc/tilcdc.txt -- 2.17.1

3 15

[PATCH] arm: dts: k3-am654-base-board: Enable I2C nodes
by Vignesh Raghavendra 23 Feb '20

23 Feb '20

Add DT nodes for main domain I2Cs and its slave devices Signed-off-by: Vignesh Raghavendra <vigneshr(a)ti.com> --- arch/arm/dts/k3-am654-base-board.dts | 48 ++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index 375f1d089c7d..5058b6c88e96 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -64,6 +64,29 @@ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ + AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ + >; + }; +}; + +&main_pmx1 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ + AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ + AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ + >; + }; }; &wkup_pmx0 { @@ -112,6 +135,31 @@ }; }; +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; + &dwc3_1 { status = "okay"; }; -- 2.25.0

2 1

[PATCH v8 0/9] Add support for loading main_r5fss0_core0
by Keerthy 23 Feb '20

23 Feb '20

This patch series enables mcu_r5fss0_core0 & main_r5fss0_core0. Tested for firmware loading and execution on J721e. Changes in v8: * Dropped patch to set_env_default in the env/nowhere driver. That was causing memory over run issues on sandbox defconfig with simple_alloc. Instead used env_relocate in place of env_load which does default environment set up to do env_set calls. * Fixed IMX build warning. All the travis tests passed: https://travis-ci.org/Keerthyj/u-boot/builds/649274826 Changes in v7: * Added BSD-2 SPDX on lib/elf.c file. * Added Tom's Reviewed-by for the relevant patches. Changes in v6: * Fixed the imx build issue. Changes in v5: * Moved the fs_loader node under r5-common-proc-board-u-boot.dtsi * Added more information on the envnowhere patch. * Added help LIB_ELF option and removed user configurable description. Changes in v4: * Changed env variable names, config names and enhanced commit logs. Changes in v3: * Removed saving env in MMC and fixed env saving in SPL when nowhere option is set. Changes in v2: * Factored out all the generic elf handling functions under lib/elf.c Keerthy (9): lib: elf: Move the generic elf loading/validating functions to lib arm: k3: Add support for loading non linux remote cores armv7R: K3: r5_mpu: Enable execute permission for MCU0 BTCM armv7R: K3: Add support for jumping to firmware arm: dts: k3-j721e-r5-u-boot: Add fs_loader node arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL include: configs: j721e_evm: Add env variables for mcu_r5fss0_core0 & main_r5fss0_core0 configs: j721e_evm_r5: Enable R5F remoteproc support configs: j721e_evm_r5_defconfig: Remove saving ENV in eMMC .../k3-j721e-r5-common-proc-board-u-boot.dtsi | 27 ++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 2 + arch/arm/mach-imx/imx_bootaux.c | 64 ----- arch/arm/mach-k3/common.c | 106 +++++++- arch/arm/mach-k3/common.h | 2 + arch/arm/mach-k3/j721e_init.c | 34 +++ arch/arm/mach-k3/r5_mpu.c | 4 +- cmd/Kconfig | 1 + cmd/elf.c | 229 ---------------- configs/j721e_evm_r5_defconfig | 6 +- include/configs/j721e_evm.h | 4 + include/elf.h | 4 + lib/Kconfig | 6 + lib/Makefile | 1 + lib/elf.c | 246 ++++++++++++++++++ 15 files changed, 427 insertions(+), 309 deletions(-) create mode 100644 arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi create mode 100644 lib/elf.c -- 2.17.1

2 10

[PATCH 1/1] power: mfd: k3_avs: update am65xx MPU_VDD voltage values
by Tero Kristo 23 Feb '20

23 Feb '20

The latest data manual SPRSP08I –NOVEMBER 2017–REVISED DECEMBER 2019[1] for am65xx SoC states the new MPU nominal voltages to be 1.1V (OPP_NOM), 1.2V (OPP_OD) and 1.24V (OPP_TURBO). Update the nominal voltages in the K3 AVS driver to reflect this. [1] http://www.ti.com/lit/gpn/am6528 Signed-off-by: Tero Kristo <t-kristo(a)ti.com> --- drivers/misc/k3_avs.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 47e42738e0..e4857ddd97 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -312,15 +312,15 @@ static struct vd_data am654_vd_data[] = { .opp = AM6_OPP_NOM, .opps = { [AM6_OPP_NOM] = { - .volt = 1000000, + .volt = 1100000, .freq = 800000000, }, [AM6_OPP_OD] = { - .volt = 1100000, + .volt = 1200000, .freq = 1000000000, }, [AM6_OPP_TURBO] = { - .volt = 1220000, + .volt = 1240000, .freq = 1100000000, }, }, @@ -332,15 +332,15 @@ static struct vd_data am654_vd_data[] = { .clk_id = 0, /* ARM clock */ .opps = { [AM6_OPP_NOM] = { - .volt = 1000000, + .volt = 1100000, .freq = 800000000, }, [AM6_OPP_OD] = { - .volt = 1100000, + .volt = 1200000, .freq = 1000000000, }, [AM6_OPP_TURBO] = { - .volt = 1220000, + .volt = 1240000, .freq = 1100000000, }, }, -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

2 1

[PATCHv2 0/7] ESM support for TI K3 SoCs
by Tero Kristo 23 Feb '20

23 Feb '20

Hi, V2 contains changes proposed by Lokesh. - Move main_esm under R5 .dts file (patch #4) - Move ESM probing to the board file (patch #6) - Enabled SPL board init in the r5 defconfig (needed for patch #6 change, done in patch #7) -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

3 9

[PATCH] bootcounter: add DM support for memory based bootcounter
by Heiko Schocher 22 Feb '20

22 Feb '20

add DM/DTS support for the memory based bootcounter in drivers/bootcount/bootcount.c. Let the old implementation in, so boards which have not yet convert to DM/DTS do not break. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Travis build: https://travis-ci.org/hsdenx/u-boot-test/builds/652839618 doc/device-tree-bindings/misc/bootcounter.txt | 21 +++++ drivers/bootcount/Kconfig | 5 ++ drivers/bootcount/Makefile | 1 + drivers/bootcount/bootcount.c | 86 +++++++++++++++++++ 4 files changed, 113 insertions(+) create mode 100644 doc/device-tree-bindings/misc/bootcounter.txt diff --git a/doc/device-tree-bindings/misc/bootcounter.txt b/doc/device-tree-bindings/misc/bootcounter.txt new file mode 100644 index 0000000000..f4a4a731b9 --- /dev/null +++ b/doc/device-tree-bindings/misc/bootcounter.txt @@ -0,0 +1,21 @@ +U-Boot bootcounter Devicetree Binding +===================================== + +The device tree node describes the U-Boot bootcounter +memory based device binding. + +Required properties : + +- compatible : "uboot,bootcount"; +- singleword : set this, if you have only one word space + for storing the bootcounter. + +Example +------- + +MPC83xx based board: + +bootcount@0x13ff8 { + compatible = "uboot,bootcount"; + reg = <0x13ff8 0x08>; +}; diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 0e506c9ea2..88203607a8 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -106,6 +106,11 @@ config DM_BOOTCOUNT_I2C_EEPROM pointing to the underlying i2c eeprom device) and an optional 'offset' property are supported. +config BOOTCOUNT_MEM + bool "memory based bootcounter" + help + Memory based bootcount, compatible = "uboot,bootcount"; + endmenu endif diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index 73ccfb5a08..059d40d16b 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_BOOTCOUNT_GENERIC) += bootcount.o +obj-$(CONFIG_BOOTCOUNT_MEM) += bootcount.o obj-$(CONFIG_BOOTCOUNT_AT91) += bootcount_at91.o obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index 7a6d03dcca..53bd416cf6 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -8,6 +8,7 @@ #include <cpu_func.h> #include <linux/compiler.h> +#if !defined(CONFIG_DM_BOOTCOUNT) /* Now implement the generic default functions */ __weak void bootcount_store(ulong a) { @@ -49,3 +50,88 @@ __weak ulong bootcount_load(void) return raw_bootcount_load(reg); #endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) */ } +#else +#include <dm.h> + +struct bootcount_mem_priv { + phys_addr_t base; + u8 singleword; +}; + +static int bootcount_mem_get(struct udevice *dev, u32 *a) +{ + struct bootcount_mem_priv *priv = dev_get_priv(dev); + void *reg = (void *)priv->base; + u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC; + + if (priv->singleword) { + u32 tmp = raw_bootcount_load(reg); + + if ((tmp & 0xffff0000) != (magic & 0xffff0000)) + return -ENODEV; + + *a = (tmp & 0x0000ffff); + } else { + if (raw_bootcount_load(reg + 4) != magic) + return -ENODEV; + + *a = raw_bootcount_load(reg); + } + + return 0; +}; + +static int bootcount_mem_set(struct udevice *dev, const u32 a) +{ + struct bootcount_mem_priv *priv = dev_get_priv(dev); + void *reg = (void *)priv->base; + u32 magic = CONFIG_SYS_BOOTCOUNT_MAGIC; + uintptr_t flush_start = rounddown(priv->base, + CONFIG_SYS_CACHELINE_SIZE); + uintptr_t flush_end; + + if (priv->singleword) { + raw_bootcount_store(reg, (magic & 0xffff0000) | a); + flush_end = roundup(priv->base + 4, + CONFIG_SYS_CACHELINE_SIZE); + } else { + raw_bootcount_store(reg, a); + raw_bootcount_store(reg + 4, magic); + flush_end = roundup(priv->base + 8, + CONFIG_SYS_CACHELINE_SIZE); + } + flush_dcache_range(flush_start, flush_end); + + return 0; +}; + +static const struct bootcount_ops bootcount_mem_ops = { + .get = bootcount_mem_get, + .set = bootcount_mem_set, +}; + +static int bootcount_mem_probe(struct udevice *dev) +{ + struct bootcount_mem_priv *priv = dev_get_priv(dev); + + priv->base = (phys_addr_t)devfdt_get_addr(dev); + priv->singleword = dev_read_u32_default(dev, "singleword", 0); + + return 0; +} + +static const struct udevice_id bootcount_mem_ids[] = { + { .compatible = "uboot,bootcount" }, + { .compatible = "u-boot,bootcount" }, + { } +}; + +U_BOOT_DRIVER(bootcount_mem) = { + .name = "bootcount-mem", + .id = UCLASS_BOOTCOUNT, + .priv_auto_alloc_size = sizeof(struct bootcount_mem_priv), + .probe = bootcount_mem_probe, + .of_match = bootcount_mem_ids, + .ops = &bootcount_mem_ops, +}; +#endif -- 2.24.1

2 2