February 2020 - U-Boot

[PATCH] lx2160a : Remove default VID setting
by Meenakshi Aggarwal 30 Mar '20

30 Mar '20

Set VID to 800 mV for Rev1 and set VID as per switch settings for Rev2. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> --- board/freescale/lx2160a/lx2160a.c | 9 ++++++++- include/configs/lx2160aqds.h | 1 - include/configs/lx2160ardb.h | 1 - 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 3deb76b..ba1cac2 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -297,7 +297,14 @@ int i2c_multiplexer_select_vid_channel(u8 channel) int init_func_vid(void) { - if (adjust_vdd(0) < 0) + int set_vid; + + if (IS_SVR_REV(get_svr(), 1, 0)) + set_vid = adjust_vdd(800); + else + set_vid = adjust_vdd(0); + + if (set_vid < 0) printf("core voltage not adjusted\n"); return 0; diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 56a50d3..ddc76bd 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -127,7 +127,6 @@ u8 qixis_esdhc_detect_quirk(void); /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ - "lx2160aqds_vdd_mv=800\0" \ "boot_scripts=lx2160aqds_boot.scr\0" \ "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \ "BOARD=lx2160aqds\0" \ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 5b530f0..e86102a 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -99,7 +99,6 @@ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2160ardb_boot.scr\0" \ "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \ - "lx2160ardb_vdd_mv=800\0" \ "BOARD=lx2160ardb\0" \ "xspi_bootcmd=echo Trying load from flexspi..;" \ "sf probe 0:0 && sf read $load_addr " \ -- 1.9.1

2 1

[PATCH] lx2160a : Add emmc in boot_targets environment variable
by Meenakshi Aggarwal 30 Mar '20

30 Mar '20

Add emmc in supported boot_targets and Add bootcmd environment variable for emmc boot. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> --- include/configs/lx2160a_common.h | 11 +++++++++++ include/configs/lx2160aqds.h | 7 +++++++ include/configs/lx2160ardb.h | 7 +++++++ 3 files changed, 25 insertions(+) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 0b0075a..bf1ba82 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -284,9 +284,20 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "run distro_bootcmd;run sd_bootcmd;" \ "env exists secureboot && esbc_halt;" +#define SD2_BOOTCOMMAND \ + "env exists mcinitcmd && mmcinfo; " \ + "mmc read 0x80d00000 0x6800 0x800; " \ + "env exists mcinitcmd && env exists secureboot " \ + " && mmc read 0x80780000 0x3C00 0x20 " \ + "&& esbc_validate 0x80780000;env exists mcinitcmd " \ + "&& fsl_mc lazyapply dpl 0x80d00000;" \ + "run distro_bootcmd;run sd2_bootcmd;" \ + "env exists secureboot && esbc_halt;" + #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ func(SCSI, scsi, 0) #include <config_distro_bootcmd.h> diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 56a50d3..12783a8 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -143,6 +143,13 @@ u8 qixis_esdhc_detect_quirk(void); "env exists secureboot && mmc read $kernelheader_addr_r "\ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" #include <asm/fsl_secure_boot.h> diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 5b530f0..ff92c0a 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -113,6 +113,13 @@ "env exists secureboot && mmc read $kernelheader_addr_r "\ "$kernelhdr_addr_sd $kernelhdr_size_sd " \ " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" #include <asm/fsl_secure_boot.h> -- 1.9.1

2 1

[PATCH 1/2] arm64: ls1028a: remove fdt_high environment variable
by Yuantian Tang 30 Mar '20

30 Mar '20

Setting fdt_high and initrd_high to 0xffffffffffffffff leads to various difficulty to resolve bugs. Remove them and use bootm_size instead to safely contain a kernel, device tree and initrd for relocation. Signed-off-by: Yuantian Tang <andy.tang(a)nxp.com> --- include/configs/ls1028a_common.h | 3 +-- include/configs/ls1028aqds.h | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 05b8cf00ee..1c7680c234 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -79,8 +79,7 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ + "bootm_size=0x10000000\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 982df07bb0..fca0a3af19 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -90,8 +90,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ -- 2.17.1

2 2

[PATCH 0/3] Program GIC LPI configuration table
by Wasim Khan 30 Mar '20

30 Mar '20

This patch set programs GIC LPI configuration table from Uboot for NXP's LX2160A SoC. Wasim Khan (3): board: fsl: lx2160a: Program GIC LPI configuration table configs: lx2160a: Enable GIC_V3_ITS config board: fsl: lx2160a: Add GIC LPI memory reserve fixup board/freescale/lx2160a/lx2160a.c | 26 +++++++++++++++++++++++++- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + 5 files changed, 29 insertions(+), 1 deletion(-) -- 2.7.4

2 5

[PATCH v2] board: lx2160a: Correct board fixup for PCIe nodes
by Vikas Singh 30 Mar '20

30 Mar '20

Update "board_fix_fdt" with correct counter value "i". This will fix the issue while fetching the "reg_names" resource from fdt after fixup. Signed-off-by: Vikas Singh <vikas.singh(a)nxp.com> --- Notes: V2 Add correct subject and remove the '.' from it board/freescale/lx2160a/lx2160a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 4509a34..5c23554 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -169,6 +169,7 @@ int board_fix_fdt(void *fdt) reg_name = reg_names; remaining_names_len = names_len - (reg_name - reg_names); + i = 0; while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { old_name_len = strlen(reg_names_map[i].old_str); new_name_len = strlen(reg_names_map[i].new_str); -- 2.7.4

2 1

[PATCH] ls1021a: Set CONFIG_SYS_BOOTMAPSZ to the memory for relocation
by Alison Wang 30 Mar '20

30 Mar '20

This patch sets CONFIG_SYS_BOOTMAPSZ to the amount of memory available to safely contain a kernel, device tree and initrd for relocation. The way to set fdt_high as 0xffffffff to disable device tree relocation is removed. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- include/configs/ls1021aiot.h | 5 +++-- include/configs/ls1021aqds.h | 3 +-- include/configs/ls1021atsn.h | 3 ++- include/configs/ls1021atwr.h | 3 +-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 769a7e2..4e3d818 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -207,12 +207,13 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ -"initrd_high=0xffffffff\0" \ -"fdt_high=0xffffffff\0" +"initrd_high=0xffffffff\0" /* * Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MEMINFO diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6f1c0d4..5345e8f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -460,13 +460,11 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #endif @@ -474,6 +472,7 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 84fdfce..039c794 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -154,7 +154,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ @@ -216,6 +215,8 @@ "bootm $load_addr#$board\0" /* Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index e845232..511d10a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -299,7 +299,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x65000000\0" \ "scriptaddr=0x80000000\0" \ @@ -357,7 +356,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ @@ -441,6 +439,7 @@ /* * Miscellaneous configurable options */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff -- 2.9.5

3 2

[PATCH 1/1] vexpress_ca9x4: Enable use of correct DTB file and restore EFI loader.
by Kristian Amlie 30 Mar '20

30 Mar '20

EFI was disabled in f95b8a4b5f64f because of the missing DTB file, and indeed, the DTB file is required to load recent versions of GRUB (2.04) correctly. Signed-off-by: Kristian Amlie <kristian.amlie(a)northern.tech> --- configs/vexpress_ca9x4_defconfig | 2 +- include/configs/vexpress_common.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 2119df6b10..6bd1f253b6 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -34,4 +34,4 @@ CONFIG_SMC911X_32_BIT=y CONFIG_BAUDRATE=38400 CONFIG_CONS_INDEX=0 CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set +CONFIG_DEFAULT_FDT_FILE="vexpress-v2p-ca9.dtb" diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 7f215a6707..e73658a9e6 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -207,7 +207,8 @@ "devtmpfs.mount=0 vmalloc=256M\0" \ "bootflash=run flashargs; " \ "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ - "bootm ${kernel_addr} ${ramdisk_addr_r}\0" + "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" /* FLASH and environment organization */ #define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ -- 2.17.1

3 12

[PATCH 1/2] rockchip: video: Use ofnode_decode_display_timing() to parse timing
by Kever Yang 29 Mar '20

29 Mar '20

Use ofnode_decode_display_timing() instead of fdtdec_decode_display_timing() to parse display timing, so that we can support live DT. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- drivers/video/rockchip/rk_lvds.c | 3 +-- drivers/video/rockchip/rk_mipi.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index cf5c0439b1..cae8bada32 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -160,8 +160,7 @@ int rk_lvds_enable(struct udevice *dev, int panel_bpp, int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing) { - if (fdtdec_decode_display_timing - (gd->fdt_blob, dev_of_offset(dev), 0, timing)) { + if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) { debug("%s: Failed to decode display timing\n", __func__); return -EINVAL; } diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index f9280e8607..a77bdfd24d 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -29,8 +29,7 @@ int rk_mipi_read_timing(struct udevice *dev, { int ret; - ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev), - 0, timing); + ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing); if (ret) { debug("%s: Failed to decode display timing (ret=%d)\n", __func__, ret); -- 2.17.1

2 4

[U-Boot] [PATCH] rockchip: rk3399: Add Pinebook Pro laptop support
by Peter Robinson 28 Mar '20

28 Mar '20

Add initial support for Pinebook Pro laptop. Specification - Rockchip RK3399 - 4GB Dual-Channel LPDDR4 - SD card slot - eMMC socket - 128Mb SPI Flash - PCIe 4X slot - AP6256 for WiFi + BT - 1920*1080 screen - USB 3.0, 2.0 - USB Type C power and data - DC 12V/2A Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- Initial v1 for feedback U-Boot TPL 2020.01-rc2-00005-g7d87be0ff5 (Nov 14 2019 - 00:27:33) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2020.01-rc2-00005-g7d87be0ff5 (Nov 14 2019 - 00:27:33 +0000) Trying to boot from MMC1 U-Boot 2020.01-rc2-00005-g7d87be0ff5 (Nov 14 2019 - 00:27:33 +0000) Model: Pine64 Pinebook Pro DRAM: 3.9 GiB PMIC: RK808 MMC: dwmmc@fe320000: 1, sdhci@fe330000: 0 In: serial@ff1a0000 Out: serial@ff1a0000 Err: serial@ff1a0000 Model: Pine64 Pinebook Pro ## Error: Can't overwrite "serial#" ## Error inserting "serial#" variable, errno=1 rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: No ethernet found. Hit any key to stop autoboot: 0 => arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 25 + arch/arm/dts/rk3399-pinebook-pro.dts | 631 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 8 + board/pine64/pinebook_pro_rk3399/Kconfig | 15 + board/pine64/pinebook_pro_rk3399/MAINTAINERS | 8 + board/pine64/pinebook_pro_rk3399/Makefile | 1 + .../pinebook_pro_rk3399/pinebook-pro-rk3399.c | 192 ++++++ configs/pinebook_pro-rk3399_defconfig | 76 +++ include/configs/pinebook_pro_rk3399.h | 29 + 10 files changed, 986 insertions(+) create mode 100644 arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-pinebook-pro.dts create mode 100644 board/pine64/pinebook_pro_rk3399/Kconfig create mode 100644 board/pine64/pinebook_pro_rk3399/MAINTAINERS create mode 100644 board/pine64/pinebook_pro_rk3399/Makefile create mode 100644 board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c create mode 100644 configs/pinebook_pro-rk3399_defconfig create mode 100644 include/configs/pinebook_pro_rk3399.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5a64fcc5a7..affedfd666 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -116,6 +116,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi new file mode 100644 index 0000000000..9b0cb7010f --- /dev/null +++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&spiflash { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-pinebook-pro.dts b/arch/arm/dts/rk3399-pinebook-pro.dts new file mode 100644 index 0000000000..85ce0206d7 --- /dev/null +++ b/arch/arm/dts/rk3399-pinebook-pro.dts @@ -0,0 +1,631 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Pine64 Pinebook Pro"; + compatible = "pine64,pinebook-pro", "rockchip,rk3399"; + + chosen { + stdout-path = &uart2; + }; + + aliases { + spi0 = &spi1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pwms = <&pwm0 0 740740 0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds { + status = "okay"; + compatible = "gpio-leds"; + + work-led { + label = "work"; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + standby-led { + label = "standby"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_usb3_host: vcc5v0-usb3-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_usb3_drv>; + regulator-name = "vcc5v0_usb3_host"; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <950000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_usb3_host>; + status = "okay"; + }; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_vbus_drv: host-vbus-drv { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_usb3_drv: host-usb3-drv { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; + max-frequency = <20000000>; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <25000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&spi1 { + status = "okay"; + + spiflash: spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <10000000>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@8000 { + label = "loader"; + reg = <0x0 0x3F8000>; + }; + + env@3f8000 { + label = "env"; + reg = <0x3F8000 0x8000>; + }; + + vendor@7c0000 { + label = "vendor"; + reg = <0x7C0000 0x40000>; + }; + }; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index f781eacd16..f694ce0119 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -10,6 +10,13 @@ config TARGET_EVB_RK3399 with full function and phisical connectors support like type-C ports, usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... +config TARGET_PINEBOOK_PRO_RK3399 + bool "Pinebook Pro" + help + Pinebook Pro is a laptop based on the Rockchip rk3399 SoC + with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, + 1920*1080 screen and all the usual laptop features. + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help @@ -94,6 +101,7 @@ config TPL_TEXT_BASE config SPL_STACK_R_ADDR default 0x04000000 +source "board/pine64/pinebook_pro_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/board/pine64/pinebook_pro_rk3399/Kconfig b/board/pine64/pinebook_pro_rk3399/Kconfig new file mode 100644 index 0000000000..c37c643d6f --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PINEBOOK_PRO_RK3399 + +config SYS_BOARD + default "pinebook_pro_rk3399" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "pinebook_pro_rk3399" + +config BOARD_SPECIFIC_OPTIONS + def_bool y + +endif diff --git a/board/pine64/pinebook_pro_rk3399/MAINTAINERS b/board/pine64/pinebook_pro_rk3399/MAINTAINERS new file mode 100644 index 0000000000..58400ebd28 --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/MAINTAINERS @@ -0,0 +1,8 @@ +PINEBOOK_PRO +M: Peter Robinson <pbrobinson at gmail.com> +S: Maintained +F: board/pine64/pinebook_pro_rk3399/ +F: include/configs/pinebook_pro_rk3399.h +F: arch/arm/dts/rk3399-pinebook-pro.dts +F: arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +F: configs/pinebook_pro-rk3399_defconfig diff --git a/board/pine64/pinebook_pro_rk3399/Makefile b/board/pine64/pinebook_pro_rk3399/Makefile new file mode 100644 index 0000000000..2f692a12a6 --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/Makefile @@ -0,0 +1 @@ +obj-y += pinebook-pro-rk3399.o diff --git a/board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c new file mode 100644 index 0000000000..b1a2ed3b77 --- /dev/null +++ b/board/pine64/pinebook_pro_rk3399/pinebook-pro-rk3399.c @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <misc.h> +#include <syscon.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <asm/io.h> +#include <asm/setup.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/misc.h> +#include <asm/arch-rockchip/periph.h> +#include <power/regulator.h> +#include <usb.h> +#include <dwc3-uboot.h> + +#define RK3399_CPUID_OFF 0x7 +#define RK3399_CPUID_LEN 0x10 + +static int fix_lcd_backling_pull_mode(void) +{ +#include <asm/arch-rockchip/grf_rk3399.h> + +#define PMU_GRF_BASE 0xff320000 + + // set pull of GPIO1_A0 + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMU_GRF_BASE; + rk_clrsetreg(&pmugrf->gpio1_p[0], 3 << (2 * 0), 0 << (2 * 0)); + return 0; +} + +#ifndef CONFIG_SPL_BUILD +int board_early_init_f(void) +{ + struct udevice *regulator; + int ret; + + ret = regulator_get_by_platname("vcc5v0_host", &regulator); + if (ret) { + debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); + goto out; + } + + ret = regulator_set_enable(regulator, true); + if (ret) + debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret); + + fix_lcd_backling_pull_mode(); + +out: + return 0; +} +#endif + +static void setup_serial(void) +{ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + struct udevice *dev; + int ret, i; + u8 cpuid[RK3399_CPUID_LEN]; + u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2]; + char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; + u64 serialno; + char serialno_str[16]; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return; + } + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); + + env_set("cpuid#", cpuid_str); + env_set("serial#", serialno_str); +#endif + + return; +} + +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define PMUGRF_CON0_VSEL_SHIFT 8 + +#ifdef CONFIG_MISC_INIT_R +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = + syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + + /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ + rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + setup_iodomain(); + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + ret = rockchip_setup_macaddr(); + + setup_serial(); + + return ret; +} +#endif + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + u64 serial = 0; + + serial_string = env_get("serial#"); + + if (serial_string) + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (u32)(serial >> 32); + serialnr->low = (u32)(serial & 0xffffffff); +} +#endif + +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = 0xfe800000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .dis_u2_susphy_quirk = 1, +}; + +int usb_gadget_handle_interrupts(void) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + return dwc3_uboot_init(&dwc3_device_data); +} +#endif diff --git a/configs/pinebook_pro-rk3399_defconfig b/configs/pinebook_pro-rk3399_defconfig new file mode 100644 index 0000000000..28577256e7 --- /dev/null +++ b/configs/pinebook_pro-rk3399_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_PINEBOOK_PRO_RK3399=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MTDPARTS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_BOOTDELAY=3 +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_ROCKCHIP_USB2_PHY=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +# CONFIG_USB_XHCI_ROCKCHIP is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/pinebook_pro_rk3399.h b/include/configs/pinebook_pro_rk3399.h new file mode 100644 index 0000000000..f383becbf8 --- /dev/null +++ b/include/configs/pinebook_pro_rk3399.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2016 Rockchip Electronics Co., Ltd + * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PINEBOOKPRO_RK3399_H +#define __PINEBOOKPRO_RK3399_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3399_common.h> + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#endif + +#undef CONFIG_SYS_SPI_U_BOOT_OFFS +#define CONFIG_SYS_SPI_U_BOOT_OFFS 1024 * 512 + +#define SDRAM_BANK_SIZE (2UL << 30) + +#endif -- 2.23.0

4 5

[PATCH v2 00/12] phy: atheros: dt bindings and cleanup
by Michael Walle 27 Mar '20

27 Mar '20

[RESEND because I've forgot to add the mailinglist. Sorry!] This patch series superseeds the following two: >From Vladimir Oltean https://patchwork.ozlabs.org/cover/1031360/ >From me: https://patchwork.ozlabs.org/cover/1184507/ Although the first is marked as accepted into u-boot-net I guess it was removed due to broken boards ("DT as ABI", RGMII delay was fixed and thus breaks the board). After disussing with Vladimir, I've integrated his patches with this series. Also the first one Address packet drops at low traffic rate due to SmartEEE feature was dropped because it will likely be fixed by making u-boot support the eee-broken-X device tree properties. Apart from that, only the subject was changed and a note about possible board breakage was added the patch which changes the delay behaviour. For all of those, who will test this patchset, the device tree binding needs the phydev->node property, which needs to be set in every network driver. If the device tree binding is not working for you have a look at the ar803x_of_init: found PHY node: phy@0 output. In the case above "phy@0" is the phy node in the device tree. If instead the node of your network device is displayed, you have to set the phydev->node property in your network device driver. For the fsl_enetc driver this patchset will add it: https://patchwork.ozlabs.org/cover/1188043/ changes since v1: - pull all Vladimirs Oltan's patches and rebase mine onto them - fix the CLK_25M settings for the AR8035 - add two new patches "fix AR8021 PHY ID mask" and "use defines for PHY IDs" - use the new kernel device tree binding for the AR803x PHYs: https://patchwork.ozlabs.org/patch/1188293/ - add debugging output Michael Walle (7): phy: atheros: fix AR8021 PHY ID mask phy: atheros: use defines for PHY IDs phy: atheros: introduce debug read and write functions phy: atheros: move delay config to common function phy: atheros: add device tree bindings and config phy: atheros: ar8035: remove static clock config phy: atheros: consolidate {ar8031|ar8035}_config() Vladimir Oltean (5): phy: atheros: Make RGMII Tx delays actually configurable for AR8035 phy: atheros: Use common functions for RGMII internal delays phy: atheros: Clarify the configuration of the CLK_25M output pin phy: atheros: Explicitly disable RGMII delays phy: atheros: Clarify the intention of ar8021_config doc/device-tree-bindings/net/phy/atheros.txt | 35 ++ drivers/net/phy/atheros.c | 349 ++++++++++++++++--- include/dt-bindings/net/qca-ar803x.h | 13 + 3 files changed, 344 insertions(+), 53 deletions(-) create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt create mode 100644 include/dt-bindings/net/qca-ar803x.h -- 2.20.1

3 22