February 2020 - U-Boot

[PATCH] spi: cadence-qspi: Move ref clock calculation to probe
by Pratyush Yadav 03 Apr '20

03 Apr '20

"assigned-clock-parents" and "assigned-clock-rates" DT properties take effect only after ofdata_to_platdata() when clk_set_defaults() is called in device_probe(). Therefore clk get rate() would return a wrong value in ofdata_to_platdata() when compared with probe. Hence it needs to be moved to probe. Tested on u-boot-ti/next. Signed-off-by: Pratyush Yadav <p.yadav(a)ti.com> --- drivers/spi/cadence_qspi.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 83b114ffe7..994a5948f1 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -166,11 +166,28 @@ static int cadence_spi_probe(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + struct clk clk; int ret; priv->regbase = plat->regbase; priv->ahbbase = plat->ahbbase; + if (plat->ref_clk_hz == 0) { + ret = clk_get_by_index(bus, 0, &clk); + if (ret) { +#ifdef CONFIG_CQSPI_REF_CLK + plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; +#else + return ret; +#endif + } else { + plat->ref_clk_hz = clk_get_rate(&clk); + clk_free(&clk); + if (IS_ERR_VALUE(plat->ref_clk_hz)) + return plat->ref_clk_hz; + } + } + ret = reset_get_bulk(bus, &priv->resets); if (ret) dev_warn(bus, "Can't get reset: %d\n", ret); @@ -268,8 +285,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; ofnode subnode; - struct clk clk; - int ret; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, @@ -305,20 +320,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); - ret = clk_get_by_index(bus, 0, &clk); - if (ret) { -#ifdef CONFIG_CQSPI_REF_CLK - plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; -#else - return ret; -#endif - } else { - plat->ref_clk_hz = clk_get_rate(&clk); - clk_free(&clk); - if (IS_ERR_VALUE(plat->ref_clk_hz)) - return plat->ref_clk_hz; - } - debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, plat->page_size); -- 2.25.0

4 4

[U-Boot] [PATCH 0/2] Add Broadcom SPI driver
by Vladimir Olovyannikov 03 Apr '20

03 Apr '20

This patchset: - adds Broadcom SPI driver for iproc-based platforms and - extends Micron SPI commands for dual and quad SPI transfers on Micon SPI. Shreesha Rajashekar (1): drivers: spi: Add brcm iproc spi driver Corneliu Doban (1): drivers: spi: Add commands for Micron SPI drivers/spi/Kconfig | 26 + drivers/spi/Makefile | 4 + drivers/spi/iproc_qspi.c | 1161 ++++++++++++++++++++++++++++++++++++++ drivers/spi/iproc_qspi.h | 47 ++ drivers/spi/iproc_spi.c | 71 +++ include/spi.h | 6 + 6 files changed, 1315 insertions(+) create mode 100644 drivers/spi/iproc_qspi.c create mode 100644 drivers/spi/iproc_qspi.h create mode 100644 drivers/spi/iproc_spi.c -- 2.17.1

2 3

[PATCH resend 0/5] spi: mpc8xxx_spi: bug fixes, real ->set_speed and a pseudo-gpio driver
by Rasmus Villemoes 31 Mar '20

31 Mar '20

This is a combination of a single patch and a 4-part series sent previously [1,2], this time with Jagan on Cc. Patch 1 is a convenient pseudo-gpio driver for controlling a single output signal on mpc830x. Since it's (usually) used as a chip select, representing it as a gpio (without the gp or i) makes it simple to use in device tree. The remaining four fix bugs in the mpc8xxx_spi driver, most importantly patch 4. Without it, reads and writes of certain lengths from spi-nor fails, and stuff at physical address 0x0 gets overwritten even if no input buffer is supplied (e.g. when sending a command). Tested on an mpc8309-derived board. It would be nice if someone with access to the gazerbeam board can test that this doesn't break that - in particular, the "only do transfers that are multiple of 8 bits" part. [1] https://patchwork.ozlabs.org/patch/1219513/ [2] https://patchwork.ozlabs.org/cover/1218170/ Klaus H. Sorensen (1): gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal Rasmus Villemoes (4): gazerbeam: add clocks property to SPI node mpc8xxx_spi: put max_cs to use mpc8xxx_spi: always use 8-bit characters, don't read or write garbage mpc8xxx_spi: implement real ->set_speed arch/powerpc/dts/gdsys/mpc8308.dtsi | 7 + .../gpio/fsl,mpc83xx-spisel-boot.txt | 22 +++ drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/mpc83xx_spisel_boot.c | 148 ++++++++++++++++++ drivers/spi/mpc8xxx_spi.c | 141 ++++++++++------- 6 files changed, 267 insertions(+), 60 deletions(-) create mode 100644 doc/device-tree-bindings/gpio/fsl,mpc83xx-spisel-boot.txt create mode 100644 drivers/gpio/mpc83xx_spisel_boot.c -- 2.23.0

2 11

[PATCH resend 0/2] gpio: mpc8xxx: honour shadow register when writing gpdat
by Rasmus Villemoes 31 Mar '20

31 Mar '20

[resending with Mario's correct address, sorry for the double post] The driver correctly uses the shadow register when asked for the current value of an output gpio. Unfortunately, it does RMW on the gpdat register both when setting a gpio as input and output. These two patches fix that. Aside: Apparently, the mpc8309 also partially suffers from the errata preventing outputs from being read back - the bits corresponding to gpios 0-7 are always read as 0, while at least the value of gpio10 is correctly reflected when reading gpdat. Which is how I noticed these bugs - I couldn't understand why turning one LED on would turn off another. Rasmus Villemoes (2): gpio: mpc8xxx: don't modify gpdat when setting gpio as input gpio: mpc8xxx: don't do RMW on gpdat register when setting value drivers/gpio/mpc8xxx_gpio.c | 41 ++++++++++++++----------------------- 1 file changed, 15 insertions(+), 26 deletions(-) -- 2.23.0

2 9

[U-Boot] [PATCH v1 0/2] stm32f7 gpio driver fixes
by Patrice Chotard 31 Mar '20

31 Mar '20

This series adds: - Fix gpio bank hole management for stm32 F7 and H7 - Fix SPL code size for stm32 F7 Patrice Chotard (2): gpio: stm32f7: Fix gpio bank hole management gpio: stm32f7: Fix SPL code size drivers/gpio/stm32f7_gpio.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
by Nico Becker 31 Mar '20

31 Mar '20

Hello, after removing the function socfpga_sdram_apply_static_cfg() in misc_gen5 we can not use the FPGA2SDRAM bridge. Without the apply static cfg the kernel crash every time, if we try to write @ the fpga2sdram bridge. After an soft reset everything is working. If we add the socfpga_sdram_apply_static_cfg() in the u-boot source code, everything is fine. Now we can use the fpga2sdram bridge after power on. Our setup: - u-boot v2020.01 - load and write fpga firmware - enable bridges - boot linux I have found some information at <https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Importan…> <http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html> -- Best regards Nico Becker

5 33

[PATCH] configs: lx2160a: Define ENV_ADDR value
by Kuldeep Singh 30 Mar '20

30 Mar '20

CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. Define the value as 0x20500000 for lx2160ardb and lx2160aqds. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- Hi Priyanka, This patch can be applied after applying below patch. https://patchwork.ozlabs.org/project/uboot/list/?series=141023 configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 987b8c3..36e7bbd 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -33,6 +33,7 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 0b0a2b2..fdeacd8 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -34,6 +34,7 @@ CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- 2.7.4

2 1

[PATCH 1/1] armv8: ls1028a: Update secure boot headers offset
by Priyanka Singh 30 Mar '20

30 Mar '20

Update the secure boot headers offsets of Kernel and other firmware images for SD and XSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh <priyanka.singh(a)nxp.com> --- include/configs/ls1028a_common.h | 8 ++++---- include/configs/ls1028aqds.h | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 98320e22e9..62639cfb39 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __L1028A_COMMON_H @@ -92,14 +92,14 @@ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ + "kernelhdr_addr_sd=0x3000\0" \ + "kernelhdr_size_sd=0x20\0" \ "console=ttyS0,115200\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index b0e9441a48..4eec03dcbd 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __LS1028A_QDS_H @@ -104,13 +104,13 @@ "fdt_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x600000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ -- 2.17.1

2 3

[PATCH 1/2] configs: arm64: ls1012afrdm Enable CONFIG_BLK
by Ran Wang 30 Mar '20

30 Mar '20

With DM_USB enabled, enable CONFIG_BLK to remove this compile warning for ls1012afrdm based targets: ===================== WARNING ====================== This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- configs/ls1012afrdm_qspi_defconfig | 1 + configs/ls1012afrdm_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index e5196de..ee0e19c 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -55,3 +55,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_DM_RTC=y +CONFIG_BLK=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 4b55b0c..57bf0a6 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -55,3 +55,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_DM_RTC=y +CONFIG_BLK=y -- 2.7.4

2 2

[RESEND v8 6/8] dm: arm64: ls1043a: add i2c DM support
by Biwen Li 30 Mar '20

30 Mar '20

This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1043A Reviewed-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Biwen Li <biwen.li(a)nxp.com> --- Changes in RESEND v8: - fix build warning Changes in v8: - none Changes in v7: - none Changes in v6: - correct dependencies Changes in v5: - update subject Changes in v4: - update copyright Changes in v3: - none Changes in v2: - merge some patches to one patch arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 +- arch/arm/include/asm/gpio.h | 4 +- board/freescale/ls1043aqds/ls1043aqds.c | 98 +++++++++++++++++-- configs/ls1043aqds_defconfig | 2 + configs/ls1043aqds_lpuart_defconfig | 2 + configs/ls1043aqds_nand_defconfig | 2 + configs/ls1043aqds_nor_ddr3_defconfig | 2 + configs/ls1043aqds_qspi_defconfig | 2 + configs/ls1043aqds_sdcard_ifc_defconfig | 2 + configs/ls1043aqds_sdcard_qspi_defconfig | 2 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1043aqds_tfa_defconfig | 2 + configs/ls1043ardb_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_defconfig | 2 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_nand_defconfig | 2 + .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_sdcard_defconfig | 2 + configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1043ardb_tfa_defconfig | 2 + include/configs/ls1043a_common.h | 11 +++ 21 files changed, 144 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 275c66d992..760053e401 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -74,11 +74,11 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC - select SYS_I2C_MXC_I2C1 - select SYS_I2C_MXC_I2C2 - select SYS_I2C_MXC_I2C3 - select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC_I2C1 if !DM_I2C + select SYS_I2C_MXC_I2C2 if !DM_I2C + select SYS_I2C_MXC_I2C3 if !DM_I2C + select SYS_I2C_MXC_I2C4 if !DM_I2C imply CMD_PCI config ARCH_LS1046A diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 29dc498bd8..c480e712fe 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -3,8 +3,8 @@ !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \ !defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1028A) && \ - !defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \ - !defined(CONFIG_ARCH_ASPEED) && \ + !defined(CONFIG_ARCH_LS1043A) && !defined(CONFIG_ARCH_LS2080A) && \ + !defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \ !defined(CONFIG_ARCH_U8500) #include <asm/arch/gpio.h> #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 8c96b962b7..2d4b18cdbc 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -271,11 +272,24 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -290,8 +304,10 @@ int dram_init(void) * When resuming from deep sleep, the I2C channel may not be * in the default channel. So, switch to the default channel * before accessing DDR SPD. + * + * PCA9547 mount on I2C1 bus */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ defined(CONFIG_SPL_BUILD) @@ -304,16 +320,83 @@ int dram_init(void) int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } void board_retimer_init(void) { u8 reg; + int bus_num = 0; /* Retimer is connected to I2C1_CH7_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH7); + select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num); reg = I2C_MUX_CH5; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + dm_i2c_write(dev, 0, &reg, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + + reg = 0x0; + dm_i2c_write(dev, 0xff, &reg, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, &reg, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, &reg, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, &reg, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, &reg, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, &reg, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, &reg, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, &reg, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, &reg, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + dm_i2c_read(dev, 0x1e, &reg, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, &reg, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, &reg, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, &reg, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, &reg, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, &reg, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, &reg, 1); +#else i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1); /* Access to Control/Shared register */ @@ -360,9 +443,10 @@ void board_retimer_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); +#endif /* Return the default channel */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num); } int board_early_init_f(void) @@ -375,8 +459,10 @@ int board_early_init_f(void) u8 uart; #endif +#ifdef CONFIG_SYS_I2C #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); +#endif #endif fsl_lsch2_early_init_f(); @@ -457,7 +543,7 @@ int board_init(void) erratum_a010315(); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_retimer_init(); #ifdef CONFIG_SYS_FSL_SERDES diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 2885552ef3..93b86af607 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -62,3 +62,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 9d9229ac03..f89c2ee3a4 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -64,3 +64,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index c45eaea02a..a169bfef8f 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -78,3 +78,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 8d28fe1baf..01d0af30b1 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -63,3 +63,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 86b2eb56b8..65eff7c40b 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -58,3 +58,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index bf3f0d0990..c5042a345d 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -79,3 +79,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 0449469b89..12706a48dc 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -72,3 +72,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 4ba5a8dd95..bbd01eb290 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -64,3 +64,5 @@ CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_CMD_SETEXPR=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 24db72a39d..6e594ed07c 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -71,3 +71,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 5e030e2586..153a62866f 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -55,3 +55,5 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 0676cbccdd..d1e534388b 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -55,3 +55,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 1f4c5705d5..252c7c8313 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index e7fe2de309..de18aaa063 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -74,3 +74,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 6529c7334c..149b25ffe5 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -74,3 +74,5 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 228262477c..b386fc668c 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -73,3 +73,5 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 83bfca078b..017ec5ea7a 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -57,3 +57,5 @@ CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y CONFIG_CMD_SETEXPR=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 4154075986..eaddbca79f 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -59,3 +59,5 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index bf24d4036d..985f40412c 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor + * Copyright (C) 2019 NXP */ #ifndef __LS1043A_COMMON_H @@ -141,7 +142,17 @@ #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif /* PCIe */ #ifndef SPL_NO_PCIE -- 2.17.1

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