December 2020 - U-Boot

[PATCH] clk: at91: sam9x60: remove the parsing of atmel, main-osc-bypass
by Claudiu Beznea 07 Dec '20

07 Dec '20

Remove the parsing of atmel,main-osc-bypass DT property as the SAM9X60 have no support for crystal oscillator bypass. Setting this bit might affect the device functionality. Fixes: a64862284f65 ("clk: at91: sam9x60: add support compatible with CCF") Signed-off-by: Claudiu Beznea <claudiu.beznea(a)microchip.com> --- drivers/clk/at91/sam9x60.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index c3235f565d7e..9e9a643d62d7 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -382,7 +382,6 @@ static int sam9x60_clk_probe(struct udevice *dev) const char *p[10]; unsigned int cm[10], m[10], *tmpclkmux, *tmpmux; struct clk clk, *c; - bool main_osc_bypass; int ret, muxallocindex = 0, clkmuxallocindex = 0, i; static const struct clk_range r = { 0, 0 }; @@ -440,8 +439,6 @@ static int sam9x60_clk_probe(struct udevice *dev) if (ret) goto fail; - main_osc_bypass = dev_read_bool(dev, "atmel,main-osc-bypass"); - /* Register main rc oscillator. */ c = at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC], clk_names[ID_MAIN_RC]); @@ -453,7 +450,7 @@ static int sam9x60_clk_probe(struct udevice *dev) /* Register main oscillator. */ c = at91_clk_main_osc(base, clk_names[ID_MAIN_OSC], - clk_names[ID_MAIN_XTAL], main_osc_bypass); + clk_names[ID_MAIN_XTAL], false); if (IS_ERR(c)) { ret = PTR_ERR(c); goto fail; -- 2.7.4

2 1

[PATCH 1/4] ARM: mvebu: helios4 adjust env sizes to enable SPI to work
by dgilmore＠redhat.com 07 Dec '20

07 Dec '20

From: Dennis Gilmore <dennis(a)ausil.us> mirror the clearfog setup to enable SPI to work Signed-off-by: Dennis Gilmore <dennis(a)ausil.us> --- arch/arm/mach-mvebu/Kconfig | 1 + board/kobol/helios4/Kconfig | 24 ++++++++++++++++++++++++ configs/helios4_defconfig | 2 -- 3 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 board/kobol/helios4/Kconfig diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 0d8e0922a2..66fd771dff 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -293,5 +293,6 @@ config SECURED_MODE_CSK_INDEX depends on SECURED_MODE_IMAGE source "board/solidrun/clearfog/Kconfig" +source "board/kobol/helios4/Kconfig" endif diff --git a/board/kobol/helios4/Kconfig b/board/kobol/helios4/Kconfig new file mode 100644 index 0000000000..cad51c1cf0 --- /dev/null +++ b/board/kobol/helios4/Kconfig @@ -0,0 +1,24 @@ +menu "Helios4 configuration" + depends on TARGET_HELIOS4 + +config ENV_SIZE + hex "Environment Size" + default 0x10000 + +config ENV_OFFSET + hex "Environment offset" + default 0xF0000 + +config ENV_SECT_SIZE + hex "Environment Sector-Size" + # Use SPI or SATA flash erase block size of 4 KiB + default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI || MVEBU_SPL_BOOT_DEVICE_SATA + # Use optimistic 64 KiB erase block, will vary between actual media + default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC || MVEBU_SPL_BOOT_DEVICE_UART + +config SYS_SPI_U_BOOT_OFFS + hex "address of u-boot payload in SPI flash" + default 0x20000 + depends on MVEBU_SPL_BOOT_DEVICE_SPI + +endmenu diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index eceb85f082..bdc6f43554 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -9,8 +9,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TARGET_HELIOS4=y CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xFE000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_SERIAL_SUPPORT=y -- 2.28.0

2 4

[PATCH 1/3] rockchip: evb-rk3399: Provide init voltage
by Kever Yang 07 Dec '20

07 Dec '20

Add missing regulator-init-microvolt property to vdd_center regulator. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index 8056dc843e..523ae78657 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -38,6 +38,10 @@ status = "okay"; }; +&vdd_center { + regulator-init-microvolt = <900000>; +}; + &sdmmc { u-boot,dm-pre-reloc; bus-width = <4>; -- 2.25.1

1 2

[PATCH v3 0/2] add support for Compulab iot-gate-imx8
by Ying-Chun Liu 06 Dec '20

06 Dec '20

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate). The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Ying-Chun Liu (PaulLiu) (2): arm: dts: add imx8mm-cl-iot-gate dts file arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate) arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 131 ++ arch/arm/dts/imx8mm-cl-iot-gate.dts | 550 +++++ arch/arm/mach-imx/imx8m/Kconfig | 8 + board/compulab/imx8mm-cl-iot-gate/Kconfig | 12 + board/compulab/imx8mm-cl-iot-gate/MAINTAINERS | 6 + board/compulab/imx8mm-cl-iot-gate/Makefile | 13 + .../compulab/imx8mm-cl-iot-gate/ddr/Makefile | 8 + board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 211 ++ board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h | 26 + .../ddr/lpddr4_timing_01061010.1_2.c | 1848 +++++++++++++++++ .../ddr/lpddr4_timing_01061010.c | 1847 ++++++++++++++++ .../ddr/lpddr4_timing_ff000110.c | 1847 ++++++++++++++++ .../ddr/lpddr4_timing_ff020008.c | 1847 ++++++++++++++++ .../imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c | 69 + board/compulab/imx8mm-cl-iot-gate/spl.c | 187 ++ configs/imx8mm-cl-iot-gate_defconfig | 130 ++ include/configs/imx8mm-cl-iot-gate.h | 190 ++ 18 files changed, 8932 insertions(+) create mode 100644 arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-cl-iot-gate.dts create mode 100644 board/compulab/imx8mm-cl-iot-gate/Kconfig create mode 100644 board/compulab/imx8mm-cl-iot-gate/MAINTAINERS create mode 100644 board/compulab/imx8mm-cl-iot-gate/Makefile create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/Makefile create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c create mode 100644 board/compulab/imx8mm-cl-iot-gate/spl.c create mode 100644 configs/imx8mm-cl-iot-gate_defconfig create mode 100644 include/configs/imx8mm-cl-iot-gate.h -- 2.29.2

2 3

[PATCH 00/34] Sama7g5 Evaluation Kit support
by Eugen Hristev 06 Dec '20

06 Dec '20

Hello, This series adds support for sama7g5 SoC DT and the sama7g5ek board. I kept the original incremental development for this board, with each commit's author and designated change, for traceability and for easier reviewing. The series starts from a basic devicetree and ends with a fully functional board including SD-Card/MMC, i2c eeproms, ethernet. Thanks, Eugen Claudiu Beznea (20): board: atmel: sama7g5ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDR configs: sama7g5ek: set malloc pool to 68K configs: sama7g5ek: enable pll driver ARM: dts: sama7g5: move clock frequencies for xtals in board file ARM: dts: sama7g5: add slow rc and main rc oscillators ARM: dts: sama7g5: add u-boot,dm-pre-reloc bindings for xtals ARM: dts: sama7g5: add slow clock bindings ARM: dts: sama7g5: add PMC bindings ARM: dts: sama7g5: switch to PMC bindings configs: sama7g5: enable CONFIG_CPU ARM: dts: sama7g5: add CPU bindings configs: sama7g5: use PIT64B ARM: dts: sama7g5: enable autoboot ARM: dts: sama7g5: add pit64b support configs: sama7g5ek: enable mii command ARM: dts: sama7g5: add GMAC0 ARM: dts: sama7g5: add GMAC1 board: atmel: sama7g5ek: increase arp timeout and retry count configs: sama7g5ek: enable support for KSZ9131 configs: sama7g5ek: enable CCF Eugen Hristev (13): ARM: dts: sama7g5: add initial DT for sama7g5 SoC board: atmel: sama7g5ek: add initial support for sama7g5ek ARM: dts: at91: sama7g5: add pinctrl node ARM: dts: at91: sama7g5ek: add pinctrl for sdmmc1 and flx3 ARM: dts: at91: sama7g5: add assigned clocks for sdmmc1 ARM: dts: at91: sama7g5: add node for sdmmc0 ARM: dts: at91: sama7g5ek: enable sdmmc0 with pinctrl board: atmel: sama7g5ek: clean-up header bootcommand configs: sama7g5: add mmc config for sdmmc0 ARM: dts: at91: sama7g5: add flexcom1 and i2c subnode ARM: dts: sama7g5ek: add i2c1 bus and eeproms board: atmel: sama7g5ek: add support for MAC address retreival configs: sama7g5ek: add i2c and eeprom Nicolas Ferre (1): ARM: dts: sama7g5ek: fix TXC pin configuration arch/arm/dts/Makefile | 3 + arch/arm/dts/sama7g5.dtsi | 169 ++++++++++++++++++++++++ arch/arm/dts/sama7g5ek-u-boot.dtsi | 65 ++++++++++ arch/arm/dts/sama7g5ek.dts | 202 +++++++++++++++++++++++++++++ arch/arm/mach-at91/Kconfig | 8 ++ board/atmel/sama7g5ek/Kconfig | 15 +++ board/atmel/sama7g5ek/MAINTAINERS | 8 ++ board/atmel/sama7g5ek/Makefile | 7 + board/atmel/sama7g5ek/sama7g5ek.c | 76 +++++++++++ configs/sama7g5ek_mmc1_defconfig | 70 ++++++++++ configs/sama7g5ek_mmc_defconfig | 70 ++++++++++ include/configs/sama7g5ek.h | 45 +++++++ 12 files changed, 738 insertions(+) create mode 100644 arch/arm/dts/sama7g5.dtsi create mode 100644 arch/arm/dts/sama7g5ek-u-boot.dtsi create mode 100644 arch/arm/dts/sama7g5ek.dts create mode 100644 board/atmel/sama7g5ek/Kconfig create mode 100644 board/atmel/sama7g5ek/MAINTAINERS create mode 100644 board/atmel/sama7g5ek/Makefile create mode 100644 board/atmel/sama7g5ek/sama7g5ek.c create mode 100644 configs/sama7g5ek_mmc1_defconfig create mode 100644 configs/sama7g5ek_mmc_defconfig create mode 100644 include/configs/sama7g5ek.h -- 2.25.1

3 41

[PATCH] ARM: mx6: add support for USB armory Mk II board
by andrej.rosano＠f-secure.com 06 Dec '20

06 Dec '20

From: Andrej Rosano <andrej.rosano(a)f-secure.com> Add support for F-Secure USB armory Mk II board, an open source flash-drive sized computer based on Freescale i.MX6UL SoC. http://inversepath.com/usbarmory Signed-off-by: Andrej Rosano <andrej(a)inversepath.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-usbarmory.dts | 200 ++++++++++ arch/arm/mach-imx/mx6/Kconfig | 5 + board/inversepath/usbarmory-mark-two/Kconfig | 71 ++++ .../usbarmory-mark-two/MAINTAINERS | 6 + board/inversepath/usbarmory-mark-two/Makefile | 10 + .../usbarmory-mark-two/imximage-1gb.cfg | 87 +++++ .../usbarmory-mark-two/imximage-512mb.cfg | 89 +++++ .../usbarmory-mark-two/usbarmory-mark-two.c | 347 ++++++++++++++++++ configs/usbarmory-mark-two_defconfig | 72 ++++ include/configs/usbarmory-mark-two.h | 234 ++++++++++++ 11 files changed, 1122 insertions(+) create mode 100644 arch/arm/dts/imx6ull-usbarmory.dts create mode 100644 board/inversepath/usbarmory-mark-two/Kconfig create mode 100644 board/inversepath/usbarmory-mark-two/MAINTAINERS create mode 100644 board/inversepath/usbarmory-mark-two/Makefile create mode 100644 board/inversepath/usbarmory-mark-two/imximage-1gb.cfg create mode 100644 board/inversepath/usbarmory-mark-two/imximage-512mb.cfg create mode 100644 board/inversepath/usbarmory-mark-two/usbarmory-mark-two.c create mode 100644 configs/usbarmory-mark-two_defconfig create mode 100644 include/configs/usbarmory-mark-two.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b195723f16..d17c14c9bb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -731,6 +731,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ + imx6ull-usbarmory.dtb \ imx6ull-somlabs-visionsom.dtb \ imx6ulz-14x14-evk.dtb diff --git a/arch/arm/dts/imx6ull-usbarmory.dts b/arch/arm/dts/imx6ull-usbarmory.dts new file mode 100644 index 0000000000..d5a616f703 --- /dev/null +++ b/arch/arm/dts/imx6ull-usbarmory.dts @@ -0,0 +1,200 @@ +/* + * USB armory Mk II device tree file + * https://github.com/inversepath/usbarmory + * + * Copyright (C) 2019, F-Secure Corporation + * Andrej Rosano <andrej.rosano(a)f-secure.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ull.dtsi" + +/ { + model = "F-Secure USB armory Mk II"; + compatible = "inversepath,imx6ull-usbarmory-mkII", "fsl,imx6ull"; + + chosen { + stdout-path = &uart2; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-white { + label = "LED_WHITE"; + gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-blue { + label = "LED_BLUE"; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_regulator { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1250000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bluetooth>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + non-removable; // FIXME: CD works on i.MX6ULL but not i.MX6ULZ + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + non-removable; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_bluetooth: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b0 /* BT_UART_TX */ + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b0 /* BT_UART_RX */ + MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b0 /* BT_UART_CTS */ + MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x1b0b0 /* BT_UART_RTS */ + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x1f020 /* BT_UART_DSR */ + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1f020 /* BT_UART_DTR */ + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1f020 /* BT_SWDCLK */ + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1f020 /* BT_SWDIO */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1f020 /* BT_RESET */ + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x1f020 /* BT_SWITCH_1 */ + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1f020 /* BT_SWITCH_2 */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x1f020 + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x1f020 + >; + }; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + tpl-support; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + tpl-support; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3d72517fa1..36b5d46c4b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -644,6 +644,10 @@ config TARGET_UDOO_NEO select SUPPORT_SPL imply CMD_DM +config TARGET_USBARMORY_MARK_TWO + bool "Support USB armory Mk II" + depends on MX6ULL + config TARGET_SOFTING_VINING_2000 bool "Softing VIN|ING 2000" depends on MX6SX @@ -744,6 +748,7 @@ source "board/phytec/pcm058/Kconfig" source "board/phytec/pfla02/Kconfig" source "board/phytec/pcl063/Kconfig" source "board/gateworks/gw_ventana/Kconfig" +source "board/inversepath/usbarmory-mark-two/Kconfig" source "board/kosagi/novena/Kconfig" source "board/softing/vining_2000/Kconfig" source "board/liebherr/display5/Kconfig" diff --git a/board/inversepath/usbarmory-mark-two/Kconfig b/board/inversepath/usbarmory-mark-two/Kconfig new file mode 100644 index 0000000000..e13290b9a1 --- /dev/null +++ b/board/inversepath/usbarmory-mark-two/Kconfig @@ -0,0 +1,71 @@ +if TARGET_USBARMORY_MARK_TWO + +choice + prompt "DDR size" + default SYS_DDR_512MB + +config SYS_DDR_512MB + bool "512 MB" + +config SYS_DDR_1GB + bool "1 GB" + +endchoice + +choice + prompt "Boot device" + default SYS_BOOT_DEV_MICROSD + +config SYS_BOOT_DEV_MICROSD + bool "micro SD" + +config SYS_BOOT_DEV_EMMC + bool "eMMC" + +endchoice + +choice + prompt "Boot mode" + default SYS_BOOT_MODE_NORMAL + +config SYS_BOOT_MODE_NORMAL + select DISTRO_DEFAULTS + select ENV_IS_IN_MMC + bool "Normal" + +config SYS_BOOT_MODE_UMS + bool "UMS" + select ENV_IS_NOWHERE + +config SYS_BOOT_MODE_TFTP + bool "TFTP" + select ENV_IS_NOWHERE + +config SYS_BOOT_MODE_VERIFIED_OPEN + bool "Verified Boot" + select ENV_IS_NOWHERE + +config SYS_BOOT_MODE_VERIFIED_LOCKED + bool "Verified Boot and console disabled" + select ENV_IS_NOWHERE + +endchoice + +config IMX_CONFIG + default "board/inversepath/usbarmory-mark-two/imximage-512mb.cfg" if SYS_DDR_512MB + default "board/inversepath/usbarmory-mark-two/imximage-1gb.cfg" if SYS_DDR_1GB + +config SYS_MEMTEST_END + default 0xa0000000 if SYS_DDR_512MB + default 0xc0000000 if SYS_DDR_1G + +config SYS_BOARD + default "usbarmory-mark-two" + +config SYS_VENDOR + default "inversepath" + +config SYS_CONFIG_NAME + default "usbarmory-mark-two" + +endif diff --git a/board/inversepath/usbarmory-mark-two/MAINTAINERS b/board/inversepath/usbarmory-mark-two/MAINTAINERS new file mode 100644 index 0000000000..89b68ae866 --- /dev/null +++ b/board/inversepath/usbarmory-mark-two/MAINTAINERS @@ -0,0 +1,6 @@ +USBARMORY MK II BOARD +M: Andrej Rosano <andrej.rosano(a)f-secure.com> +S: Maintained +F: board/inversepath/usbarmory-mark-two/ +F: include/configs/usbarmory-mark-two.h +F: configs/usbarmory-mark-two_defconfig diff --git a/board/inversepath/usbarmory-mark-two/Makefile b/board/inversepath/usbarmory-mark-two/Makefile new file mode 100644 index 0000000000..bf84d05bfd --- /dev/null +++ b/board/inversepath/usbarmory-mark-two/Makefile @@ -0,0 +1,10 @@ +# +# USB armory Mk II board Makefile +# https://github.com/inversepath/usbarmory +# +# Copyright (C) 2019, F-Secure +# Andrej Rosano <andrej.rosano(a)f-secure.com> +# +# SPDX-License-Identifier:|____GPL-2.0+ + +obj-y := usbarmory-mark-two.o diff --git a/board/inversepath/usbarmory-mark-two/imximage-1gb.cfg b/board/inversepath/usbarmory-mark-two/imximage-1gb.cfg new file mode 100644 index 0000000000..47bd4830f7 --- /dev/null +++ b/board/inversepath/usbarmory-mark-two/imximage-1gb.cfg @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * USB armory Mk II board imximage configuration + * https://github.com/inversepath/usbarmory + * + * Copyright (C) 2019, F-Secure Corportation + * Andrej Rosano <andrej.rosano(a)f-secure.com> + */ + +#define __ASSEMBLY__ +#include <config.h> + +IMAGE_VERSION 2 +BOOT_FROM sd +CSF CONFIG_CSF_SIZE + +/* CCM */ + +DATA 4 0x020c4068 0xffffffff /* CCM_CCGR0 */ +DATA 4 0x020c406c 0xffffffff /* CCM_CCGR1 */ +DATA 4 0x020c4070 0xffffffff /* CCM_CCGR2 */ +DATA 4 0x020c4074 0xffffffff /* CCM_CCGR3 */ +DATA 4 0x020c4078 0xffffffff /* CCM_CCGR4 */ +DATA 4 0x020c407c 0xffffffff /* CCM_CCGR5 */ +DATA 4 0x020c4080 0xffffffff /* CCM_CCGR6 */ + +/* IOMUX */ + +DATA 4 0x020E04B4 0x000C0000 /* GRP_DDR_TYPE */ +DATA 4 0x020E04AC 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x020E027C 0x00000030 /* DRAM_SDCLK0_P */ +DATA 4 0x020E0250 0x00000030 /* DRAM_CAS_B */ +DATA 4 0x020E024C 0x00000030 /* DRAM_RAS_B */ +DATA 4 0x020E0490 0x00000030 /* GRP_ADDDS */ +DATA 4 0x020E0288 0x00000030 /* DRAM_RESET */ +DATA 4 0x020E0270 0x00000000 /* DRAM_SDBA2 */ +DATA 4 0x020E0260 0x00000030 /* DRAM_ODT0 */ +DATA 4 0x020E0264 0x00000030 /* DRAM_ODT1 */ +DATA 4 0x020E04A0 0x00000030 /* GRP_CTLDS */ +DATA 4 0x020E0494 0x00020000 /* GRP_DDRMODE_CTL */ +DATA 4 0x020E0280 0x00000030 /* DRAM_SDQS0_P */ +DATA 4 0x020E0284 0x00000030 /* DRAM_SDQS1_P */ +DATA 4 0x020E04B0 0x00020000 /* GRP_DDRMODE */ +DATA 4 0x020E0498 0x00000030 /* GRP_B0DS */ +DATA 4 0x020E04A4 0x00000030 /* GRP_B1DS */ +DATA 4 0x020E0244 0x00000030 /* DRAM_DQM0 */ +DATA 4 0x020E0248 0x00000030 /* DRAM_DQM1 */ + +/* MMDC */ + +DATA 4 0x021B001C 0x00008000 /* MMDC_MDSCR */ +DATA 4 0x021B000C 0x676B52F3 /* MMDC_MDCFG0 */ +DATA 4 0x021B0010 0xB66D0B63 /* MMDC_MDCFG1 */ +DATA 4 0x021B0014 0x01FF00DB /* MMDC_MDCFG2 */ +DATA 4 0x021B0008 0x1B333030 /* MMDC_MDOTC */ +DATA 4 0x021B0018 0x00201740 /* MMDC_MDMISC */ +DATA 4 0x021B002C 0x000026D2 /* MMDC_MDRWD */ +DATA 4 0x021B0040 0x0000005F /* MMDC_MDASP */ +DATA 4 0x021B0030 0x006B1023 /* MMDC_MDOR */ +DATA 4 0x021B0000 0x85180000 /* MMDC_MDCTL */ + +/* Calibration */ +DATA 4 0x021B0800 0xA1390003 /* MMDC_MPZQHWCTRL */ +DATA 4 0x021B080C 0x00100014 /* MMDC_MPWLDECTRL0 */ +DATA 4 0x021B083C 0x415C015C /* MMDC_MPDGCTRL0 */ +DATA 4 0x021B0848 0x40403A40 /* MMDC_MPRDDLCTL */ +DATA 4 0x021B0850 0x40402626 /* MMDC_MPWRDLCTL */ +DATA 4 0x021B081C 0x33333333 /* MMDC_MPRDDQBY0DL */ +DATA 4 0x021B0820 0x33333333 /* MMDC_MPRDDQBY1DL */ +DATA 4 0x021B082C 0xf3333333 /* MMDC_MPWRDQBY0DL */ +DATA 4 0x021B0830 0xf3333333 /* MMDC_MPWRDQBY1DL */ +DATA 4 0x021B08C0 0x00921012 /* MMDC_MPDCCR */ +DATA 4 0x021B08B8 0x00000800 /* MMDC_MPMUR0 */ + +/* JEDEC initialization sequence */ +DATA 4 0x021B001C 0x02008032 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x00008033 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x00048031 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x15208030 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x04008040 /* MMDC_MDSCR */ + +DATA 4 0x021B0004 0x0002556D /* MMDC_MDPDC */ +DATA 4 0x021B0404 0x00011006 /* MMDC_MAPSR */ +DATA 4 0x021B0020 0x00000800 /* MMDC_MDREF */ +DATA 4 0x021B0818 0x00000227 /* MMDC_MPODTCTRL */ + +DATA 4 0x021B001C 0x00000000 /* MMDC_MDSCR */ diff --git a/board/inversepath/usbarmory-mark-two/imximage-512mb.cfg b/board/inversepath/usbarmory-mark-two/imximage-512mb.cfg new file mode 100644 index 0000000000..b856481b08 --- /dev/null +++ b/board/inversepath/usbarmory-mark-two/imximage-512mb.cfg @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * USB armory Mk II board imximage configuration + * https://github.com/inversepath/usbarmory + * + * Copyright (C) 2019, F-Secure Corportation + * Andrej Rosano <andrej.rosano(a)f-secure.com> + */ + +#define __ASSEMBLY__ +#include <config.h> + +IMAGE_VERSION 2 +BOOT_FROM sd +CSF CONFIG_CSF_SIZE + +/* CCM */ + +DATA 4 0x020c4068 0xffffffff /* CCM_CCGR0 */ +DATA 4 0x020c406c 0xffffffff /* CCM_CCGR1 */ +DATA 4 0x020c4070 0xffffffff /* CCM_CCGR2 */ +DATA 4 0x020c4074 0xffffffff /* CCM_CCGR3 */ +DATA 4 0x020c4078 0xffffffff /* CCM_CCGR4 */ +DATA 4 0x020c407c 0xffffffff /* CCM_CCGR5 */ +DATA 4 0x020c4080 0xffffffff /* CCM_CCGR6 */ + +/* IOMUX */ + +DATA 4 0x020E04B4 0x000C0000 /* GRP_DDR_TYPE */ +DATA 4 0x020E04AC 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x020E027C 0x00000030 /* DRAM_SDCLK0_P */ +DATA 4 0x020E0250 0x00000030 /* DRAM_CAS_B */ +DATA 4 0x020E024C 0x00000030 /* DRAM_RAS_B */ +DATA 4 0x020E0490 0x00000030 /* GRP_ADDDS */ +DATA 4 0x020E0288 0x00000030 /* DRAM_RESET */ +DATA 4 0x020E0270 0x00000000 /* DRAM_SDBA2 */ +DATA 4 0x020E0260 0x00000030 /* DRAM_ODT0 */ +DATA 4 0x020E0264 0x00000030 /* DRAM_ODT1 */ +DATA 4 0x020E04A0 0x00000030 /* GRP_CTLDS */ +DATA 4 0x020E0494 0x00020000 /* GRP_DDRMODE_CTL */ +DATA 4 0x020E0280 0x00000030 /* DRAM_SDQS0_P */ +DATA 4 0x020E0284 0x00000030 /* DRAM_SDQS1_P */ +DATA 4 0x020E04B0 0x00020000 /* GRP_DDRMODE */ +DATA 4 0x020E0498 0x00000030 /* GRP_B0DS */ +DATA 4 0x020E04A4 0x00000030 /* GRP_B1DS */ +DATA 4 0x020E0244 0x00000030 /* DRAM_DQM0 */ +DATA 4 0x020E0248 0x00000030 /* DRAM_DQM1 */ + +/* MMDC */ + +DATA 4 0x021B001C 0x00008000 /* MMDC_MDSCR */ +DATA 4 0x021B000C 0x676B52F3 /* MMDC_MDCFG0 */ +DATA 4 0x021B0010 0xB66D0B63 /* MMDC_MDCFG1 */ +DATA 4 0x021B0014 0x01FF00DB /* MMDC_MDCFG2 */ +DATA 4 0x021B0008 0x1B333030 /* MMDC_MDOTC */ +DATA 4 0x021B0018 0x00201740 /* MMDC_MDMISC */ +DATA 4 0x021B002C 0x000026D2 /* MMDC_MDRWD */ +DATA 4 0x021B0040 0x0000004F /* MMDC_MDASP */ +DATA 4 0x021B0030 0x006B1023 /* MMDC_MDOR */ +DATA 4 0x021B0000 0x84180000 /* MMDC_MDCTL */ + +/* Calibration */ +DATA 4 0x021B0800 0xA1390003 /* MMDC_MPZQHWCTRL */ +DATA 4 0x021B080C 0x000D000F /* MMDC_MPWLDECTRL0 */ +DATA 4 0x021B0810 0x00100010 /* MMDC_MPWLDECTRL1 */ +DATA 4 0x021B083C 0x415C0160 /* MMDC_MPDGCTRL0 */ +DATA 4 0x021B0840 0x00000000 /* MMDC_MPDGCTRL1 */ +DATA 4 0x021B0848 0x40403C42 /* MMDC_MPRDDLCTL */ +DATA 4 0x021B0850 0x40402C26 /* MMDC_MPWRDLCTL */ +DATA 4 0x021B081C 0x33333333 /* MMDC_MPRDDQBY0DL */ +DATA 4 0x021B0820 0x33333333 /* MMDC_MPRDDQBY1DL */ +DATA 4 0x021B082C 0xf3333333 /* MMDC_MPWRDQBY0DL */ +DATA 4 0x021B0830 0xf3333333 /* MMDC_MPWRDQBY1DL */ +DATA 4 0x021B08C0 0x00921012 /* MMDC_MPDCCR */ +DATA 4 0x021B08B8 0x00000800 /* MMDC_MPMUR0 */ + +/* JEDEC initialization sequence */ +DATA 4 0x021B001C 0x02008032 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x00008033 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x00048031 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x15208030 /* MMDC_MDSCR */ +DATA 4 0x021B001C 0x04008040 /* MMDC_MDSCR */ + +DATA 4 0x021B0004 0x0002556D /* MMDC_MDPDC */ +DATA 4 0x021B0404 0x00011006 /* MMDC_MAPSR */ +DATA 4 0x021B0020 0x00000800 /* MMDC_MDREF */ +DATA 4 0x021B0818 0x00000227 /* MMDC_MPODTCTRL */ + +DATA 4 0x021B001C 0x00000000 /* MMDC_MDSCR */ diff --git a/board/inversepath/usbarmory-mark-two/usbarmory-mark-two.c b/board/inversepath/usbarmory-mark-two/usbarmory-mark-two.c new file mode 100644 index 0000000000..97723992ba --- /dev/null +++ b/board/inversepath/usbarmory-mark-two/usbarmory-mark-two.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * USB armory Mk II board initialization + * https://github.com/inversepath/usbarmory + * + * Copyright (C) 2019, F-Secure Corporation + * Andrej Rosano <andrej.rosano(a)f-secure.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/mach-imx/iomux-v3.h> +#include <linux/errno.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc_imx.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP || \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS || \ + PAD_CTL_SRE_SLOW) +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define PAD_JTAG (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) +#define PAD_JTAG_TDO (PAD_CTL_PKE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_60ohm | PAD_CTL_SRE_FAST) +#define PAD_JTAG_MOD (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_60ohm) + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t pads[] = { +#ifndef CONFIG_SYS_BOOT_MODE_VERIFIED_LOCKED + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART2_CTS_B__UART2_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART2_RTS_B__UART2_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL) +#else + MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_UART2_CTS_B__GPIO1_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_UART2_RTS_B__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) +#endif + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t pads[] = { + MX6_PAD_GPIO1_IO02__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + MX6_PAD_GPIO1_IO03__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_mmc(void) +{ + static const iomux_v3_cfg_t pads[] = { + /* microSD */ + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* eMMC */ + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL) + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_misc(void) +{ + static const iomux_v3_cfg_t pads[] = { + /* type-c */ + MX6_PAD_GPIO1_IO00__GPIO1_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_GPIO1_IO01__GPIO1_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), + /* crypto */ + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), + /* pmic */ + MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(WEAK_PULLUP), + /* usb */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(WEAK_PULLUP) + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_jtag(void) +{ + static const iomux_v3_cfg_t pads[] = { +#ifndef CONFIG_SYS_BOOT_MODE_VERIFIED_LOCKED + MX6_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(PAD_JTAG), + MX6_PAD_JTAG_TRST_B__SJC_TRSTB | MUX_PAD_CTRL(PAD_JTAG), + MX6_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(PAD_JTAG), + MX6_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(PAD_JTAG_TDO), + MX6_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(PAD_JTAG), + MX6_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(PAD_JTAG_MOD), +#else + MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_JTAG_TRST_B__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_JTAG_TDI__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_JTAG_TDO__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_JTAG_TCK__GPIO1_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_JTAG_MOD__GPIO1_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), +#endif + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_unused_boot(void) +{ + static const iomux_v3_cfg_t pads[] = { + + /* pulled-up/pulled-down pads */ + MX6_PAD_LCD_DATA05__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_LCD_DATA11__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_LCD_DATA14__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_LCD_DATA08__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* floating and pulled-up pads */ + MX6_PAD_LCD_DATA00__GPIO3_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA01__GPIO3_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA02__GPIO3_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA03__GPIO3_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA04__GPIO3_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA06__GPIO3_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA07__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA09__GPIO3_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA10__GPIO3_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA12__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA13__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA15__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA16__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA17__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA18__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA19__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA20__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA21__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA22__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_DATA23__GPIO3_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_unused_nc(void) +{ + /* Out of reset values define the pin values before the + ROM is executed so we force all the not connected pins + to a known state */ + static const iomux_v3_cfg_t pads[] = { + + /* TAMPER pins */ + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), + // FIXME: Configuration of one of the following two pads + // disables console UART for some reason. + //MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), + //MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), + + /* ENET block */ + MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET1_RX_EN__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET1_RX_ER__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET2_RX_EN__GPIO2_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_ENET2_RX_ER__GPIO2_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + + /* CSI block */ + MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_VSYNC__GPIO4_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_HSYNC__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_DATA02__GPIO4_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_DATA03__GPIO4_IO24 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_DATA04__GPIO4_IO25 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_DATA06__GPIO4_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_CSI_DATA07__GPIO4_IO28 | MUX_PAD_CTRL(WEAK_PULLUP), + + /* GPIO block */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), + + /* NAND block */ + MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NAND_READY_B__GPIO4_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NAND_CE0_B__GPIO4_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_NAND_CLE__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLUP), + + /* LCD block */ + MX6_PAD_LCD_CLK__GPIO3_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_ENABLE__GPIO3_IO01 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_HSYNC__GPIO3_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_VSYNC__GPIO3_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + int ret = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]); + + return ret; +} + +int board_eth_init(struct bd_info *bis) +{ + return usb_eth_initialize(bis); +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +/* Enable FUSB303 receptacle Type-C controller */ +int fusb303_init(void) +{ + uchar val; + + val = 0xbb; + i2c_set_bus_num(0); + i2c_write(0x31, 0x5, 1, &val, 1); + return 0; +} + +int board_early_init_f(void) +{ + // i2c initialization should not be moved in dts as otherwise + // the fsusb303_init() does not have effect. + setup_iomux_i2c(); + setup_iomux_uart(); + setup_iomux_mmc(); + setup_iomux_unused_boot(); + setup_iomux_unused_nc(); + setup_iomux_misc(); + setup_iomux_jtag(); + return 0; +} + +int board_init(void) +{ + fusb303_init(); + return 0; +} + +int checkboard(void) +{ + puts("Board: F-Secure USB armory Mk II\n"); + return 0; +} + +#ifndef CONFIG_CMDLINE +static char *ext2_argv[] = { + "ext2load", + "mmc", + USBARMORY_BOOT_DEV ":1", + USBARMORY_FIT_ADDR, + USBARMORY_FIT_PATH, + USBARMORY_FIT_SIZE +}; + +static char *bootm_argv[] = { + "bootm", + USBARMORY_FIT_ADDR "#" USBARMORY_FIT_CONF +}; + +int board_run_command(const char *cmdline) +{ + if (do_ext2load(NULL, 0, 6, ext2_argv) != 0) { + hang(); + } + + do_bootm(NULL, 0, 2, bootm_argv); + hang(); + + return 1; +} +#endif diff --git a/configs/usbarmory-mark-two_defconfig b/configs/usbarmory-mark-two_defconfig new file mode 100644 index 0000000000..85600f86ff --- /dev/null +++ b/configs/usbarmory-mark-two_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_USBARMORY_MARK_TWO=y +CONFIG_MX6ULL=y + +CONFIG_SYS_DDR_512MB=y +# CONFIG_SYS_DDR_1GB is not set + +# Boot device +CONFIG_SYS_BOOT_DEV_MICROSD=y +# CONFIG_SYS_BOOT_DEV_EMMC is not set + +# Environment +CONFIG_ENV_OFFSET=0x100000 +CONFIG_ENV_SIZE=0x2000 + +# Boot mode +CONFIG_SYS_BOOT_MODE_NORMAL=y +# CONFIG_SYS_BOOT_MODE_UMS is not set +# CONFIG_SYS_BOOT_MODE_TFTP is not set +# CONFIG_SYS_BOOT_MODE_VERIFIED_OPEN is not set +# CONFIG_SYS_BOOT_MODE_VERIFIED_LOCKED is not set + +CONFIG_NR_DRAM_BANKS=1 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_DOS_PARTITION=y +CONFIG_FSL_USDHC=y +CONFIG_SYS_MEMTEST_START=0x80000000 + +# Commands +CONFIG_CMD_DHCP=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_USB=y + +# Device model support +CONFIG_DM=y +CONFIG_DM_MMC=y +CONFIG_DM_USB=y +CONFIG_BLK=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-usbarmory" + +# Secure/Verified boot +CONFIG_FSL_CAAM=y +CONFIG_IMX_HAB=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_RSA=y + +# USB gadgets +CONFIG_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# UMS gadget +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_CMD_USB_MASS_STORAGE=y + +# Ethernet gadget +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y diff --git a/include/configs/usbarmory-mark-two.h b/include/configs/usbarmory-mark-two.h new file mode 100644 index 0000000000..4ad19fa8f5 --- /dev/null +++ b/include/configs/usbarmory-mark-two.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * USB armory Mk II board configuration settings + * https://github.com/inversepath/usbarmory + * + * Copyright (C) 2019, F-Secure Corporation + * Andrej Rosano <andrej.rosano(a)f-secure.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include "mx6_common.h" + +#define CONFIG_BOARD_EARLY_INIT_F + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* USB */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USBD_HS + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 + +/* U-Boot memory offsets */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Boot parameters */ +#define USBARMORY_FIT_PATH "/boot/usbarmory.itb" +#define USBARMORY_FIT_ADDR "0x80800000" +#define USBARMORY_FIT_CONF "conf-1" +#define USBARMORY_FIT_SIZE "0x4000000" + +#ifdef CONFIG_SYS_BOOT_DEV_MICROSD +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define USBARMORY_BOOT_DEV "0" +#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) +#elif CONFIG_SYS_BOOT_DEV_EMMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define USBARMORY_BOOT_DEV "1" +#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 1) +#endif + +/* Bootargs */ + +#define CONFIG_USE_BOOTARGS +#define CONFIG_BOOTARGS "console=ttymxc1,115200 root=/dev/mmcblk" USBARMORY_BOOT_DEV "p1 rootwait rw" + +#define CONFIG_HOSTNAME "usbarmory" +#define CONFIG_SYS_CBSIZE 512 + +/* DDR size config */ + +#ifdef CONFIG_SYS_DDR_1GB +#define BOOTENV_DDR_1GB \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" +#else +#define BOOTENV_DDR_1GB +#endif + +/* scripts */ + +#define BOOTENV_CHECK_SILICON_REVISION \ + "check_silicon_revision=" \ + "echo *** Checking Silicon Revision *** ; " \ + "setexpr USB_ANALOG_DIGPROG *0x20c8260 ; " \ + "setexpr imx6_family $USB_ANALOG_DIGPROG '/' 0x10000 ; " \ + "setexpr silicon_revision $USB_ANALOG_DIGPROG '&' 0xffff ; " \ + "if itest $imx6_family == 0x64; then " \ + "if itest $silicon_revision < 0x0002; then " \ + "echo ; " \ + "echo \"***********************************************\" ; " \ + "echo \"* WARNING *\" ; " \ + "echo \"* i.MX6UltraLight with Silicon Revision < 1.2 *\" ; " \ + "echo \"* Important security fixes are missing *\" ; " \ + "echo \"***********************************************\" ; " \ + "echo ; " \ + "fi ; " \ + "fi ; " \ + "if itest $imx6_family == 0x65; then " \ + "if itest $silicon_revision < 0x0001; then " \ + "echo ; " \ + "echo \"********************************************\" ; " \ + "echo \"* WARNING *\" ; " \ + "echo \"* i.MX6ULL/ULZ with Silicon Revision < 1.1 *\" ; " \ + "echo \"* Important security fixes are missing *\" ; " \ + "echo \"********************************************\" ; " \ + "echo ; " \ + "fi ; " \ + "fi\0" + +#define BOOTENV_CHECK_OTPMK \ + "check_otpmk=" \ + "echo *** Checking OTPMK *** ; " \ + "env set check_otpmk_var 0 ; " \ + "setexpr SNVS_HPSR *0x020cc014 ; " \ + "setexpr test $SNVS_HPSR '&' 0x08000000 ; " \ + "if itest $test != 0; then " \ + "env set check_otpmk_var 1 ; " \ + "echo ; " \ + "echo \"**************************\" ; " \ + "echo \"* WARNING: OTPMK is zero *\" ; " \ + "echo \"**************************\" ; " \ + "echo ; " \ + "fi ; " \ + "setexpr test $SNVS_HPSR '&' 0x01FF0000 ; " \ + "if itest $test != 0; then " \ + "env set check_otpmk_var 1 ; " \ + "echo ; " \ + "echo \"******************************************\" ; " \ + "echo \"* WARNING: OTPMK_SYNDROME error detected *\" ; " \ + "echo \"******************************************\" ; " \ + "echo ; " \ + "fi ; " \ + "setexpr test $SNVS_HPSR '&' 0xF00 ; " \ + "if itest $test != 0xD00; then " \ + "env set check_otpmk_var 1 ; " \ + "echo ; " \ + "echo \"***************************************\" ; " \ + "echo \"* WARNING: Device not in TRUSTED mode *\" ; " \ + "echo \"***************************************\" ; " \ + "echo ; " \ + "fi ; " \ + "if itest $check_otpmk_var != 0; then " \ + "echo *** Unable to continue. Resetting in 60s *** ; " \ + "sleep 60 ; " \ + "reset ; " \ + "fi\0" + +#define BOOTENV_UMS \ + "start_ums=" \ + "ums 0 mmc ${mmcdev}\0" + +#define BOOTENV_TFTP \ + "start_tftp=" \ + "dhcp ${kernel_addr_r} ${serverip}:${bootfile} ; " \ + "dhcp ${fdt_addr_r} ${serverip}:${fdtfile} ; " \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" + +#define BOOTENV_VERIFIED_OPEN \ + "start_verified_open=" \ + "ext2load mmc ${mmcdev}:1 " USBARMORY_FIT_ADDR " " USBARMORY_FIT_PATH " " USBARMORY_FIT_SIZE " ; " \ + "bootm " USBARMORY_FIT_ADDR "#" USBARMORY_FIT_CONF "\0" + +#define BOOTENV_NORMAL \ + "start_normal=run distro_bootcmd ; " \ + "ext2load mmc ${mmcdev}:1 ${kernel_addr_r} /boot/${bootfile} ; "\ + "ext2load mmc ${mmcdev}:1 ${fdt_addr_r} /boot/${fdtfile} ; " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" + +/* Boot modes */ + +#ifdef CONFIG_SYS_BOOT_MODE_UMS + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run start_ums" + +#elif CONFIG_SYS_BOOT_MODE_VERIFIED_OPEN + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run start_verified_open" + +#elif CONFIG_SYS_BOOT_MODE_TFTP + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run start_tftp" + +#elif CONFIG_SYS_BOOT_MODE_NORMAL + +#include <config_distro_bootcmd.h> +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run start_normal" + +#elif CONFIG_SYS_BOOT_MODE_VERIFIED_LOCKED + +#undef CONFIG_CMDLINE +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY -2 + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "dummy" + +#endif + +/* Custom environment variables */ + +#ifndef BOOTENV +#define BOOTENV +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x80800000\0" \ + "fdt_addr_r=0x82000000\0" \ + "scriptaddr=0x80800000\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "bootfile=zImage\0" \ + "fdtfile=imx6ull-usbarmory.dtb\0" \ + "mmcdev=" USBARMORY_BOOT_DEV "\0" \ + "ethact=usb_ether\0" \ + "cdc_connect_timeout=60\0" \ + "usbnet_devaddr=1a:55:89:a2:69:52\0" \ + "usbnet_hostaddr=1a:55:89:a2:69:51\0" \ + BOOTENV_CHECK_SILICON_REVISION \ + BOOTENV_CHECK_OTPMK \ + BOOTENV_NORMAL \ + BOOTENV_TFTP \ + BOOTENV_UMS \ + BOOTENV_VERIFIED_OPEN \ + BOOTENV_DDR_1GB \ + BOOTENV + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#endif /* __CONFIG_H */ -- 2.28.0

2 1

[PATCH v2] imx: Add support for Ronetix's i.MX7-CM board.
by Ilko Iliev 06 Dec '20

06 Dec '20

Supported peripherals: ETH, SD, eMMC, USB, I2C EEPROM, PMIC, QSPI Nor Flash. U-Boot 2020.07-00611-g1fc3bcb2ee-dirty (Jul 13 2020 - 15:25:49 +0200) CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 39C Reset cause: POR Model: Ronetix i.MX7-CM Board Board: i.MX7-CM in non-secure mode DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Signed-off-by: Ilko Iliev <iliev(a)ronetix.at> Changes for v2: - support for i.MX7-CM v2.0 - applicable to the current master branch --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7-cm.dts | 674 +++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7/Kconfig | 10 +- board/ronetix/imx7-cm/Kconfig | 12 + board/ronetix/imx7-cm/MAINTAINERS | 6 + board/ronetix/imx7-cm/Makefile | 4 + board/ronetix/imx7-cm/imx7-cm.c | 210 +++++++++ board/ronetix/imx7-cm/imximage.cfg | 104 +++++ configs/imx7_cm_defconfig | 97 +++++ include/configs/imx7-cm.h | 157 +++++++ 10 files changed, 1275 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx7-cm.dts create mode 100644 board/ronetix/imx7-cm/Kconfig create mode 100644 board/ronetix/imx7-cm/MAINTAINERS create mode 100644 board/ronetix/imx7-cm/Makefile create mode 100644 board/ronetix/imx7-cm/imx7-cm.c create mode 100644 board/ronetix/imx7-cm/imximage.cfg create mode 100644 configs/imx7_cm_defconfig create mode 100644 include/configs/imx7-cm.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d839cb49b3..7a134190e5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -730,7 +730,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7s-warp.dtb \ imx7d-meerkat96.dtb \ imx7d-pico-pi.dtb \ - imx7d-pico-hobbit.dtb + imx7d-pico-hobbit.dtb \ + imx7-cm.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ diff --git a/arch/arm/dts/imx7-cm.dts b/arch/arm/dts/imx7-cm.dts new file mode 100644 index 0000000000..1938a1829d --- /dev/null +++ b/arch/arm/dts/imx7-cm.dts @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Ronetix i.MX7-CM Board"; + compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sd1_vmmc: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + enable-active-high; + }; + + reg_sd2_vmmc: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_vmmc_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + enable-active-high; + }; + + reg_can2_3v3: regulator-can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; +}; + +&adc1 { + vref-supply = <&reg_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <&reg_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <&ethphy0>; + fsl,magic-packet; + phy-reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* + * The skew settings should be in the ethernet-phy subnode, but + * currently this doesn't work. + * + * All skews are offset since hardware skew values for the ksz9031 + * range from a negative skew to a positive skew. The increment + * step is 60ps. + * See the micrel-ksz90x1.txt Documentation file for details. + */ + + /* -900ps up t0 +960ps + * 0 (reg val 0) -> -900 ps + * 900 (reg val 15) -> 0 ps + * 1860 (reg val 31) -> +960 ps + * + */ + rxc-skew-ps = <1860>; /* */ + txc-skew-ps = <1860>; /* */ + + /* -420ps up to 480ps + * 0 (reg val 0) -> -420 ps + * 420 (reg val 7) -> 0 ps + * 900 (reg val 15) -> +480 ps + * */ + txd0-skew-ps = <420>; /* 0 ps */ + txd1-skew-ps = <420>; /* 0 ps */ + txd2-skew-ps = <420>; /* 0 ps */ + txd3-skew-ps = <420>; /* 0 ps */ + rxd0-skew-ps = <420>; /* 0 ps */ + rxd1-skew-ps = <420>; /* 0 ps */ + rxd2-skew-ps = <420>; /* 0 ps */ + rxd3-skew-ps = <420>; /* 0 ps */ + txen-skew-ps = <420>; /* 0 ps */ + rxdv-skew-ps = <420>; /* 0 ps */ + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <1>; + }; + + ethphy1: ethernet-phy@1 { + reg = <2>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <&ethphy1>; + fsl,magic-packet; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <&reg_can2_3v3>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + i2c_eeprom: i2c_eeprom@50 { + compatible = "microchip,24lc512"; + reg = <0x50>; + }; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + wlf,shared-lrclk; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <&reg_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <&reg_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + vmmc-supply = <&reg_sd1_vmmc>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + wakeup-source; + keep-power-in-suspend; + non-removable; + vmmc-supply = <&reg_sd2_vmmc>; + fsl,tuning-step = <2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx7d-sdb { + pinctrl_sd2_vmmc_reg: pinctrl_sd2_vmmc_reg { + fsl,pins = < + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 /* WL_REG_ON */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* ETH_RESET */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; +}; + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25l25645g"; + spi-max-frequency = <29000000>; + /* take off one dummy cycle */ + spi-nor,ddr-quad-read-dummy = <5>; + reg = <0>; + }; +}; diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index c8146c3509..64c15cbc07 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -76,6 +76,14 @@ config TARGET_COLIBRI_IMX7 select DM_THERMAL imply CMD_DM +config TARGET_IMX7_CM + bool "imx7-cm" + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select MX7D + imply CMD_DM + endchoice config SYS_SOC @@ -87,5 +95,5 @@ source "board/novtech/meerkat96/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" - +source "board/ronetix/imx7-cm/Kconfig" endif diff --git a/board/ronetix/imx7-cm/Kconfig b/board/ronetix/imx7-cm/Kconfig new file mode 100644 index 0000000000..ef7565419f --- /dev/null +++ b/board/ronetix/imx7-cm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX7_CM + +config SYS_BOARD + default "imx7-cm" + +config SYS_VENDOR + default "ronetix" + +config SYS_CONFIG_NAME + default "imx7-cm" + +endif diff --git a/board/ronetix/imx7-cm/MAINTAINERS b/board/ronetix/imx7-cm/MAINTAINERS new file mode 100644 index 0000000000..5faa2c5c8b --- /dev/null +++ b/board/ronetix/imx7-cm/MAINTAINERS @@ -0,0 +1,6 @@ +IMX7-CM BOARD +M: Ilko Iliev <iliev(a)ronetix.at> +S: Maintained +F: board/ronetix/imx7-cm/ +F: include/configs/imx7-cm.h +F: configs/imx7-cm_defconfig diff --git a/board/ronetix/imx7-cm/Makefile b/board/ronetix/imx7-cm/Makefile new file mode 100644 index 0000000000..34021b00fd --- /dev/null +++ b/board/ronetix/imx7-cm/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2015 Freescale Semiconductor, Inc. + +obj-y := imx7-cm.o diff --git a/board/ronetix/imx7-cm/imx7-cm.c b/board/ronetix/imx7-cm/imx7-cm.c new file mode 100644 index 0000000000..b8888f4eae --- /dev/null +++ b/board/ronetix/imx7-cm/imx7-cm.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#include <init.h> +#include <net.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx7-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <common.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <miiphy.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../../freescale/common/pfuze.h" +#include <i2c.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/crm_regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* status LED */ +#define GPIO_LED_STATUS IMX_GPIO_NR(2, 7) + +/* reset PHY */ +#define GPIO_PHY_RESET IMX_GPIO_NR(2, 4) + +/* LCD back light enable: 1- ON, 0 - OFF */ +#define GPIO_LCD_BL_EN IMX_GPIO_NR(1, 13) + +/* LCD back light PWM */ +#define GPIO_LCD_BL_PWM IMX_GPIO_NR(1, 1) + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_mmc_get_env_dev(int devno) +{ + if (devno == 2) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (dev_no == 1) + dev_no++; + + return dev_no; +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + int ret; + unsigned int gpio = GPIO_PHY_RESET; + + ret = gpio_request(gpio, "fec_rst"); + if (ret && ret != -EBUSY) { + printf("gpio: requesting pin %u failed\n", gpio); + return ret; + } + + gpio_direction_output(gpio, 0); + udelay(500); + gpio_direction_output(gpio, 1); + udelay(10000); + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + + return set_clk_enet(ENET_125MHZ); +} +#endif + +#ifdef CONFIG_FSL_QSPI +int board_qspi_init(void) +{ + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* turn ON the status LED */ + gpio_request(GPIO_LED_STATUS, "LED status"); + gpio_direction_output(GPIO_LED_STATUS, 0); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + + /* + * Set the voltage of VLDO4 output to 2.8V which feeds + * the MIPI DSI and MIPI CSI inputs. + */ + pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); + + return 0; +} +#endif + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); + + return 0; +} + +int checkboard(void) +{ + char *mode; + + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) + mode = "secure"; + else + mode = "non-secure"; + + printf("Board: i.MX7-CM in %s mode\n", mode); + + return 0; +} diff --git a/board/ronetix/imx7-cm/imximage.cfg b/board/ronetix/imx7-cm/imximage.cfg new file mode 100644 index 0000000000..af46ebc671 --- /dev/null +++ b/board/ronetix/imx7-cm/imximage.cfg @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : sd + */ + +BOOT_FROM sd + +/* + * Secure boot support + */ +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x0A0A0A0A +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig new file mode 100644 index 0000000000..92d7c10da5 --- /dev/null +++ b/configs/imx7_cm_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_IMX7_CM=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx7-cm/imximage.cfg" +CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7-cm" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_DM_VIDEO=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h new file mode 100644 index 0000000000..07850fe65c --- /dev/null +++ b/include/configs/imx7-cm.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D SABRESD board. + */ + +#ifndef __MX7D_SABRESD_CONFIG_H +#define __MX7D_SABRESD_CONFIG_H + +#include "mx7_common.h" + +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_IMX_BOOTAUX +/* Set to QSPI1 A flash at default */ +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=image raw 0 0x800000;"\ + "u-boot raw 0 0x4000;"\ + "bootimg part 0 1;"\ + "rootfs part 0 2\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + CONFIG_MFG_ENV_SETTINGS \ + CONFIG_DFU_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ + "initrd_high=0xffffffff\0" \ + "fdtfile=imx7-cm.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83100000\0" \ + "ramdiskaddr=0x83100000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) \ + func(PXE, pxe, na) + +#include <config_distro_bootcmd.h> + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment organization */ + +/* + * If want to use nand, define CONFIG_NAND_MXS and rework board + * to support nand, since emmc has pin conflicts with nand + */ +#ifdef CONFIG_NAND_MXS +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#define CONFIG_IMX_THERMAL + +#define CONFIG_USBD_HS + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#endif /* __CONFIG_H */ -- 2.25.1

2 1

[PATCH v1 1/2] imx: imx8qm_rom7720: added missing USDHC Base address defines
by Oliver Graute 06 Dec '20

06 Dec '20

Added missing USDHC Base address defines Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Ye Li <ye.li(a)nxp.com> Cc: uboot-imx <uboot-imx(a)nxp.com> --- include/configs/imx8qm_rom7720.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 865863eb7c..8e1427da8a 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -18,6 +18,10 @@ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_ENV_OVERWRITE -- 2.17.1

4 6

About the commit imx: mx6ull: update the REFTOP_VBGADJ setting
by Michael Nazzareno Trimarchi 06 Dec '20

06 Dec '20

Hi Peng I have a design with imx6ull that is running properly according to the manufacturer with the old REFTOP_VBGA set BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ,. With this commit, the TJunction of the CPU is around 8 degree more than without. The commit message does not provide any info According to the design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Can someone describe to me better? The device needs to run in a very hot environment and 10 to 8 degrees on the junction are really important. In the same environment: temp without this patch 34 temp with is 43 Register value is 0x240080E8 and 0x24008088 Michael -- Michael Nazzareno Trimarchi Amarula Solutions BV COO Co-Founder Cruquiuskade 47 Amsterdam 1018 AM NL T. +31(0)851119172 M. +39(0)3479132170 [`as] https://www.amarulasolutions.com

1 1

Crash on Raspberry Pi 4 if my USB Keyboard is connected
by Pascal Terjan 05 Dec '20

05 Dec '20

Here is the boot log: ===== U-Boot 2020.10 (Nov 28 2020 - 18:14:31 +0000) DRAM: 3.9 GiB RPI 4 Model B (0xc03111) MMC: mmcnr@7e300000: 1, emmc2@7e340000: 0 Loading Environment from FAT... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: eth0: ethernet@7d580000 PCIe BRCM: link up, 5.0 Gbps x1 (SSC) starting USB... Bus usb@7e980000: USB DWC2 Bus xhci_pci: Register 5000420 NbrPorts 5 Starting the controller USB XHCI 1.00 scanning bus usb@7e980000 for devices... 1 USB Device(s) found scanning bus xhci_pci for devices... WARN halted endpoint, queueing URB anyway. Unexpected XHCI event TRB, skipping... (3db6b570 00000000 13000000 02008401) BUG at drivers/usb/host/xhci-ring.c:498/abort_td()! BUG! resetting ... ===== Unplugging the USB keyboard fixed it. It seems to also happen for other kinds of USB devices: https://lists.denx.de/pipermail/u-boot/2020-November/433620.html

1 0