December 2020 - U-Boot

[PATCH 1/2] ls1043a: Fix address for secure boot headers
by Manish Tomar 11 Dec '20

11 Dec '20

Update kernelheader_addr and kernelheader_addr variables with correct values for ls1043a. Signed-off-by: Manish Tomar <manish.tomar(a)nxp.com> --- include/configs/ls1043a_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 01722f1344..6488c1f039 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -261,12 +261,12 @@ "kernelheader_start=0x800000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x60800000\0" \ + "kernelheader_addr=0x60600000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ -- 2.17.1

2 2

[v3] net: pfe_eth: read PFE ESBC header flash with spi_flash_read API
by Biwen Li 11 Dec '20

11 Dec '20

From: Biwen Li <biwen.li(a)nxp.com> Read PFE ESBC header flash with spi_flash_read API - logs as follows, Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB "Synchronous Abort" handler, esr 0x96000210 elr: 000000008206db44 lr : 0000000082004ea0 (reloc) elr: 00000000b7ba6b44 lr : 00000000b7b3dea0 x0 : 00000000b79407e8 x1 : 0000000040640000 x2 : 0000000000000050 x3 : 0000000000000000 x4 : 000000000000000a x5 : 0000000000000050 x6 : 0000000000000366 x7 : 00000000b7942308 x8 : 00000000b76407c0 x9 : 0000000000000008 x10: 0000000000000044 x11: 00000000b7634d1c x12: 000000000000004f x13: 0000000000000044 x14: 00000000b7634d98 x15: 00000000b76407c0 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000b7636dd8 x19: 0000000000000000 x20: 00000000b79407d0 x21: 00000000b79407e8 x22: 0000000040640000 x23: 00000000b7634e58 x24: 0000000000000000 x25: 0000000003800000 x26: 00000000b7bdd000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000b7634d10 Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826) Resetting CPU ... Signed-off-by: Biwen Li <biwen.li(a)nxp.com> --- Change in v3: - cleanup code Change in v2: - update subject and description board/freescale/ls1012afrdm/Kconfig | 11 +++++++ board/freescale/ls1012aqds/Kconfig | 14 +++++++-- board/freescale/ls1012ardb/Kconfig | 18 +++++++++-- drivers/net/pfe_eth/pfe_firmware.c | 48 ++++++++++++++++++++++++++--- 4 files changed, 81 insertions(+), 10 deletions(-) diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig index 55b414e168..4ac69d7117 100644 --- a/board/freescale/ls1012afrdm/Kconfig +++ b/board/freescale/ls1012afrdm/Kconfig @@ -16,6 +16,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40400000 @@ -65,6 +69,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40020000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" default 0x40060000 @@ -77,6 +85,9 @@ config SYS_LS_PFE_ESBC_ADDR hex "PFE Firmware HDR Addr" default 0x401f8000 +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig index 8844557aae..59b1a87665 100644 --- a/board/freescale/ls1012aqds/Kconfig +++ b/board/freescale/ls1012aqds/Kconfig @@ -20,6 +20,14 @@ if CHAIN_OF_TRUST config SYS_LS_PPA_ESBC_ADDR hex "PPA Firmware HDR Addr" default 0x40680000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if FSL_PFE @@ -39,9 +47,9 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40700000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 5a2fa91f6b..c4acea3ae2 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -20,6 +20,14 @@ if CHAIN_OF_TRUST config SYS_LS_PPA_ESBC_ADDR hex "PPA Firmware HDR Addr" default 0x40680000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40640000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 endif if FSL_PFE @@ -33,9 +41,9 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40640000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" @@ -89,6 +97,10 @@ config SYS_LS_PFE_FW_ADDR hex "Flash address of PFE firmware" default 0x40a00000 +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + config DDR_PFE_PHYS_BASEADDR hex "PFE DDR physical base address" default 0x03800000 diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index d414c750d4..41999e176d 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -10,6 +10,8 @@ * files. */ +#include <dm.h> +#include <dm/device-internal.h> #include <image.h> #include <log.h> #include <malloc.h> @@ -24,6 +26,9 @@ #define PFE_FIRMWARE_FIT_CNF_NAME "config@1" static const void *pfe_fit_addr; +#ifdef CONFIG_CHAIN_OF_TRUST +static const void *pfe_esbc_hdr_addr; +#endif /* * PFE elf firmware loader. @@ -169,7 +174,7 @@ int pfe_spi_flash_init(void) struct spi_flash *pfe_flash; struct udevice *new; int ret = 0; - void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH); if (!addr) return -ENOMEM; @@ -179,21 +184,56 @@ int pfe_spi_flash_init(void) CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE, &new); + if (ret) { + printf("SF: failed to probe spi\n"); + free(addr); + device_remove(new, DM_REMOVE_NORMAL); + return ret; + } + pfe_flash = dev_get_uclass_priv(new); if (!pfe_flash) { printf("SF: probe for pfe failed\n"); free(addr); + device_remove(new, DM_REMOVE_NORMAL); return -ENODEV; } ret = spi_flash_read(pfe_flash, CONFIG_SYS_LS_PFE_FW_ADDR, - CONFIG_SYS_QE_FMAN_FW_LENGTH, + CONFIG_SYS_LS_PFE_FW_LENGTH, addr); - if (ret) + if (ret) { printf("SF: read for pfe failed\n"); + free(addr); + spi_flash_free(pfe_flash); + return ret; + } +#ifdef CONFIG_CHAIN_OF_TRUST + void *hdr_addr = malloc(CONFIG_SYS_LS_PFE_ESBC_LENGTH); + + if (!hdr_addr) { + free(addr); + spi_flash_free(pfe_flash); + return -ENOMEM; + } + + ret = spi_flash_read(pfe_flash, + CONFIG_SYS_LS_PFE_ESBC_ADDR, + CONFIG_SYS_LS_PFE_ESBC_LENGTH, + hdr_addr); + if (ret) { + printf("SF: failed to read pfe esbc header\n"); + free(addr); + free(hdr_addr); + spi_flash_free(pfe_flash); + return ret; + } + + pfe_esbc_hdr_addr = hdr_addr; +#endif pfe_fit_addr = addr; spi_flash_free(pfe_flash); @@ -233,7 +273,7 @@ int pfe_firmware_init(void) goto err; #ifdef CONFIG_CHAIN_OF_TRUST - pfe_esbc_hdr = CONFIG_SYS_LS_PFE_ESBC_ADDR; + pfe_esbc_hdr = (uintptr_t)pfe_esbc_hdr_addr; pfe_img_addr = (uintptr_t)pfe_fit_addr; if (fsl_check_boot_mode_secure() != 0) { /* -- 2.17.1

2 1

[PATCH v4 0/3] Add support for LX2162AQDS board
by meenakshi.aggarwal＠nxp.com 11 Dec '20

11 Dec '20

From: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> This patch set add support for LX2162AQDS board. LX2162A is a variant of LX2160A. --- Changes: v2: - Add Separate ARCH for LX2162A SoC - Updated ReadMe of SoC and board v3: - Fix compilation bug for ls1088 introduced with lx2162 changes v4: - Remove non-config options from config file *** BLURB HERE *** Meenakshi Aggarwal (3): drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig armv8: lx2162a: Add Soc changes to support LX2162A armv8: lx2162aqds: Add support for LX2162AQDS platform arch/arm/Kconfig | 12 + arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 8 +- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 4 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 10 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/fsl-lx2160a-qds.dts | 3 - arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + arch/arm/dts/fsl-lx2162a-qds.dts | 34 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 +- board/freescale/common/qixis.h | 25 + board/freescale/common/vid.c | 3 +- board/freescale/common/vid.h | 31 + board/freescale/lx2160a/Kconfig | 16 + board/freescale/lx2160a/MAINTAINERS | 26 + board/freescale/lx2160a/Makefile | 1 + board/freescale/lx2160a/README | 132 +++ board/freescale/lx2160a/eth_lx2160ardb.c | 3 +- board/freescale/lx2160a/eth_lx2162aqds.c | 974 +++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 43 +- board/freescale/lx2160a/lx2160a.h | 61 ++ configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 98 +++ configs/lx2162aqds_tfa_defconfig | 96 ++ configs/lx2162aqds_tfa_verified_boot_defconfig | 103 +++ drivers/ddr/fsl/Kconfig | 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/net/phy/Kconfig | 9 + drivers/net/phy/cortina.c | 8 +- drivers/pci/Kconfig | 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 +- include/configs/lx2160a_common.h | 2 + include/configs/lx2160aqds.h | 76 -- include/configs/lx2160ardb.h | 50 -- include/configs/lx2162aqds.h | 78 ++ 56 files changed, 2127 insertions(+), 198 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c create mode 100644 board/freescale/lx2160a/lx2160a.h create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/lx2162aqds_tfa_defconfig create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig create mode 100644 include/configs/lx2162aqds.h -- 2.7.4

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[PATCH v2 00/12] Add label to pcie nodes
by Wasim Khan 11 Dec '20

11 Dec '20

This patch series - Adds label to pcie nodes in dts file for NXP's layerscape SoCs - Print the pcie controller number starting from 1 to match RMs - Add checks for config resource size and fix indendation. Changes in V2: - Enable CONFIG_PCIE_LAYERSCAPE_GEN4 to make LX2160A-Rev1 work - Fix CheckPatch issues - Change 1KB size check to 4KB size check for ls_pcie_g4. - Commit description updates Changes in V3: - fix compilation issue on ls102xa platforms Wasim Khan (12): configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 pci: layerscape: Print pcie controller number starting from 1 pci: ls_pcie_g4: Print pcie controller number starting from 1 arm: dts: lx2160a: add label to pcie nodes in dts arm: dts: ls1046a: add label to pcie nodes in dts arm: dts: ls2080a: add label to pcie nodes in dts arm: dts: ls1088a: add label to pcie nodes in dts arm: dts: ls1012a: add label to pcie nodes in dts arm: dts: ls1043a: add label to pcie nodes in dts arm: dts: ls1028a: add label to pcie nodes in dts pci: layerscape: Add size check for config resource pci: ls_pcie_g4: Add size check for config resource arch/arm/dts/fsl-ls1012a.dtsi | 3 ++- arch/arm/dts/fsl-ls1028a.dtsi | 6 +++--- arch/arm/dts/fsl-ls1043a.dtsi | 9 +++++---- arch/arm/dts/fsl-ls1046a.dtsi | 12 ++++++------ arch/arm/dts/fsl-ls1088a.dtsi | 8 ++++---- arch/arm/dts/fsl-ls2080a.dtsi | 11 ++++++----- arch/arm/dts/fsl-lx2160a.dtsi | 12 ++++++------ configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + drivers/pci/pcie_layerscape_ep.c | 4 +++- drivers/pci/pcie_layerscape_gen4.c | 19 +++++++++++++++---- drivers/pci/pcie_layerscape_rc.c | 14 +++++++++++--- 15 files changed, 66 insertions(+), 37 deletions(-) -- 2.7.4

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[PATCH] armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A
by Alban Bedel 11 Dec '20

11 Dec '20

When booting from TF-A there is a logic that attempt to detect if the default environment is used, if this is the case it then set the `bootcmd` and `mcinitcmd` depending of the device we booted from. This detection logic is dubious as it access internals of the env implementation and it doesn't always work correctly. First of all it detect any valid environment as not being the default, so after running `env default -a && saveenv` the board doesn't boot anymore as `bootcmd` is then empty. But it also fails in some other ways, for example it always detect a default environment when redundant env is enabled on MMC, so in that case `bootcmd` is overwritten on every boot. Instead of increasing the complexity of the detection just check if `bootcmd` and `mcinitcmd` are set in the environment and set them if they are not. Signed-off-by: Alban Bedel <alban.bedel(a)aerq.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27 ++++--------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 96b2775f3f..af9399278f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -33,13 +33,10 @@ #include <fsl_validate.h> #endif #include <fsl_immap.h> -#ifdef CONFIG_TFABOOT -#include <env_internal.h> -#endif #include <dm.h> #include <dm/device_compat.h> #include <linux/err.h> -#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS) +#ifdef CONFIG_GIC_V3_ITS DECLARE_GLOBAL_DATA_PTR; #endif @@ -954,28 +951,12 @@ int board_late_init(void) #endif #ifdef CONFIG_TFABOOT /* - * check if gd->env_addr is default_environment; then setenv bootcmd - * and mcinitcmd. - */ -#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR - if (gd->env_addr == (ulong)&default_environment[0]) { -#else - if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { -#endif - fsl_setenv_bootcmd(); - fsl_setenv_mcinitcmd(); - } - - /* - * If the boot mode is secure, default environment is not present then - * setenv command needs to be run by default + * Set bootcmd and mcinitcmd if they don't exist in the environment. */ -#ifdef CONFIG_CHAIN_OF_TRUST - if ((fsl_check_boot_mode_secure() == 1)) { + if (!env_get("bootcmd")) fsl_setenv_bootcmd(); + if (!env_get("mcinitcmd")) fsl_setenv_mcinitcmd(); - } -#endif #endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); -- 2.25.1

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[PATCH] powerpc: mpc85xx: Allow boards to override CONFIG_USB_MAX_CONTROLLER_COUNT
by Chris Packham 11 Dec '20

11 Dec '20

If the board isn't strapped to enable USB1 then attempting to access it will result in a hang. Avoid this by allowing boards to define CONFIG_USB_MAX_CONTROLLER_COUNT. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4ca1e2b325f1..f25ba1af0928 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -116,7 +116,9 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -- 2.29.2

2 1

[PATCH] drivers: ifc: add define for IFC_CSPRn TE bit
by Aleksandar Gerasimovski 11 Dec '20

11 Dec '20

To drive TE pin high is supported IFC configuration that can be used on some designs. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachi-powergrids.com> --- include/fsl_ifc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index fd91533..e1e6214 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -52,6 +52,8 @@ /* Machine Select */ #define CSPR_MSEL 0x00000006 #define CSPR_MSEL_SHIFT 1 +/* External Transceiver Enable */ +#define CSPR_TE 0x00000010 /* NOR */ #define CSPR_MSEL_NOR 0x00000000 /* NAND */ -- 1.8.3.1

2 1

[PATCH] arm: ls102xa: select USB PHY erratum's only if USB support is enabled
by Aleksandar Gerasimovski 11 Dec '20

11 Dec '20

The USB support is not by default enabled on all designs, so it does not make seance to have USB specific erratum's enabled on such a designs. On our internal Hitachi-Powergrids design not using the USB controller there is a crash when accessing those specific memory locations selected by the erratum flags. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachi-powergrids.com> --- arch/arm/cpu/armv7/ls102xa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 937989b..747059b 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,11 +5,11 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 select SYS_FSL_ERRATUM_A008850 - select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 - select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A008997 if USB + select SYS_FSL_ERRATUM_A009007 if USB + select SYS_FSL_ERRATUM_A009008 if USB select SYS_FSL_ERRATUM_A009663 - select SYS_FSL_ERRATUM_A009798 + select SYS_FSL_ERRATUM_A009798 if USB select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_HAS_CCI400 -- 1.8.3.1

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[RESEND PATCH] configs: lx2162aqds: Enable gpio driver in defconfig
by Ran Wang 11 Dec '20

11 Dec '20

From: "hui.song" <hui.song_1(a)nxp.com> make lx2162aqds platform to enable gpio driver. Signed-off-by: Hui Song <hui.song_1(a)nxp.com> Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- depends on: http://patchwork.ozlabs.org/project/uboot/patch/1599473527-21511-3-git-send… configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 065f6a1..649c93c 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -95,3 +95,4 @@ CONFIG_CMD_DATE=y CONFIG_RTC_PCF2127=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_MPC8XXX_GPIO=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 33ca543..8201d95 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -93,3 +93,4 @@ CONFIG_CMD_DATE=y CONFIG_RTC_PCF2127=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_MPC8XXX_GPIO=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 7d0dbcd..4d0538f 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -100,3 +100,4 @@ CONFIG_OPTEE=y CONFIG_CMD_OPTEE_RPMB=y CONFIG_OPTEE_TA_AVB=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MPC8XXX_GPIO=y -- 2.7.4

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[PATCH] tools: socfpgaimage: Print image header information
by Ley Foon Tan 11 Dec '20

11 Dec '20

Print image header information if the header is verified. Example output from mkimage "-l" option: $ ./tools/mkimage -l spl/u-boot-spl.sfp Image Type : Cyclone V / Arria V SoC Image Validation word : 0x31305341 Version : 0x00000000 Flags : 0x00000000 Program length : 0x00003a59 Header checksum : 0x00000188 $ ./tools/mkimage -l spl/u-boot-spl.sfp Image Type : Arria 10 SoC Image Validation word : 0x31305341 Version : 0x00000001 Flags : 0x00000000 Header length : 0x00000014 Program length : 0x000138e0 Program entry : 0x00000014 Header checksum : 0x00000237 Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- tools/socfpgaimage.c | 45 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c index 3ba3c93af1bd..5808b383e9cb 100644 --- a/tools/socfpgaimage.c +++ b/tools/socfpgaimage.c @@ -274,12 +274,51 @@ static int socfpgaimage_verify_header(unsigned char *ptr, int image_size, return sfp_verify_buffer(ptr); } +static void socfpgaimage_print_header_v0(struct socfpga_header_v0 *header) +{ + printf("Image Type\t: Cyclone V / Arria V SoC Image\n"); + printf("Validation word\t: 0x%08x\n", + le32_to_cpu(header->validation)); + printf("Version\t\t: 0x%08x\n", header->version); + printf("Flags\t\t: 0x%08x\n", header->flags); + printf("Program length\t: 0x%08x\n", + le16_to_cpu(header->length_u32)); + printf("Header checksum\t: 0x%08x\n", + le16_to_cpu(header->checksum)); +} + +static void socfpgaimage_print_header_v1(struct socfpga_header_v1 *header) +{ + printf("Image Type\t: Arria 10 SoC Image\n"); + printf("Validation word\t: 0x%08x\n", + le32_to_cpu(header->validation)); + printf("Version\t\t: 0x%08x\n", header->version); + printf("Flags\t\t: 0x%08x\n", header->flags); + printf("Header length\t: 0x%08x\n", + le16_to_cpu(header->header_u8)); + printf("Program length\t: 0x%08x\n", + le32_to_cpu(header->length_u8)); + printf("Program entry\t: 0x%08x\n", + le32_to_cpu(header->entry_offset)); + printf("Header checksum\t: 0x%08x\n", + le16_to_cpu(header->checksum)); +} + static void socfpgaimage_print_header(const void *ptr) { - if (sfp_verify_buffer(ptr) == 0) - printf("Looks like a sane SOCFPGA preloader\n"); - else + const void *header = ptr + HEADER_OFFSET; + struct socfpga_header_v0 *header_v0; + + if (sfp_verify_buffer(ptr) == 0) { + header_v0 = (struct socfpga_header_v0 *)header; + + if (header_v0->version == 0) + socfpgaimage_print_header_v0(header_v0); + else + socfpgaimage_print_header_v1((struct socfpga_header_v1 *)header); + } else { printf("Not a sane SOCFPGA preloader\n"); + } } static int socfpgaimage_check_params_v0(struct image_tool_params *params) -- 2.19.0

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