November 2020 - U-Boot

[PATCH v2] env: mmc: Correct partition comparison in mmc_offset_try_partition
by Hoyeonjiki Kim 15 Nov '20

15 Nov '20

The function mmc_offset_try_partition searches MMC partition to save the environment data by name. However, it only compares the first word-size bytes (size of 'const char *'), which may make the function to find unintended partition. Correct the function not to partially compare the partition name with config "u-boot,mmc-env-partition". Fixes: c9e87ba66540 ("env: Save environment at the end of an MMC partition") Signed-off-by: Hoyeonjiki Kim <jigi.kim(a)gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- env/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/env/mmc.c b/env/mmc.c index 4e67180b23..505f7aa2b8 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -42,7 +42,7 @@ static inline int mmc_offset_try_partition(const char *str, int copy, s64 *val) if (ret < 0) return ret; - if (!strncmp((const char *)info.name, str, sizeof(str))) + if (!strcmp((const char *)info.name, str)) break; } -- 2.25.1

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[PATCH v3 0/4] Add Renesas SoC identification driver support
by Biju Das 15 Nov '20

15 Nov '20

This patch series aims to support Renesas SoC identification driver. Added a helper function of_match_node to find the matching of_match structure. This helper function can be used to replace the following code in u-boot [1] and [2] [1] https://elixir.bootlin.com/u-boot/latest/source/drivers/serial/serial_uniph… [2] https://elixir.bootlin.com/u-boot/latest/source/drivers/usb/phy/rockchip_us… Also added soc_id attribute support in UCLASS_SOC which is required for Renesas SoC identification driver similar to mainline linux. Biju Das (4): dm: core: Add of_match_node helper function soc: Fix comments from SOC to SoC dm: soc: Add SoC id for attribute matching dm: soc: SoC identification driver for Renesas SoC's drivers/core/device.c | 21 ++++ drivers/soc/Kconfig | 7 ++ drivers/soc/Makefile | 1 + drivers/soc/soc-uclass.c | 19 ++- drivers/soc/soc_renesas.c | 239 ++++++++++++++++++++++++++++++++++++++ drivers/soc/soc_sandbox.c | 8 ++ include/dm/device.h | 13 +++ include/soc.h | 39 ++++++- test/dm/core.c | 31 +++++ test/dm/soc.c | 8 ++ 10 files changed, 379 insertions(+), 7 deletions(-) create mode 100644 drivers/soc/soc_renesas.c -- 2.17.1

2 10

[PATCH 0/7] patman: Minor improvements to 'patman status'
by Simon Glass 15 Nov '20

15 Nov '20

This series builds on the previous one which added a new 'status' subcommand to patman. With this, the patchwork URL can be specified in the settings file, a commit tag or the command line. Some other minor improvements are included also. Both series are available at u-boot-dm/patman-working Simon Glass (7): patman: Refactor how the default subcommand works patman: Correct Change-Ids error message args patman: Fix-up for plural warning patman: Update defaults in subparsers patman: Allow specifying the patchwork URL patman: Add a setting for the Patchwork URL patman: Add a Series-patchwork-url option tools/patman/README | 7 ++++ tools/patman/control.py | 10 ++++-- tools/patman/func_test.py | 40 +++++++++++++++-------- tools/patman/gitutil.py | 10 +++--- tools/patman/main.py | 64 +++++++++++++++++++++---------------- tools/patman/patchstream.py | 6 ++-- tools/patman/series.py | 2 +- tools/patman/settings.py | 28 ++++++++++++---- tools/patman/status.py | 29 ++++++++++------- 9 files changed, 126 insertions(+), 70 deletions(-) -- 2.29.1.341.ge80a0c044ae-goog

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[PATCH 1/2] cros_ec: Correct collection of EC hash
by Simon Glass 15 Nov '20

15 Nov '20

The EC now requires that the offset field be set correctly when checking on hash status. Update the code to handle this. Use the same message struct in both functions to reduce stack space. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- drivers/misc/cros_ec.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index c3674908ee8..1b22f1883ee 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -495,18 +495,18 @@ int cros_ec_read_current_image(struct udevice *dev, } static int cros_ec_wait_on_hash_done(struct udevice *dev, + struct ec_params_vboot_hash *p, struct ec_response_vboot_hash *hash) { - struct ec_params_vboot_hash p; ulong start; start = get_timer(0); while (hash->status == EC_VBOOT_HASH_STATUS_BUSY) { mdelay(50); /* Insert some reasonable delay */ - p.cmd = EC_VBOOT_HASH_GET; - if (ec_command(dev, EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), - hash, sizeof(*hash)) < 0) + p->cmd = EC_VBOOT_HASH_GET; + if (ec_command(dev, EC_CMD_VBOOT_HASH, 0, p, sizeof(*p), hash, + sizeof(*hash)) < 0) return -1; if (get_timer(start) > CROS_EC_CMD_HASH_TIMEOUT_MS) { @@ -530,7 +530,7 @@ int cros_ec_read_hash(struct udevice *dev, uint hash_offset, return -1; /* If the EC is busy calculating the hash, fidget until it's done. */ - rv = cros_ec_wait_on_hash_done(dev, hash); + rv = cros_ec_wait_on_hash_done(dev, &p, hash); if (rv) return rv; @@ -553,9 +553,13 @@ int cros_ec_read_hash(struct udevice *dev, uint hash_offset, hash, sizeof(*hash)) < 0) return -1; - rv = cros_ec_wait_on_hash_done(dev, hash); + rv = cros_ec_wait_on_hash_done(dev, &p, hash); if (rv) return rv; + if (hash->status != EC_VBOOT_HASH_STATUS_DONE) { + log_err("Hash did not complete, status=%d\n", hash->status); + return -EIO; + } debug("%s: hash done\n", __func__); -- 2.29.2.222.g5d2a92d10f8-goog

1 3

[PATCH 1/1] cros_ec: Handling EC_CMD_GET_NEXT_EVENT
by Heinrich Schuchardt 15 Nov '20

15 Nov '20

With commit 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does not understand this command. We need to reply with -EC_RES_INVALID_COMMAND to force check_for_keys() to fall back to use EC_CMD_MKBP_STATE. Currently the driver prints ** Unknown EC command 0x67 in this case. With the patch the message is suppressed. In a future patch we should upgrade the sandbox driver to provide EC_CMD_GET_NEXT_EVENT support. Fixes: 690079767803 ("cros_ec: Support keyboard scanning with EC_CMD_GET_NEXT_EVENT") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- process_cmd() should always return an appropriate negative enum ec_status in case of an error and not simply -1. But fixing the return values is beyond the scope of this patch. --- drivers/misc/cros_ec_sandbox.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index a191f061b8..ff7f782742 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -460,6 +460,16 @@ static int process_cmd(struct ec_state *ec, case EC_CMD_ENTERING_MODE: len = 0; break; + case EC_CMD_GET_NEXT_EVENT: + /* + * TODO: + * This driver emulates an old keyboard device supporting + * EC_CMD_MKBP_STATE. Current Chrome OS keyboards use + * EC_CMD_GET_NEXT_EVENT. Cf. + * "mkbp: Add support for buttons and switches" + * https://chromium.googlesource.com/chromiumos/platform/ec/+/87a071941b89e3f7… + */ + return -EC_RES_INVALID_COMMAND; default: printf(" ** Unknown EC command %#02x\n", req_hdr->command); return -1; -- 2.28.0

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[PATCH 1/2] power: twl4030: Add twl4030_i2c_read() function
by Pali Rohár 15 Nov '20

15 Nov '20

Function twl4030_i2c_read() is like twl4030_i2c_read_u8() but instead of single value it rather returns array of values. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/power/twl4030.c | 7 +++---- include/twl4030.h | 12 +++++++++--- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index b0d5cba2c4..f48af84e17 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -201,7 +201,7 @@ int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) return 0; } -int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) +int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *valp, int len) { struct udevice *dev; int ret; @@ -211,12 +211,11 @@ int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *valp) pr_err("unable to get I2C bus. ret %d\n", ret); return ret; } - ret = dm_i2c_reg_read(dev, reg); - if (ret < 0) { + ret = dm_i2c_read(dev, reg, valp, len); + if (ret) { pr_err("reading from twl4030 failed. ret %d\n", ret); return ret; } - *valp = (u8)ret; return 0; } #endif diff --git a/include/twl4030.h b/include/twl4030.h index c27ad615ee..ef05193996 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -654,14 +654,20 @@ static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) return i2c_write(chip_no, reg, 1, &val, 1); } -static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +static inline int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len) { - return i2c_read(chip_no, reg, 1, val, 1); + return i2c_read(chip_no, reg, 1, val, len); } #else int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val); -int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val); +int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len); #endif + +static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) +{ + return twl4030_i2c_read(chip_no, reg, val, 1); +} + /* * Power */ -- 2.20.1

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[u-boot PATCH] configs: am65/j72x: Set CONFIG_LOGLEVEL to 7
by Roger Quadros 15 Nov '20

15 Nov '20

By default CONFIG_LOGLEVEL seems to be set to 4 which is too low and doesn't show dev_info/dev_notice/dev_warn messages on console. This has been deliberately set low globally to be conservative setting across the board due to primary bootloader size limitations. It is best to tune per board config as per user needs. On K3 we have separate SPL and u-boot configs so we can afford to set u-boot CONFIG_LOGLEVEL to 7. On AM65 this patch causes u-boot.img size to change from 932KB to 940KB with 1 line additional print during MMC boot. i.e. details of Net subsystem "Net: K3 CPSW: nuss_ver: 0x6BA00102 cpsw_ver: 0x6BA80102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000" Similar 8KB difference was seen on J721E. Signed-off-by: Roger Quadros <rogerq(a)ti.com> Reviewed-by: Nishanth Menon <nm(a)ti.com> --- configs/am65x_evm_a53_defconfig | 1 + configs/am65x_hs_evm_a53_defconfig | 1 + configs/j7200_evm_a72_defconfig | 1 + configs/j721e_evm_a72_defconfig | 1 + configs/j721e_hs_evm_a72_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 8a94ad1530..941073ce7f 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 2c7217afb6..7d467c167e 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit" +CONFIG_LOGLEVEL=7 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 7c900b1d2e..1d2526b5f1 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 6de8666956..982e3df2f2 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index acbc04359c..28bf56e7e1 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit" +CONFIG_LOGLEVEL=7 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[PATCH v2] ARM: am335x: Add phyBOARD REGOR support
by Parthiban Nallathambi 15 Nov '20

15 Nov '20

phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060). CPU : AM335X-GP rev 2.1 Model: Phytec AM335x phyBOARD-REGOR DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 eth0: ethernet@4a100000 Working: - Eth0 - i2C - MMC/SD - NAND - UART - USB (host) Device trees were taken from Linux mainline: commit c4d6fe731176 ("Linux 5.9.0") Signed-off-by: Parthiban Nallathambi <parthiban(a)linumiz.com> --- Notes: Changelog in v2: - include regor files in MAINTAINERS arch/arm/dts/Makefile | 3 +- arch/arm/dts/am335x-regor-rdk-u-boot.dtsi | 31 ++++ arch/arm/dts/am335x-regor-rdk.dts | 24 +++ arch/arm/dts/am335x-regor.dtsi | 202 +++++++++++++++++++++ board/phytec/phycore_am335x_r2/MAINTAINERS | 6 +- configs/phycore-am335x-r2-regor_defconfig | 88 +++++++++ 6 files changed, 352 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/am335x-regor-rdk-u-boot.dtsi create mode 100644 arch/arm/dts/am335x-regor-rdk.dts create mode 100644 arch/arm/dts/am335x-regor.dtsi create mode 100644 configs/phycore-am335x-r2-regor_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b195723f16..4f67108e7f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -347,7 +347,8 @@ dtb-$(CONFIG_AM33XX) += \ am335x-sl50.dtb \ am335x-base0033.dtb \ am335x-guardian.dtb \ - am335x-wega-rdk.dtb + am335x-wega-rdk.dtb \ + am335x-regor-rdk.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi new file mode 100644 index 0000000000..1ddd715875 --- /dev/null +++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linumiz + */ + +/ { + chosen { + #address-cells = <1>; + #size-cells = <1>; + + bootargs = "console=ttyO0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + ocp { + u-boot,dm-pre-reloc; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&mmc1 { + u-boot,dm-pre-reloc; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/am335x-regor-rdk.dts b/arch/arm/dts/am335x-regor-rdk.dts new file mode 100644 index 0000000000..66a1360b83 --- /dev/null +++ b/arch/arm/dts/am335x-regor-rdk.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet(a)phytec.de> + * + */ + +/dts-v1/; + +#include "am335x-phycore-som.dtsi" +#include "am335x-regor.dtsi" + +/* SoM */ +&gpmc { + status = "okay"; +}; + +&i2c_eeprom { + status = "okay"; +}; + +&serial_flash { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi new file mode 100644 index 0000000000..86b3f07429 --- /dev/null +++ b/arch/arm/dts/am335x-regor.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Phytec Messtechnik GmbH + * Author: Teresa Remmet <t.remmet(a)phytec.de> + * + */ + +/ { + model = "Phytec AM335x phyBOARD-REGOR"; + compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; + + vcc3v3: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* User IO */ + user_leds: user_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_pins>; + + run_stop-led { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + error-led { + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + }; +}; + +/* User Leds */ +&am33xx_pinmux { + user_leds_pins: pinmux_user_leds { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2_22 */ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ + >; + }; +}; + +/* CAN Busses */ +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +/* Ethernet */ +&am33xx_pinmux { + ethernet1_pins: pinmux_ethernet1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */ + AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */ + AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */ + AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */ + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */ + AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */ + AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */ + AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */ + >; + }; +}; + +&cpsw_emac1 { + phy-handle = <&phy1>; + phy-mode = "mii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&mac { + slaves = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&ethernet0_pins &ethernet1_pins>; + dual_emac = <1>; +}; + +/* GPIOs */ +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&user_gpios_pins>; + + user_gpios_pins: pinmux_user_gpios { + pinctrl-single,pins = < + /* DIGIN 1-4 */ + AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7) /* gpmc_ad11.gpio0_27 */ + AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ + AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7) /* gpmc_ad9.gpio0_23 */ + AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7) /* gpmc_ad8.gpio0_22 */ + /* DIGOUT 1-4 */ + AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad15.gpio1_15 */ + AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad14.gpio1_14 */ + AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad13.gpio1_13 */ + AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad12.gpio1_12 */ + >; + }; +}; + +/* MMC */ +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */ + >; + }; +}; + +&mmc1 { + vmmc-supply = <&vcc3v3>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* RTC */ +&i2c_rtc { + status = "okay"; +}; + +/* UARTs */ +&am33xx_pinmux { + uart0_pins: pinmux_uart0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + uart2_pins: pinmux_uart2 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ + AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rx_clk.uart2_txd */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +/* RS485 - UART1 */ +&am33xx_pinmux { + uart1_rs485_pins: pinmux_uart1_rs485_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_rs485_pins>; + status = "okay"; + linux,rs485-enabled-at-boot-time; +}; diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS index e56f30fdc0..8d02b0e198 100644 --- a/board/phytec/phycore_am335x_r2/MAINTAINERS +++ b/board/phytec/phycore_am335x_r2/MAINTAINERS @@ -1,7 +1,11 @@ phyCORE AM335x R2 WEGA BOARD M: Niel Fourie <lusus(a)denx.de> -M: Parthiban Nallathambi <pn(a)denx.de> +M: Parthiban Nallathambi <parthiban(a)linumiz.com> S: Maintained +F: arch/arm/dts/am335x-regor.dtsi +F: arch/arm/dts/am335x-regor-rdk.dts +F: arch/arm/dts/am335x-regor-rdk-u-boot.dtsi F: board/phytec/phycore_am335x_r2 F: include/configs/phycore_am335x_r2.h +F: configs/phycore-am335x-r2-regor_defconfig F: configs/phycore-am335x-r2-wega_defconfig diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig new file mode 100644 index 0000000000..6d40497537 --- /dev/null +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_OFFSET=0xA0000 +CONFIG_AM33XX=y +CONFIG_SYS_MPUCLK=1000 +CONFIG_TARGET_PHYCORE_AM335X_R2=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk" +# CONFIG_FIT is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="am335x-regor-rdk.dtb" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_DRIVERS=y +CONFIG_SPL_NAND_ECC=y +CONFIG_SPL_NAND_BASE=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_SPL=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_DNS2=y +CONFIG_CMD_PING=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),1m(NAND.u-boot),-(NAND.UBI)" +CONFIG_CMD_UBI=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_OMAP3_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_TI=y +CONFIG_USB_GADGET=y +CONFIG_USB_ETHER=y +CONFIG_FDT_FIXUP_PARTITIONS=y +# CONFIG_EFI_LOADER is not set -- 2.28.0

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[PATCH] MIPS: introduce `REL_LA' to get label runtime address
by Du Huanpeng 14 Nov '20

14 Nov '20

replace PTR_LA in the very begining, e.g. in arch/mips/cpu/start.S arch/mips/lib/cache_init.S to write position independence code. this is helpfull for make single binary can be loaded to different ram/rom addresses. FIXME: only tested on 32 bit system Signed-off-by: Du Huanpeng <dhu(a)hodcarrier.cn> --- arch/mips/include/asm/asm.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index a6876e1..f93281f 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -289,6 +289,27 @@ symbol = value #define PTRLOG 3 #endif +#ifdef __ASSEMBLER__ +/* + * helpers for writing position independence code + * FIXME: only tested on 32 bit system + */ + .macro REL_LA reg lable + .set push + .set noat + .set noreorder + move $at, $ra /* preserve ra */ + bal 888f + nop +888: la \reg, 888b + subu \reg, $ra, \reg /* offset store in reg */ + move $ra, $at /* restroe ra */ + la $at, \lable + addu \reg, $at, \reg + .set pop + .endm +#endif + /* * Some cp0 registers were extended to 64bit for MIPS III. */ -- 2.7.4

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Re: [PATCH v2 1/2] i2c: ocores: add i2c driver for OpenCores I2C controller
by Rick Chen 14 Nov '20

14 Nov '20

> From: Pragnesh Patel [mailto:pragnesh.patel@sifive.com] > Sent: Thursday, October 22, 2020 2:55 PM > To: u-boot(a)lists.denx.de > Cc: atish.patra(a)wdc.com; palmerdabbelt(a)google.com; bmeng.cn(a)gmail.com; paul.walmsley(a)sifive.com; anup.patel(a)wdc.com; sagar.kadam(a)sifive.com; Rick Jian-Zhi Chen(陳建志); peter(a)korsgaard.com; Pragnesh Patel; Heiko Schocher > Subject: [PATCH v2 1/2] i2c: ocores: add i2c driver for OpenCores I2C controller > > Add support for the OpenCores I2C controller IP core > (See http://www.opencores.org/projects.cgi/web/i2c/overview). > > This driver implementation is inspired from the Linux OpenCores > I2C driver available. > > Thanks to Peter Korsgaard <peter(a)korsgaard.com> for writing Linux > OpenCores I2C driver. > > Signed-off-by: Pragnesh Patel <pragnesh.patel(a)sifive.com> > --- > > Changes in v2: > - Remove TYPE_SIFIVE_REV0 flag > - Update the Opencores I2C Controller Link > > drivers/i2c/Kconfig | 7 + > drivers/i2c/Makefile | 1 + > drivers/i2c/ocores_i2c.c | 636 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 644 insertions(+) > create mode 100644 drivers/i2c/ocores_i2c.c > Reviewed-by: Rick Chen <rick(a)andestech.com>

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