January 2020 - U-Boot

[PATCH v3] board/lx2160aqds: Update the DSPI status fixup
by Xiaowei Bao 03 Jan '20

03 Jan '20

The dts node of the DSPI controller in kernel is spi instead of dspi, it is not correct if use "/soc/dspi@" to fix up the status of the dts in kernel, so, modify it to "/soc/spi@". The DSPI2 and I2C5 are muxed, and the status of DSPI2 node in kernel dts default value is okay, set the status of DSPI2 node is disabled if it used to I2C5. Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Modify the subject and commit message. v3: - Modify the Copyright. board/freescale/lx2160a/lx2160a.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index eff5d9f..184e111 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP */ #include <common.h> @@ -210,9 +210,9 @@ void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; const char esdhc1_path[] = "/soc/esdhc@2150000"; - const char dspi0_path[] = "/soc/dspi@2100000"; - const char dspi1_path[] = "/soc/dspi@2110000"; - const char dspi2_path[] = "/soc/dspi@2120000"; + const char dspi0_path[] = "/soc/spi@2100000"; + const char dspi1_path[] = "/soc/spi@2110000"; + const char dspi2_path[] = "/soc/spi@2120000"; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 sdhc1_base_pmux; @@ -262,10 +262,12 @@ void esdhc_dspi_status_fixup(void *blob) & FSL_CHASSIS3_IIC5_PMUX_MASK; iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; - if (iic5_pmux == IIC5_PMUX_SPI3) { + if (iic5_pmux == IIC5_PMUX_SPI3) do_fixup_by_path(blob, dspi2_path, "status", "okay", sizeof("okay"), 1); - } + else + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); } #endif -- 2.9.5

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[PATCH v2] board/lx2160aqds: Update the DSPI status fixup
by Xiaowei Bao 03 Jan '20

03 Jan '20

The dts node of the DSPI controller in kernel is spi instead of dspi, it is not correct if use "/soc/dspi@" to fix up the status of the dts in kernel, so, modify it to "/soc/spi@". The DSPI2 and I2C5 are muxed, and the status of DSPI2 node in kernel dts default value is okay, set the status of DSPI2 node is disabled if it used to I2C5. Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Modify the subject and commit message. board/freescale/lx2160a/lx2160a.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index eff5d9f..3d7cd8b 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -210,9 +210,9 @@ void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; const char esdhc1_path[] = "/soc/esdhc@2150000"; - const char dspi0_path[] = "/soc/dspi@2100000"; - const char dspi1_path[] = "/soc/dspi@2110000"; - const char dspi2_path[] = "/soc/dspi@2120000"; + const char dspi0_path[] = "/soc/spi@2100000"; + const char dspi1_path[] = "/soc/spi@2110000"; + const char dspi2_path[] = "/soc/spi@2120000"; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 sdhc1_base_pmux; @@ -262,10 +262,12 @@ void esdhc_dspi_status_fixup(void *blob) & FSL_CHASSIS3_IIC5_PMUX_MASK; iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; - if (iic5_pmux == IIC5_PMUX_SPI3) { + if (iic5_pmux == IIC5_PMUX_SPI3) do_fixup_by_path(blob, dspi2_path, "status", "okay", sizeof("okay"), 1); - } + else + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); } #endif -- 2.9.5

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[PATCH v2] board/lx2160aqds: Update the DSPI status fixup
by Xiaowei Bao 03 Jan '20

03 Jan '20

The dts node of the DSPI controller in kernel is spi instead of dspi, it is not correct if ues "/soc/dspi@" to fix up the status of the dts in kernel, so, modify it to "/soc/spi@". The DSPI2 and I2C5 are muxed, and the status of DSPI2 node in kernel dts default value is okay, set the status of DSPI2 node is disabled if it used to I2C5. Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Modify the subject and commit message. board/freescale/lx2160a/lx2160a.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index eff5d9f..3d7cd8b 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -210,9 +210,9 @@ void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; const char esdhc1_path[] = "/soc/esdhc@2150000"; - const char dspi0_path[] = "/soc/dspi@2100000"; - const char dspi1_path[] = "/soc/dspi@2110000"; - const char dspi2_path[] = "/soc/dspi@2120000"; + const char dspi0_path[] = "/soc/spi@2100000"; + const char dspi1_path[] = "/soc/spi@2110000"; + const char dspi2_path[] = "/soc/spi@2120000"; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 sdhc1_base_pmux; @@ -262,10 +262,12 @@ void esdhc_dspi_status_fixup(void *blob) & FSL_CHASSIS3_IIC5_PMUX_MASK; iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; - if (iic5_pmux == IIC5_PMUX_SPI3) { + if (iic5_pmux == IIC5_PMUX_SPI3) do_fixup_by_path(blob, dspi2_path, "status", "okay", sizeof("okay"), 1); - } + else + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); } #endif -- 2.9.5

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[PATCH] lx2160aqds: Fix the the issue that dspi not work in kernel
by Xiaowei Bao 03 Jan '20

03 Jan '20

The DSPI node of DTS in kernel is spi, so fix the "/soc/dspi@" ot "/soc/spi@". The DSPI2 and I2C5 is muxed, and the DSPI2 default status is okay, so must set the DSPI2 status is disabled if the pin use to I2C5. Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- board/freescale/lx2160a/lx2160a.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index eff5d9f..3d7cd8b 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -210,9 +210,9 @@ void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; const char esdhc1_path[] = "/soc/esdhc@2150000"; - const char dspi0_path[] = "/soc/dspi@2100000"; - const char dspi1_path[] = "/soc/dspi@2110000"; - const char dspi2_path[] = "/soc/dspi@2120000"; + const char dspi0_path[] = "/soc/spi@2100000"; + const char dspi1_path[] = "/soc/spi@2110000"; + const char dspi2_path[] = "/soc/spi@2120000"; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 sdhc1_base_pmux; @@ -262,10 +262,12 @@ void esdhc_dspi_status_fixup(void *blob) & FSL_CHASSIS3_IIC5_PMUX_MASK; iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; - if (iic5_pmux == IIC5_PMUX_SPI3) { + if (iic5_pmux == IIC5_PMUX_SPI3) do_fixup_by_path(blob, dspi2_path, "status", "okay", sizeof("okay"), 1); - } + else + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); } #endif -- 2.9.5

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[PATCH] .gitignore: ignore files generated by asn1 compiler
by Dario Binacchi 03 Jan '20

03 Jan '20

As described in doc/README.asn1 document the tools/asn1_compiler is used to "generate bytecode as a C file (*.asn1.[ch]) from *.asn1 file". Signed-off-by: Dario Binacchi <dariobin(a)libero.it> --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index f980ae6f70..2e1c8bf2bf 100644 --- a/.gitignore +++ b/.gitignore @@ -7,6 +7,7 @@ # .* *.a +*.asn1.[ch] *.bin *.cfgout *.dtb -- 2.24.0

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[PATCH] tools: .gitignore: add asn1_compiler
by Dario Binacchi 03 Jan '20

03 Jan '20

Add the tool to the ignore list to prevent being marked as unversioned. Signed-off-by: Dario Binacchi <dariobin(a)libero.it> --- tools/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/.gitignore b/tools/.gitignore index d0176a7283..82bdce2782 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -1,3 +1,4 @@ +/asn1_compiler /atmel_pmecc_params /bin2header /bmp_logo -- 2.24.0

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[PATCH] test: Fix the boardspec for the SPL handoff test
by Simon Glass 03 Jan '20

03 Jan '20

This test currently does not run because it specifies the sandbox board instead of sandbox_spl. Fix it. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- test/py/tests/test_handoff.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_handoff.py b/test/py/tests/test_handoff.py index 0ee972298c..038f03064a 100644 --- a/test/py/tests/test_handoff.py +++ b/test/py/tests/test_handoff.py @@ -6,7 +6,7 @@ import pytest # Magic number to check that SPL handoff is working TEST_HANDOFF_MAGIC = 0x14f93c7b -(a)pytest.mark.boardspec('sandbox') +(a)pytest.mark.boardspec('sandbox_spl') @pytest.mark.buildconfigspec('spl') def test_handoff(u_boot_console): """Test that of-platdata can be generated and used in sandbox""" -- 2.24.1.735.g03f4e72817-goog

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[PATCH] [ARM] arch/arm/Kconfig: typo/grammar/punctuation fixes
by Robert P. J. Day 03 Jan '20

03 Jan '20

Various (mostly minor) spelling, grammar and punctuation tweaks for arch/arm/Kconfig. Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9dab073ea..36c9c2fecd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -17,7 +17,7 @@ config POSITION_INDEPENDENT be loaded to and run from that address. This option lifts that restriction, thus allowing the code to be loaded to and executed from almost any address. This logic relies on the relocation - information that is embedded into the binary to support U-Boot + information that is embedded in the binary to support U-Boot relocating itself to the top-of-RAM later during execution. config INIT_SP_RELATIVE @@ -26,7 +26,7 @@ config INIT_SP_RELATIVE U-Boot typically uses a hard-coded value for the stack pointer before relocation. Enable this option to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses - into U-Boot, so that can be loaded and executed at arbitrary + into U-Boot, so that it can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. If this option is enabled, the early stack pointer is set to @@ -57,7 +57,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE hex help The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the - TEXT_OFFSET value written in to the Linux kernel image header. + TEXT_OFFSET value written to the Linux kernel image header. endif endif @@ -121,7 +121,7 @@ config SYS_ARM_MMU select SYS_ARM_CACHE_CP15 help Select if you want MMU-based virtualised addressing space - support by paged memory management. + support via paged memory management. config SYS_ARM_MPU bool 'Use the ARM v7 PMSA Compliant MPU' @@ -136,8 +136,8 @@ config SYS_ARM_MPU # startup. Note that in general these options force the workarounds to be # applied; no CPU-type/version detection exists, unlike the similar options in # the Linux kernel. Do not set these options unless they apply! Also note that -# the following can be machine specific errata. These do have ability to -# provide rudimentary version and machine specific checks, but expect no +# the following can be machine-specific errata. These do have ability to +# provide rudimentary version and machine-specific checks, but expect no # product checks: # CONFIG_ARM_ERRATA_430973 # CONFIG_ARM_ERRATA_454179 @@ -332,7 +332,7 @@ config SYS_CACHELINE_SIZE config ARCH_CPU_INIT bool "Enable ARCH_CPU_INIT" help - Some architectures require a call to arch_cpu_init() + Some architectures require a call to arch_cpu_init(). Say Y here to enable it config SYS_ARCH_TIMER @@ -342,7 +342,7 @@ config SYS_ARCH_TIMER help The ARM Generic Timer (aka arch-timer) provides an architected interface to a timer source on an SoC. - It is mandantory for ARMv8 implementation and widely available + It is mandatory for ARMv8 implementation and widely available on ARMv7 systems. config ARM_SMCCC @@ -385,7 +385,7 @@ config TPL_SYS_THUMB_BUILD default y if SYS_THUMB_BUILD depends on TPL && !ARM64 help - Use this flag to build SPL using the Thumb instruction set for + Use this flag to build TPL using the Thumb instruction set for ARM architectures. Thumb instruction set provides better code density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC. @@ -394,7 +394,7 @@ config TPL_SYS_THUMB_BUILD config SYS_L2CACHE_OFF bool "L2cache off" help - If SoC does not support L2CACHE or one do not want to enable + If SoC does not support L2CACHE or one does not want to enable L2CACHE, choose this option. config ENABLE_ARM_SOC_BOOT0_HOOK @@ -414,7 +414,7 @@ config USE_ARCH_MEMCPY depends on !ARM64 help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SPL_USE_ARCH_MEMCPY @@ -423,7 +423,7 @@ config SPL_USE_ARCH_MEMCPY depends on !ARM64 && SPL help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config TPL_USE_ARCH_MEMCPY @@ -432,7 +432,7 @@ config TPL_USE_ARCH_MEMCPY depends on !ARM64 && TPL help Enable the generation of an optimized version of memcpy. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config USE_ARCH_MEMSET @@ -441,7 +441,7 @@ config USE_ARCH_MEMSET depends on !ARM64 help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SPL_USE_ARCH_MEMSET @@ -450,7 +450,7 @@ config SPL_USE_ARCH_MEMSET depends on !ARM64 && SPL help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config TPL_USE_ARCH_MEMSET @@ -459,7 +459,7 @@ config TPL_USE_ARCH_MEMSET depends on !ARM64 && TPL help Enable the generation of an optimized version of memset. - Such implementation may be faster under some conditions + Such an implementation may be faster under some conditions but may increase the binary size. config SET_STACK_SIZE @@ -467,14 +467,14 @@ config SET_STACK_SIZE default y if ARCH_VERSAL || ARCH_ZYNQMP help This will enable an option to set max stack size that can be - used by u-boot. + used by U-Boot. config STACK_SIZE - hex "Define max stack size that can be used by u-boot" + hex "Define max stack size that can be used by U-Boot" depends on SET_STACK_SIZE default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP help - Defines Max stack size that can be used by u-boot so that the + Define Max stack size that can be used by U-Boot so that the initrd_high will be calculated as base stack pointer minus this stack size. @@ -689,7 +689,7 @@ config TARGET_BCMNS2 help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking - applications + applications. config ARCH_EXYNOS bool "Samsung EXYNOS" @@ -1101,8 +1101,8 @@ config TARGET_LS2080A_EMU select ARMV8_MULTIENTRY select FSL_DDR_SYNC_REFRESH help - Support for Freescale LS2080A_EMU platform - The LS2080A Development System (EMULATOR) is a pre silicon + Support for Freescale LS2080A_EMU platform. + The LS2080A Development System (EMULATOR) is a pre-silicon development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1114,7 +1114,7 @@ config TARGET_LS2080A_SIMU select ARMV8_MULTIENTRY select BOARD_LATE_INIT help - Support for Freescale LS2080A_SIMU platform + Support for Freescale LS2080A_SIMU platform. The LS2080A Development System (QDS) is a pre silicon development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1130,7 +1130,7 @@ config TARGET_LS1088AQDS select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT help - Support for NXP LS1088AQDS platform + Support for NXP LS1088AQDS platform. The LS1088A Development System (QDS) is a high-performance development platform that supports the QorIQ LS1088A Layerscape Architecture processor. @@ -1149,7 +1149,7 @@ config TARGET_LS2080AQDS select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL help - Support for Freescale LS2080AQDS platform + Support for Freescale LS2080AQDS platform. The LS2080A Development System (QDS) is a high-performance development platform that supports the QorIQ LS2080A Layerscape Architecture processor. @@ -1649,7 +1649,7 @@ config TFABOOT default n help Enabling this will make a U-Boot binary that is capable of being - booted via TF-A. + booted via TF-A (Trusted Firmware for Cortex-A). config TI_SECURE_DEVICE bool "HS Device Type Support" -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[PATCH] test_env: don't strip() printenv results
by Stephen Warren 03 Jan '20

03 Jan '20

From: Stephen Warren <swarren(a)nvidia.com> get_env() was originally written to strip() the output of printenv to isolate the test from any whitespace changes in printenv's output. However, this throws away any whitespace in the variable value, which can cause issues when test code expects to see that whitespace. In fact, printenv never adds any whitespace at all, so there's no need to strip. The strip causes a practical problem for test_env_echo_exists() if state_test_env.get_existent_var() happens to choose a U-Boot variable that contains trailing whitespace. This is true for variable boot_targets. With Python 2, get_existent_var() never returned boot_targets so this issue never caused a practical problem. With Python 3, get_existent_var does sometimes return boot_targets, no doubt due to Python 3's different dict hash key order implementation, about 0.5-2% of the time, so this test appears intermittent. With the strip removed, this intermittency is solved, since the test passes for all possible U-Boot variables. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- test/py/tests/test_env.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py index 9bdaef9373fd..6ff38f1020b5 100644 --- a/test/py/tests/test_env.py +++ b/test/py/tests/test_env.py @@ -49,7 +49,7 @@ class StateTestEnv(object): for l in response.splitlines(): if not '=' in l: continue - (var, value) = l.strip().split('=', 1) + (var, value) = l.split('=', 1) self.env[var] = value def get_existent_var(self): -- 2.24.1

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[PATCH v1] mailmap: Update mail address for Igor Opaniuk
by Igor Opaniuk 03 Jan '20

03 Jan '20

My address at Linaro doesn't exist anymore, so people keep getting mail delivery error responses. Map this address to the actual one. Signed-off-by: Igor Opaniuk <igor.opaniuk(a)gmail.com> --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index 98d2131e97..61802f97f6 100644 --- a/.mailmap +++ b/.mailmap @@ -29,6 +29,7 @@ Jagan Teki <jaganna(a)gmail.com> Jagan Teki <jaganna(a)xilinx.com> Jagan Teki <jagannadh.teki(a)gmail.com> Jagan Teki <jagannadha.sutradharudu-teki(a)xilinx.com> +Igor Opaniuk <igor.opaniuk(a)gmail.com> <igor.opaniuk(a)linaro.org> Markus Klotzbuecher <mk(a)denx.de> Paul Burton <paul.burton(a)mips.com> <paul.burton(a)imgtec.com> Prabhakar Kushwaha <prabhakar(a)freescale.com> -- 2.17.1

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