January 2020 - U-Boot

[PATCH 1/2] mtd: spi-nand: Import Toshiba SPI-NAND support
by Robert Marko 04 Jan '20

04 Jan '20

Linux has good support for Toshiba SPI-NAND, so lets import it. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> Tested-by: Luka Kovacic <luka.kovacic(a)sartura.hr> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- drivers/mtd/nand/spi/Makefile | 2 +- drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/toshiba.c | 190 +++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/toshiba.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index dd6bacae34..6c65b187e8 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o +spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index cb8ffa3fa9..67ebbdcb08 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -833,6 +833,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &gigadevice_spinand_manufacturer, &macronix_spinand_manufacturer, &micron_spinand_manufacturer, + &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, }; diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c new file mode 100644 index 0000000000..29846cf4bd --- /dev/null +++ b/drivers/mtd/nand/spi/toshiba.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 exceet electronics GmbH + * Copyright (c) 2018 Kontron Electronics GmbH + * + * Author: Frieder Schrempf <frieder.schrempf(a)kontron.de> + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_TOSHIBA 0x98 +#define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 0) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 0) + return -ERANGE; + + /* 2 bytes reserved for BBM */ + region->offset = 2; + region->length = (mtd->oobsize / 2) - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = { + .ecc = tc58cxgxsx_ooblayout_ecc, + .free = tc58cxgxsx_ooblayout_free, +}; + +static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + u8 mbf = 0; + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, &mbf); + + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + case STATUS_ECC_HAS_BITFLIPS: + case TOSH_STATUS_ECC_HAS_BITFLIPS_T: + /* + * Let's try to retrieve the real maximum number of bitflips + * in order to avoid forcing the wear-leveling layer to move + * data around if it's not necessary. + */ + if (spi_mem_exec_op(spinand->slave, &op)) + return nand->eccreq.strength; + + mbf >>= 4; + + if (WARN_ON(mbf > nand->eccreq.strength || !mbf)) + return nand->eccreq.strength; + + return mbf; + + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info toshiba_spinand_table[] = { + /* 3.3V 1Gb */ + SPINAND_INFO("TC58CVG0S3", 0xC2, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 3.3V 2Gb */ + SPINAND_INFO("TC58CVG1S3", 0xCB, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 3.3V 4Gb */ + SPINAND_INFO("TC58CVG2S0", 0xCD, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 1.8V 1Gb */ + SPINAND_INFO("TC58CYG0S3", 0xB2, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 1.8V 2Gb */ + SPINAND_INFO("TC58CYG1S3", 0xBB, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), + /* 1.8V 4Gb */ + SPINAND_INFO("TC58CYG2S0", 0xBD, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, + tc58cxgxsx_ecc_get_status)), +}; + +static int toshiba_spinand_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + /* + * Toshiba SPI NAND read ID needs a dummy byte, + * so the first byte in id is garbage. + */ + if (id[1] != SPINAND_MFR_TOSHIBA) + return 0; + + ret = spinand_match_and_init(spinand, toshiba_spinand_table, + ARRAY_SIZE(toshiba_spinand_table), + id[2]); + if (ret) + return ret; + + return 1; +} + +static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { + .detect = toshiba_spinand_detect, +}; + +const struct spinand_manufacturer toshiba_spinand_manufacturer = { + .id = SPINAND_MFR_TOSHIBA, + .name = "Toshiba", + .ops = &toshiba_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index be01e1e82e..83eafb184e 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -204,6 +204,7 @@ struct spinand_manufacturer { extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; extern const struct spinand_manufacturer micron_spinand_manufacturer; +extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; /** -- 2.24.1

1 1

SPI NOR stops working if I put Env in MMC
by Mauro Condarelli 04 Jan '20

04 Jan '20

Hi, I'm facing a strange problem that took quite a while to analyze. I'm porting U-Boot to a new board and thus some problem is expected. I am also trying to configure U-Boot in a useful (for my purposes) way. I decided to switch Environment storage from SPI NOR to SD card (in a file in FAT partition. Before switch I had both SPI NOR (MTD) and MMC working. > U-Boot 2020.01-rc5-00074-g57fe7de5a3-dirty (Jan 04 2020 - 01:38:21 +0100) > > CPU: MT7628 Rev 1.2 - Boot from XTAL (3-Byte SPI Addr) > Model: VoCore2 > DRAM: 128 MiB > MMC: mmc@10130000: 0 > Loading Environment from SPI Flash... SF: Detected gd25q128 with page > size 256 Bytes, erase size 4 KiB, total 16 MiB > OK > In: uart2@e00 > Out: uart2@e00 > Err: uart2@e00 > Model: VoCore2 > => mtd list > List of MTD devices: > * nor0 > - type: NOR flash > - block size: 0x1000 bytes > - min I/O: 0x1 bytes > - 0x000000000000-0x000001000000 : "nor0" > - 0x000000000000-0x000000050000 : "u-boot" > - 0x000000050000-0x000000300000 : "kernel" > - 0x000000300000-0x000000ffe000 : "squash" > - 0x000000ffe000-0x000000fff000 : "env" > - 0x000000fff000-0x000001000000 : "factory" > => mmc part > > Partition Map for MMC device 0 -- Partition Type: DOS > > Part Start Sector Num Sectors UUID Type > 1 2048 262144 f31c8249-01 0c > 2 264192 4194304 f31c8249-02 83 > 3 4458496 327680 f31c8249-03 83 > 4 4786176 10737664 f31c8249-04 05 Extd > 5 4788224 2097152 f31c8249-05 83 > 6 6887424 2097152 f31c8249-06 83 > => I made a minimal change in configuration: > mcon@cinderella:/tmp/u-boot$ git diff > diff --git a/configs/vocore_vocore2_defconfig > b/configs/vocore_vocore2_defconfig > index ad1b580431..ece98beea0 100644 > --- a/configs/vocore_vocore2_defconfig > +++ b/configs/vocore_vocore2_defconfig > @@ -1,8 +1,6 @@ > CONFIG_MIPS=y > CONFIG_SYS_TEXT_BASE=0x80010000 > CONFIG_ENV_SIZE=0x00001000 > -CONFIG_ENV_OFFSET=0x00FFE000 > -CONFIG_ENV_SECT_SIZE=0x00001000 > CONFIG_ARCH_MTMIPS=y > CONFIG_BOARD_VOCORE2=y > CONFIG_MIPS_BOOT_FDT=y > @@ -37,8 +35,9 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" > CONFIG_MTDPARTS_DEFAULT="spi0.0:320k(u-boot),2752k(kernel),13304k(filesystem),4k(env),-(factory)" > # CONFIG_ISO_PARTITION is not set > CONFIG_DEFAULT_DEVICE_TREE="vocore_vocore2" > -CONFIG_ENV_IS_IN_SPI_FLASH=y > -CONFIG_ENV_ADDR=0x00FFE000 > +CONFIG_ENV_IS_IN_FAT=y > +CONFIG_ENV_FAT_INTERFACE="mmc" > +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" > # CONFIG_NET is not set > # CONFIG_DM_DEVICE_REMOVE is not set > CONFIG_BLK=y > mcon@cinderella:/tmp/u-boot$ ... but it seems very destructive for spi: > U-Boot 2020.01-rc5-00074-g0cac9383d7-dirty (Jan 04 2020 - 01:55:34 +0100) > > CPU: MT7628 Rev 1.2 - Boot from XTAL (3-Byte SPI Addr) > Model: VoCore2 > DRAM: 128 MiB > MMC: mmc@10130000: 0 > Loading Environment from FAT... OK > In: uart2@e00 > Out: uart2@e00 > Err: uart2@e00 > Model: VoCore2 > => mmc part > > Partition Map for MMC device 0 -- Partition Type: DOS > > Part Start Sector Num Sectors UUID Type > 1 2048 262144 f31c8249-01 0c > 2 264192 4194304 f31c8249-02 83 > 3 4458496 327680 f31c8249-03 83 > 4 4786176 10737664 f31c8249-04 05 Extd > 5 4788224 2097152 f31c8249-05 83 > 6 6887424 2097152 f31c8249-06 83 > => mtd list > Could not find a valid device for spi0.0 > List of MTD devices: > No MTD device found > => I assume some initialization is not done, but I would like some help to debug this as I did *not* change anything in SPI (aside from setting it in .dts). OTOH I had to change a bit MMC handling, but that shouldn't be relevant, or is it? I attach my complete patch against a fairly recent commit (it was "master" a few hours ago). The patch is to the working ENV_IS_IN_SPI_FLASH version. Changes for "not working" with ENV_IS_IN_FAT are above. Please advise. Thanks in Advance Mauro

1 1

Re: pull request u-boot-fsl-qoriq to next branch
by Tom Rini 04 Jan '20

04 Jan '20

On Fri, Jan 03, 2020 at 04:59:03AM +0000, Priyanka Jain wrote: > Dear Tom, > > > > Please find my pull-request for u-boot-fsl-qoriq/master to next branch > > https://travis-ci.org/p-priyanka-jain/u-boot/builds/631797597<https://travis-ci.org/p-priyanka-jain/u-boot/builds/631797597?utm_medium=no…> > > Summary > > updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support > > > > priyankajain > Applied to u-boot/next, thanks! -- Tom

1 0

commit "dm: spi: Avoid setting the speed with every transfer"
by Rasmus Villemoes 04 Jan '20

04 Jan '20

Hi I'm wondering how commit 60e2809a84 (dm: spi: Avoid setting the speed with every transfer) works. AFAIU, the currently selected speed is a property of the SPI master, so suppose we have two slaves, A which has max_hz = 10MHz and B which has max_hz = 20MHz. Now suppose we do transfers to A, then B, then A again. The third time we still compute speed = 10MHz, but since that matches what we cached in slave->speed, we don't call spi_set_speed_mode(), hence we proceed to do the xfer with a too large speed? I'm probably missing something obvious here since the commit is more than 4 years old. Thanks, Rasmus

2 2

[U-Boot] [PATCH 0/4] arm: mxs: mxs_set_gpmiclk
by Rasmus Villemoes 04 Jan '20

04 Jan '20

While trying to implement an mxs_set_gpmiclk() I stumbled on a few minor things. Rasmus Villemoes (4): arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspX arm: mxs: fix comments in arch_cpu_init to match the code arm: mxs: be more careful when enabling gpmi_clk arm: mxs: implement mxs_set_gpmiclk arch/arm/cpu/arm926ejs/mxs/clock.c | 41 +++++++++++++++++++ arch/arm/cpu/arm926ejs/mxs/mxs.c | 9 ++-- arch/arm/include/asm/arch-mxs/clock.h | 1 + .../include/asm/arch-mxs/regs-clkctrl-mx23.h | 6 ++- .../include/asm/arch-mxs/regs-clkctrl-mx28.h | 15 ++++--- 5 files changed, 62 insertions(+), 10 deletions(-) -- 2.20.1

4 7

[PATCH 1/1] efi_loader: define all known warning status codes
by Heinrich Schuchardt 04 Jan '20

04 Jan '20

Of all warning status codes up to now only EFI_WARN_DELETE_FAILURE is defined. The patch adds the missing definitions for later usage. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- .mailmap | 1 + include/efi.h | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/.mailmap b/.mailmap index 98d2131e97..dec2abeffa 100644 --- a/.mailmap +++ b/.mailmap @@ -24,6 +24,7 @@ Boris Brezillon <bbrezillon(a)kernel.org> <boris.brezillon(a)bootlin.com> Boris Brezillon <bbrezillon(a)kernel.org> <boris.brezillon(a)free-electrons.com> Dirk Behme <dirk.behme(a)googlemail.com> Fabio Estevam <fabio.estevam(a)nxp.com> +Heinrich Schuchardt <xypron.glpk(a)gmx.de> Jagan Teki <402jagan(a)gmail.com> Jagan Teki <jaganna(a)gmail.com> Jagan Teki <jaganna(a)xilinx.com> diff --git a/include/efi.h b/include/efi.h index 5f415a99cc..e12697a5d5 100644 --- a/include/efi.h +++ b/include/efi.h @@ -91,7 +91,13 @@ typedef struct { #define EFI_IP_ADDRESS_CONFLICT (EFI_ERROR_MASK | 34) #define EFI_HTTP_ERROR (EFI_ERROR_MASK | 35) -#define EFI_WARN_DELETE_FAILURE 2 +#define EFI_WARN_UNKNOWN_GLYPH 1 +#define EFI_WARN_DELETE_FAILURE 2 +#define EFI_WARN_WRITE_FAILURE 3 +#define EFI_WARN_BUFFER_TOO_SMALL 4 +#define EFI_WARN_STALE_DATA 5 +#define EFI_WARN_FILE_SYSTEM 6 +#define EFI_WARN_RESET_REQUIRED 7 typedef unsigned long efi_status_t; typedef u64 efi_physical_addr_t; -- 2.24.1

2 1

i2c_class_init problem
by Michael Nazzareno Trimarchi 04 Jan '20

04 Jan '20

Hi Simon U-Boot SPL 2020.01-rc5-00071-g82f6f6e4e4-dirty (Jan 04 2020 - 13:39:54 +0100) spl_early_init i2c_uclass_init: highest alias id is 2 i2c_post_bind: i2c@30a20000, req_seq=-1 i2c_post_bind: i2c@30a20000, new req_seq=3 i2c_post_bind: i2c@30a40000, req_seq=-1 i2c_post_bind: i2c@30a40000, new req_seq=4 When I try to use usb bus from spl, I have a strange mapping of i2c bus i2c1 and i2c3 are in use (ok) and defined in uboot.dtsi part. req_seq get the max alias and add 1 so i2c1 is 3 and i2c3 is 4. Now all the function that need to work for reading in my case the eeprom needs to use 3 and 4. Can you explain a bit more how this should work? Michael -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com |

1 1

[PATCH 1/3] mx7dsabresd: Fix the pmic_get() parameter in the DM case
by Fabio Estevam 04 Jan '20

04 Jan '20

When pmic_get() is used with DM the first parameter must be the complete node name plus the unit address, so fix it accordingly. Reported-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index f1120d67e3..05cf8c8c7c 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -326,7 +326,7 @@ int power_init_board(void) struct udevice *dev; int ret, dev_id, rev_id; - ret = pmic_get("pfuze3000", &dev); + ret = pmic_get("pfuze3000@08", &dev); if (ret == -ENODEV) return 0; if (ret != 0) -- 2.17.1

3 8

[PATCH v1] mach-imx: nandbcb: improve cmd help
by Igor Opaniuk 04 Jan '20

04 Jan '20

From: Igor Opaniuk <igor.opaniuk(a)toradex.com> Add info about supported i.MX7, improve details the usage of bcbonly subcommand. Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> --- arch/arm/mach-imx/cmd_nandbcb.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index 9d3ed1aac3..334cc0766e 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -590,11 +590,14 @@ static char nandbcb_help_text[] = "update addr off|partition len - update 'len' bytes starting at\n" " 'off|part' to memory address 'addr', skipping bad blocks\n" "bcbonly fw-size fw1-off [fw2-off] - write only BCB (FCB and DBBT)\n" - " where `fw-size` is fw sizes in bytes, `fw1-off` and\n" - " and `fw2-off` - firmware offsets "; + " where `fw-size` is fw sizes in bytes, `fw1-off`\n" + " and `fw2-off` - firmware offsets\n" + " FIY, BCB isn't erased automatically, so mtd erase should\n" + " be called in advance before writing new BCB:\n" + " > mtd erase mx7-bcb"; #endif U_BOOT_CMD(nandbcb, 5, 1, do_nandbcb, - "i.MX6 Nand BCB", + "i.MX6/i.MX7 NAND Boot Control Blocks write", nandbcb_help_text ); -- 2.17.1

3 2

[PATCH] arm: imx: Default to SYS_THUMB_BUILD for i.MX6/7
by Tom Rini 04 Jan '20

04 Jan '20

In the case of i.MX6 and i.MX7 family SoCs it is safe (from an errata point of view) to use thumb2 by default to save space. Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9dab073ea14..31c07d9b0b4a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -823,6 +823,7 @@ config ARCH_MX7ULP select CPU_V7A select ROM_UNIFIED_SECTIONS imply MXC_GPIO + imply SYS_THUMB_BUILD config ARCH_MX7 bool "Freescale MX7" @@ -833,6 +834,7 @@ config ARCH_MX7 select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE imply MXC_GPIO + imply SYS_THUMB_BUILD config ARCH_MX6 bool "Freescale MX6" @@ -840,8 +842,8 @@ config ARCH_MX6 select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE - select SYS_THUMB_BUILD if SPL imply MXC_GPIO + imply SYS_THUMB_BUILD if ARCH_MX6 config SPL_LDSCRIPT -- 2.17.1

3 3