January 2020 - U-Boot

[PATCH V2 1/3] imx8mn: evk: add README
by Peng Fan 08 Jan '20

08 Jan '20

Add a README for users to build a workable image. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: Update README follow Fabio's comments board/freescale/imx8mn_evk/README | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 board/freescale/imx8mn_evk/README diff --git a/board/freescale/imx8mn_evk/README b/board/freescale/imx8mn_evk/README new file mode 100644 index 0000000000..ff3d15c02b --- /dev/null +++ b/board/freescale/imx8mn_evk/README @@ -0,0 +1,37 @@ +U-Boot for the NXP i.MX8MN EVK board + +Quick Start +=========== +- Build the ARM Trusted firmware binary +- Get firmware-imx package +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +====================================== +Note: srctree is U-Boot source directory +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +branch: imx_4.19.35_1.1.0 +$ make PLAT=imx8mn bl31 +$ cp build/imx8mn/release/bl31.bin $(srctree) + +Get the ddr firmware +============================= +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin +$ chmod +x firmware-imx-8.5.bin +$ ./firmware-imx-8.5 +$ cp firmware-imx-8.5/firmware/ddr/synopsys/ddr4*.bin $(srctree) + +Build U-Boot +============ +$ export CROSS_COMPILE=aarch64-poky-linux- +$ make imx8mn_ddr4_evk_defconfig +$ export ATF_LOAD_ADDR=0x960000 +$ make flash.bin + +Burn the flash.bin to MicroSD card offset 32KB +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot switch to SD boot -- 2.16.4

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fitImage align 8-byte for ARM64
by Matthias Schoepfer 08 Jan '20

08 Jan '20

Hi! I have had trouble booting a fitImage packed kernel for dragonboard410c, which is an ARM64 platform. After days and days of debugging, I found that the fdt is 4-byte aligned. But within the linux kernel, Documentation/arm64/booting.txt says, fdt must be 8 byte aligned. If I change the alignment by means of fdt_high, the Kernel boots, otherwise, it hangs. Is there an option to align the fitImage to 8-byte boundaries, and if not, is it feasible to submit a patch or will this never have a chance to get merged?! Thanks and Regards, Matthias Schöpfer -- Dr.-Ing. Matthias Schöpfer matthias.schoepfer(a)googlemail.com

4 6

[PATCH RESEND] usbtty: fix possible alignment issues
by Seung-Woo Kim 08 Jan '20

08 Jan '20

With gcc9, below warnings are shown: drivers/serial/usbtty.c: In function 'usbtty_init_strings': drivers/serial/usbtty.c:590:44: warning: taking address of packed member of 'struct usb_string_descriptor' may result in an unaligned pointer value [-Waddress-of-packed-member] 590 | str2wide (CONFIG_USBD_MANUFACTURER, string->wData); | ~~~~~~^~~~~~~ drivers/serial/usbtty.c:596:44: warning: taking address of packed member of 'struct usb_string_descriptor' may result in an unaligned pointer value [-Waddress-of-packed-member] 597 | str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData); | ~~~~~~^~~~~~~ drivers/serial/usbtty.c:603:33: warning: taking address of packed member of 'struct usb_string_descriptor' may result in an unaligned pointer value [-Waddress-of-packed-member] 604 | str2wide (serial_number, string->wData); | ~~~~~~^~~~~~~ drivers/serial/usbtty.c:610:49: warning: taking address of packed member of 'struct usb_string_descriptor' may result in an unaligned pointer value [-Waddress-of-packed-member] 611 | str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData); | ~~~~~~^~~~~~~ drivers/serial/usbtty.c:617:50: warning: taking address of packed member of 'struct usb_string_descriptor' may result in an unaligned pointer value [-Waddress-of-packed-member] 618 | str2wide (CONFIG_USBD_DATA_INTERFACE_STR, string->wData); | ~~~~~~^~~~~~~ drivers/serial/usbtty.c:623:50: warning: taking address of packed member of 'struct usb_string_descriptor' may result in an unaligned pointer value [-Waddress-of-packed-member] 624 | str2wide (CONFIG_USBD_CTRL_INTERFACE_STR, string->wData); | ~~~~~~^~~~~~~ Fix the issues by using packed structure. Ref: commit 616ebd8b9cb4 ("usb: composite: fix possible alignment issues") Signed-off-by: Seung-Woo Kim <sw0312.kim(a)samsung.com> --- resend with proper e-mail address --- drivers/serial/usbtty.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index f1c1a260da..54e67dd0d1 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -48,6 +48,8 @@ #define CONFIG_USBD_DATA_INTERFACE_STR "Bulk Data Interface" #define CONFIG_USBD_CTRL_INTERFACE_STR "Control Interface" +typedef struct { __le16 val; } __attribute__((aligned(16))) __le16_packed; + /* * Buffers to hold input and output data */ @@ -372,14 +374,15 @@ static int fill_buffer (circbuf_t * buf); void usbtty_poll (void); /* utility function for converting char* to wide string used by USB */ -static void str2wide (char *str, u16 * wide) +static void str2wide (char *str, void *wide) { int i; + __le16_packed *tmp = wide; for (i = 0; i < strlen (str) && str[i]; i++){ #if defined(__LITTLE_ENDIAN) - wide[i] = (u16) str[i]; + tmp[i].val = (u16) str[i]; #elif defined(__BIG_ENDIAN) - wide[i] = ((u16)(str[i])<<8); + tmp[i].val = ((u16)(str[i])<<8); #else #error "__LITTLE_ENDIAN or __BIG_ENDIAN undefined" #endif -- 2.19.2

2 3

[PATCH] spl: fit: enable hash control even without signature
by Dario Binacchi 08 Jan '20

08 Jan '20

The function "fit_image_verify_with_data" that performs the integrity protection of FIT images is already able to correctly manage the device tree nodes that require signature and/or hash control. Tests with device tree with or without hash nodes but certainly not signed have given positive results. Furthermore, the hash calculation is performed only if the hash property has been detected, without adding unnecessary calculations. It is therefore useless and limiting to enable hash control only in the case of a signed image. Signed-off-by: Dario Binacchi <dariobin(a)libero.it> --- common/spl/spl_fit.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index cbc00a4e7c..58ba40cb2f 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -242,14 +242,12 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, src = (void *)data; } -#ifdef CONFIG_SPL_FIT_SIGNATURE printf("## Checking hash(es) for Image %s ... ", fit_get_name(fit, node, NULL)); if (!fit_image_verify_with_data(fit, node, src, length)) return -EPERM; puts("OK\n"); -#endif #ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS board_fit_image_post_process(&src, &length); -- 2.24.0

2 1

[PATCH v1 0/1] arm: Add support for SoC S5P4418
by Stefan Bosch 07 Jan '20

07 Jan '20

This patch adds support for SAMSUNG's ARM Cortex-A9 based S5P4418 SoC, especially FriendlyARM's NanoPi2 and NanoPC-T2 boards. It is based on https://github.com/friendlyarm/u-boot/tree/nanopi2-v2016.01. For v2016.01 I have also made a working SPL (FriendlyARM U-Boot is using a closed source 2nd-bootloader). My plan is to migrate this also to the current U-Boot. Issues: Please send me a value for "#define MACH_TYPE_S5P4418" for arch/arm/include/asm/mach-types.h. The size of the patch is over 700kB, so I will upload it on http://www.denx.de/wiki/attach/U-Boot/TooBigPatches if not otherwise instructed.

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[U-Boot] [PATCH 1/2] imx: add imx8x capricorn giedi board
by Anatolij Gustschin 07 Jan '20

07 Jan '20

Add support for i.MX8X based Capricorn Giedi SoM. Supported interfaces: GPIO, ENET, eMMC, I2C, UART. Console output: U-Boot SPL 2019.10-00178-g6e34009eee (Oct 21 2019 - 18:16:42 +0200) Trying to boot from MMC1 Load image from MMC/SD 0x3e000 U-Boot 2019.10-00178-g6e34009eee (Oct 21 2019 - 18:16:42 +0200) ##v01.07 CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 24C Model: Siemens Giedi Board: Capricorn Build: SCFW 65afe5f6, SECO-FW 9d71fd5b, ATF d6451cc Boot: MMC0 DRAM: 1022 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial@5a080000 Out: serial@5a080000 Err: serial@5a080000 Net: eth1: ethernet@5b050000 [PRIME] Autobooting in 1 seconds, press "<Esc><Esc>" to stop Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8-giedi.dts | 10 + arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi | 133 +++++++++ arch/arm/dts/imx8qxp-capricorn.dtsi | 285 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/siemens/capricorn/Kconfig | 12 + board/siemens/capricorn/MAINTAINERS | 9 + board/siemens/capricorn/Makefile | 12 + board/siemens/capricorn/board.c | 443 ++++++++++++++++++++++++++++ board/siemens/capricorn/imximage.cfg | 22 ++ board/siemens/capricorn/spl.c | 47 +++ board/siemens/capricorn/uboot-container.cfg | 13 + board/siemens/common/factoryset.c | 2 + configs/giedi_defconfig | 99 +++++++ include/configs/capricorn-common.h | 190 ++++++++++++ include/configs/giedi.h | 19 ++ include/configs/siemens-ccp-common.h | 20 ++ include/configs/siemens-env-common.h | 202 +++++++++++++ 18 files changed, 1526 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8-giedi.dts create mode 100644 arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi create mode 100644 arch/arm/dts/imx8qxp-capricorn.dtsi create mode 100644 board/siemens/capricorn/Kconfig create mode 100644 board/siemens/capricorn/MAINTAINERS create mode 100644 board/siemens/capricorn/Makefile create mode 100644 board/siemens/capricorn/board.c create mode 100644 board/siemens/capricorn/imximage.cfg create mode 100644 board/siemens/capricorn/spl.c create mode 100644 board/siemens/capricorn/uboot-container.cfg create mode 100644 configs/giedi_defconfig create mode 100644 include/configs/capricorn-common.h create mode 100644 include/configs/giedi.h create mode 100644 include/configs/siemens-ccp-common.h create mode 100644 include/configs/siemens-env-common.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3b8dc2f..669d99e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -647,7 +647,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ fsl-imx8qxp-colibri.dtb \ - fsl-imx8qxp-mek.dtb + fsl-imx8qxp-mek.dtb \ + imx8-giedi.dtb dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \ imx8mm-evk.dtb diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts new file mode 100644 index 0000000..0dbfef2 --- /dev/null +++ b/arch/arm/dts/imx8-giedi.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +#include "imx8qxp-capricorn.dtsi" + +/ { + model = "Siemens Giedi"; +}; diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi new file mode 100644 index 0000000..1cf58fc --- /dev/null +++ b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_dma_lpuart2 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&lpuart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8qxp-capricorn.dtsi new file mode 100644 index 0000000..db5653e --- /dev/null +++ b/arch/arm/dts/imx8qxp-capricorn.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + * + * Copyright 2019 Siemens AG + * + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" +#include "imx8qxp-capricorn-u-boot.dtsi" + +/ { + model = "Siemens Giedi"; + compatible = "siemens,capricorn", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; + stdout-path = &lpuart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + run { + label = "run"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + flt { + label = "flt"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + svc { + label = "svc"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_tx { + label = "com1-tx"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_rx { + label = "com1-rx"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_tx { + label = "com2-tx"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_rx { + label = "com2-rx"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + cloud { + label = "cloud"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + wlan { + label = "wlan"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg1 { + label = "dbg1"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg2 { + label = "dbg2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg3 { + label = "dbg3"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg4 { + label = "dbg4"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + muxcgrp: imx8qxp-som { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 + SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020 + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021 + //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 + + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */ + >; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + clock-frequency=<52000000>; + no-1-8-v; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&fec1 { + status ="disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rmii"; + + phy-handle = <&ethphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index d17760e..1f25e9c 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -60,11 +60,17 @@ config TARGET_IMX8QXP_MEK select BOARD_LATE_INIT select IMX8QXP +config TARGET_GIEDI + bool "Support i.MX8QXP Capricorn Giedi board" + select BOARD_LATE_INIT + select IMX8QXP + endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" +source "board/siemens/capricorn/Kconfig" endif diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig new file mode 100644 index 0000000..ed1f793 --- /dev/null +++ b/board/siemens/capricorn/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GIEDI + +config SYS_BOARD + default "capricorn" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "giedi" + +endif diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS new file mode 100644 index 0000000..5d81aaf --- /dev/null +++ b/board/siemens/capricorn/MAINTAINERS @@ -0,0 +1,9 @@ +CAPRICORN BOARD +M: Anatolij Gustschin <agust(a)denx.de> +S: Maintained +F: board/siemens/capricorn/ +F: include/configs/capricorn-common.h +F: include/configs/giedi.h +F: include/configs/siemens-ccp-common.h +F: include/configs/siemens-env-common.h +F: configs/giedi_defconfig diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile new file mode 100644 index 0000000..d5846cc --- /dev/null +++ b/board/siemens/capricorn/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Siemens AG +# + +obj-y += board.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += ../common/factoryset.o +endif diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c new file mode 100644 index 0000000..d73b88b --- /dev/null +++ b/board/siemens/capricorn/board.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + * + * Copyright 2019 Siemens AG + * + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <netdev.h> +#include <env_internal.h> +#include <fsl_esdhc_imx.h> +#include <i2c.h> +#include <led.h> +#include <pca953x.h> +#include <power-domain.h> +#include <asm/gpio.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/sys_proto.h> +#ifndef CONFIG_SPL +#include <asm/arch-imx8/clock.h> +#endif +#include "../common/factoryset.h" + +#define GPIO_PAD_CTRL \ + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL \ + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL \ + ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart2_pads[] = { + SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +int board_early_init_f(void) +{ + /* Set UART clock root to 80 MHz */ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + ret |= sc_pm_setup_uart(SC_R_UART_2, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#define ENET_PHY_RESET IMX_GPIO_NR(0, 3) +#define ENET_TEST_1 IMX_GPIO_NR(0, 8) +#define ENET_TEST_2 IMX_GPIO_NR(0, 9) + +/*#define ETH_IO_TEST*/ +static iomux_cfg_t enet_reset[] = { + SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +#ifdef ETH_IO_TEST + /* GPIO0.IO08 MODE3: TXD0 */ + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) | + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + /* GPIO0.IO09 MODE3: TXD1 */ + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) | + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +#endif +}; + +static void enet_device_phy_reset(void) +{ + int ret = 0; + + imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset)); + + ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset"); + if (!ret) { + gpio_direction_output(ENET_PHY_RESET, 1); + gpio_set_value(ENET_PHY_RESET, 0); + /* SMSC9303 TRM chapter 14.5.2 */ + udelay(200); + gpio_set_value(ENET_PHY_RESET, 1); + } else { + printf("ENET RESET failed!\n"); + } + +#ifdef ETH_IO_TEST + ret = gpio_request(ENET_TEST_1, "enet_test1"); + if (!ret) { + int i; + + printf("ENET TEST 1!\n"); + for (i = 0; i < 20; i++) { + gpio_direction_output(ENET_TEST_1, 1); + gpio_set_value(ENET_TEST_1, 0); + udelay(50); + gpio_set_value(ENET_TEST_1, 1); + udelay(50); + } + gpio_free(ENET_TEST_1); + } else { + printf("GPIO for ENET TEST 1 failed!\n"); + } + ret = gpio_request(ENET_TEST_2, "enet_test2"); + if (!ret) { + int i; + + printf("ENET TEST 2!\n"); + for (i = 0; i < 20; i++) { + gpio_direction_output(ENET_TEST_2, 1); + gpio_set_value(ENET_TEST_2, 0); + udelay(50); + gpio_set_value(ENET_TEST_2, 1); + udelay(50); + } + gpio_free(ENET_TEST_2); + } else { + printf("GPIO for ENET TEST 2 failed!\n"); + } +#endif +} + +int setup_gpr_fec(void) +{ + sc_ipc_t ipc_handle = -1; + sc_err_t err = 0; + unsigned int test; + + /* + * TX_CLK_SEL: it controls a mux between clock coming from the pad 50M + * input pin and clock generated internally to connectivity subsystem + * 0: internal clock + * 1: external clock ---> your choice for RMII + * + * CLKDIV_SEL: it controls a div by 2 on the internal clock path à + * it should be don’t care when using external clock + * 0: non-divided clock + * 1: clock divided by 2 + * 50_DISABLE or 125_DISABLE: + * it’s used to disable the clock tree going outside the chip + * when reference clock is generated internally. + * It should be don’t care when reference clock is provided + * externally. + * 0: clock is enabled + * 1: clock is disabled + * + * SC_C_TXCLK = 24, + * SC_C_CLKDIV = 25, + * SC_C_DISABLE_50 = 26, + * SC_C_DISABLE_125 = 27, + */ + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#endif + +static int setup_fec(void) +{ + setup_gpr_fec(); + /* Reset ENET PHY */ + enet_device_phy_reset(); + return 0; +} + +void reset_cpu(ulong addr) +{ +} + +#ifndef CONFIG_SPL_BUILD +/* LED's */ +static int board_led_init(void) +{ + struct udevice *bus, *dev; + u8 pca_led[2] = { 0x00, 0x00 }; + int ret; + + /* init all GPIO LED's */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + /* enable all leds on PCA9552 */ + ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus); + if (ret) { + printf("ERROR: I2C get %d\n", ret); + return ret; + } + + ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev); + if (ret) { + printf("ERROR: PCA9552 probe failed\n"); + return ret; + } + + ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led)); + if (ret) { + printf("ERROR: PCA9552 write failed\n"); + return ret; + } + + mdelay(1); + return ret; +} +#endif /* !CONFIG_SPL_BUILD */ + +int checkboard(void) +{ + puts("Board: Capricorn\n"); + + build_info(); + print_bootinfo(); + return 0; +} + +int board_init(void) +{ + setup_fec(); + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if (autodetect_str && (strcmp(autodetect_str, "yes") == 0)) + return 1; + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +#ifndef CONFIG_SPL_BUILD +int factoryset_read_eeprom(int i2c_addr); + +static int load_parameters_from_factoryset(void) +{ + int ret; + + ret = factoryset_read_eeprom(EEPROM_I2C_ADDR); + if (ret) + return ret; + + return factoryset_env_set(); +} + +int board_late_init(void) +{ + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + /* Init LEDs */ + if (board_led_init()) + printf("I2C LED init failed\n"); + + /* Set environment from factoryset */ + if (load_parameters_from_factoryset()) + printf("Loading factoryset parameters failed!\n"); + + return 0; +} + +/* Service button */ +#define MAX_PIN_NUMBER 128 +#define BOARD_DEFAULT_BUTTON_GPIO IMX_GPIO_NR(1, 31) + +unsigned char get_button_state(char * const envname, unsigned char def) +{ + int button = 0; + int gpio; + char *ptr_env; + + /* If button is not found we take default */ + ptr_env = env_get(envname); + if (!ptr_env) { + printf("Using default: %u\n", def); + gpio = def; + } else { + gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0); + if (gpio > MAX_PIN_NUMBER) + gpio = def; + } + + gpio_request(gpio, ""); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + + return button; +} + +/* + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int button = 0; + + button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO); + + if (argc > 1) + printf("Button state: %u\n", button); + + return button; +} + +U_BOOT_CMD( + usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton, + "Return the status of user button", + "[print]" +); + +#define ERST IMX_GPIO_NR(0, 3) + +static int +do_eth_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + gpio_request(ERST, "ERST"); + gpio_direction_output(ERST, 0); + udelay(200); + gpio_set_value(ERST, 1); + return 0; +} + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset, + "Reset eth phy", + "[print]" +); +#endif /* ! CONFIG_SPL_BUILD */ diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg new file mode 100644 index 0000000..8660e50 --- /dev/null +++ b/board/siemens/capricorn/imximage.cfg @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU capricorn-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c new file mode 100644 index 0000000..47fe86c --- /dev/null +++ b/board/siemens/capricorn/spl.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Copyright 2019 Siemens AG + * + */ +#include <common.h> +#include <spl.h> +#include <dm.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/siemens/capricorn/uboot-container.cfg b/board/siemens/capricorn/uboot-container.cfg new file mode 100644 index 0000000..8165811 --- /dev/null +++ b/board/siemens/capricorn/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QX +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c index 7715ddf..0d3701c 100644 --- a/board/siemens/common/factoryset.c +++ b/board/siemens/common/factoryset.c @@ -13,7 +13,9 @@ #include <env_internal.h> #include <i2c.h> #include <asm/io.h> +#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB) #include <asm/arch/cpu.h> +#endif #include <asm/arch/sys_proto.h> #include <asm/unaligned.h> #include <net.h> diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig new file mode 100644 index 0000000..5a26f54 --- /dev/null +++ b/configs/giedi_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" +CONFIG_TARGET_GIEDI=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MV88E61XX_SWITCH=y +CONFIG_MV88E61XX_88E6020_FAMILY=y +CONFIG_MV88E61XX_CPU_PORT=5 +CONFIG_MV88E61XX_PHY_PORTS=0x7 +CONFIG_MV88E61XX_FIXED_PORTS=0x0 +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_SPL_WDT is not set +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h new file mode 100644 index 0000000..41b9005 --- /dev/null +++ b/include/configs/capricorn-common.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * Copyright 2019 Siemens AG + */ + +#ifndef __IMX8X_CAPRICORN_H +#define __IMX8X_CAPRICORN_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#include "siemens-env-common.h" +#include "siemens-ccp-common.h" + +/* SPL config */ +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_FACTORYSET + +#undef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07") + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Commands */ +#define CONFIG_CMD_READ + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +#define CONFIG_FEC_XCV_TYPE RMII +#define FEC_QUIRK_ENET_MAC + +/* ENET1 connects to base board and MUX with ESAI */ +#define CONFIG_FEC_ENET_DEV 1 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth1" + +/* I2C Configuration */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_I2C_SPEED 400000 +/* EEPROM */ +#define EEPROM_I2C_BUS 0 /* I2C0 */ +#define EEPROM_I2C_ADDR 0x50 +/* PCA9552 */ +#define PCA9552_1_I2C_BUS 1 /* I2C1 */ +#define PCA9552_1_I2C_ADDR 0x60 +#endif /* !CONFIG_SPL_BUILD */ + +/* AHAB */ +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#define MFG_ENV_SETTINGS_DEFAULT \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "clk_ignore_unused "\ + "\0" \ + "kboot=booti\0"\ + "bootcmd_mfg=run mfgtool_args;" \ + "if iminfo ${initrd_addr}; then " \ + "if test ${tee} = yes; then " \ + "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \ + "else " \ + "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \ + "fi; " \ + "else " \ + "echo \"Run fastboot ...\"; fastboot 0; " \ + "fi;\0" + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define CONFIG_MFG_ENV_SETTINGS \ + MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + AHAB_ENV \ + ENV_COMMON \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP2\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x88000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "netdev=eth0\0" \ + "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \ + "hostname=capricorn\0" \ + ENV_EMMC \ + ENV_NET + +#define CONFIG_BOOTCOMMAND \ + "if usrbutton; then " \ + "run flash_self_test; " \ + "reset; " \ + "fi;" \ + "run flash_self;" \ + "reset;" + +/* Default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x80280000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_ENV + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#define CONFIG_SYS_MMC_ENV_PART 2 /* user area */ + +/* On CCP board, USDHC1 is for eMMC */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* eMMC */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +/* DDR3 board total DDR is 1 GB */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Console buffer and boot args */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ + +#endif /* __IMX8X_CAPRICORN_H */ diff --git a/include/configs/giedi.h b/include/configs/giedi.h new file mode 100644 index 0000000..dabb1fb --- /dev/null +++ b/include/configs/giedi.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Siemens AG + * + */ + +#ifndef __GIEDI_H +#define __GIEDI_H + +#include "capricorn-common.h" + +#undef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07") + +/* DDR3 board total DDR is 1 GB */ +#undef PHYS_SDRAM_1_SIZE +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ + +#endif /* __GIEDI_H */ diff --git a/include/configs/siemens-ccp-common.h b/include/configs/siemens-ccp-common.h new file mode 100644 index 0000000..ad2a082 --- /dev/null +++ b/include/configs/siemens-ccp-common.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Be very careful updating CONFIG_IDENT_STRING + * This string will control the update flow whether an U-Boot should be + * updated or not. If the version of installed U-Boot (in flash) is smaller + * than the version to be installed (from update file), an update will + * be performed. + * + * General rules: + * 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number + * to identify the following strings after easily. Don't change them! + * + * 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version + * change, e.g. from 2015.04 to 2018.03 + * + * 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade + * U-Boot within an U-Boot version. + */ +#define CCP_IDENT_MAGIC " ##v" +#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR + diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h new file mode 100644 index 0000000..64ca0c5 --- /dev/null +++ b/include/configs/siemens-env-common.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Common env settings */ + +/** set_bootargs() + * input: + * console: string, tty, etc. + * baudrate: string, tty baudrate + * testargs: string + * optargs: string + * output: + * bootargs: string, default boot string + */ +#define ENV_BOOTARGS_DEFAULT "set_bootargs=" \ + "setenv bootargs " \ + "console=${console} " \ + "${testargs} " \ + "${optargs}\0" + +/** set_bootargs_net() + * input: + * kernel_name: + * dtb_name: + * project_dir: + * output: + */ +#define ENV_NET_FCT_NETARGS "set_bootargs_net=" \ + "run set_bootargs;" \ + "setenv bootfile ${project_dir}/boot/${kernel_name};" \ + "setenv bootdtb ${project_dir}/boot/${dtb_name_nfs}.dtb;" \ + "setenv rootpath /home/projects/${project_dir}/;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" + +/** net_nfs() + * input: + * output: + */ +#define ENV_NET_FCT_BOOT "net_nfs=" \ + "echo Booting from network ...; " \ + "run set_bootargs_net; " \ + "tftpboot ${dtb_loadaddr} ${serverip}:${bootdtb};" \ + "if test $? -eq 1;" \ + "then " \ + "echo Loading default.dtb!;" \ + "tftpboot ${dtb_loadaddr} ${serverip}:${project_dir}/boot/${dtb_name_default}.dtb;" \ + "fi;" \ + "tftpboot ${kernel_loadaddr} ${serverip}:${bootfile};" \ + "printenv bootargs;" \ + "booti ${kernel_loadaddr} - ${dtb_loadaddr}\0" + +/** check_update() + * input: + * upgrade_available: [0|1], if set to 1 check bootcount variables + * bootcount: int, bootcount + * bootlimit: int, limit cootcount + * toggle_partition(): - toggles active partition set + * output: + * upgrade_available: [0|1], set to 0 if bootcount > bootlimit + */ +#define ENV_FCT_CHECK_UPGRADE "check_upgrade="\ + "if test ${upgrade_available} -eq 1; " \ + "then " \ + "echo upgrade_available is set; " \ + "if test ${bootcount} -gt ${bootlimit}; " \ + "then " \ + "setenv upgrade_available 0;" \ + "echo toggle partition;" \ + "run toggle_partition;" \ + "fi;" \ + "fi;\0" + +/** toggle_partition() + * input: + * partitionset_active: [A|B], selected partition set + * output: + * partitionset_active: [A|B], toggle + */ +#define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; " \ + "then " \ + "setenv partitionset_active B; " \ + "env delete A; " \ + "fi;" \ + "if test -n ${B}; "\ + "then " \ + "setenv partitionset_active A; " \ + "env delete B; " \ + "fi;" \ + "saveenv\0" + +/** set_partition() + * input: + * partitionset_active: [A|B], selected partition set + * rootfs_name: string, mmc device file in kernel, e.g. /dev/mmcblk0 + * output: + * mmc_active_vol: string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2 + * mmc_part_nr: int, partition number of mmc, e.g. /dev/mmcblk0p2 --> 2 + */ +#define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; " \ + "then " \ + "setenv mmc_part_nr 1;" \ + "fi;" \ + "if test -n ${B}; " \ + "then " \ + "setenv mmc_part_nr 2;" \ + "fi;" \ + "setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} \0" + +/** set_bootargs_mmc() + * input: + * bootargs: string, default bootargs + * mmc_active_vol string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2 + * ip_method: string, [none|?] + * output: + * bootargs: string + */ +#define ENV_EMMC_FCT_SET_EMMC_BOOTARGS "set_bootargs_mmc=" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_active_vol} rw " \ + "rootdelay=1 rootwait " \ + "rootfstype=ext4 " \ + "ip=${ip_method} \0" + +/** mmc_load_bootfiles() + * input: + * mmc_part_nr: + * dtb_loadaddr: + * dtb_name: + * kernel_loadaddr: + * kernel_name: + */ +#define ENV_EMMC_FCT_LOADFROM_EMMC "mmc_load_bootfiles=" \ + "echo Loading from eMMC ...;" \ + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name}.dtb;" \ + "if test $? -eq 1;" \ + "then " \ + "echo Loading default.dtb!;" \ + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name_default}.dtb;" \ + "fi;" \ + "ext4load mmc 0:${mmc_part_nr} ${kernel_loadaddr} boot/${kernel_name};" \ + "printenv bootargs;\0" + +/** mmc_boot() + * input: + * mmc_part_nr: + * dtb_loadaddr: + * dtb_name: + * kernel_loadaddr: + * kernel_name: + */ +#define ENV_EMMC_FCT_EMMC_BOOT "mmc_boot=" \ + "run set_bootargs;" \ + "run check_upgrade; " \ + "run set_partition;" \ + "run set_bootargs_mmc;" \ + "run mmc_load_bootfiles;" \ + "echo Booting from eMMC ...; " \ + "booti ${kernel_loadaddr} - ${dtb_loadaddr} \0" + +#define ENV_EMMC_ALIASES "" \ + "flash_self=run mmc_boot\0" \ + "flash_self_test=setenv testargs test; " \ + "run mmc_boot\0" + +#define ENV_COMMON "" \ + "project_dir=targetdir/rootfs\0" \ + "serverip=192.168.251.2\0" \ + "ipaddr=192.168.251.1\0" \ + "dtb_name_nfs=default\0" \ + "dtb_name_default=default\0" \ + "kernel_name=Image\0" \ + "partitionset_active=A\0" \ + "dtb_loadaddr=0x83000000\0" \ + "kernel_loadaddr=0x80280000\0" \ + "ip_method=none\0" \ + "rootfs_name=/dev/mmcblk0\0" \ + "upgrade_available=0\0" \ + "bootlimit=3\0" \ + "altbootcmd=run bootcmd\0" \ + "optargs=\0" \ + +/**********************************************************************/ + +#define ENV_EMMC ENV_EMMC_FCT_EMMC_BOOT \ + ENV_EMMC_FCT_LOADFROM_EMMC \ + ENV_EMMC_FCT_SET_EMMC_BOOTARGS \ + ENV_EMMC_FCT_SET_ACTIVE_PARTITION \ + ENV_FCT_CHECK_UPGRADE \ + ENV_EMMC_ALIASES \ + ENV_FCT_TOGGLE_PARTITION + +#define ENV_NET ENV_NET_FCT_BOOT \ + ENV_NET_FCT_NETARGS \ + ENV_BOOTARGS_DEFAULT + -- 2.7.4

3 6

[GIT PULL] Pull request: u-boot-imx u-boot-imx-20200107
by Stefano Babic 07 Jan '20

07 Jan '20

Hi Tom, please pull for 2020.04, thanks ! The following changes since commit 0b0c6af38738f2c132cfd41a240889acaa031c8f: Prepare v2020.01 (2020-01-06 15:56:31 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20200107 for you to fetch changes up to b6e7ef4bf71bc0927dea35fdec0a653a82ae57a7: ARM: mxs: spl_boot.c: make early_delay more robust (2020-01-07 10:26:57 +0100) ---------------------------------------------------------------- New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664 ---------------------------------------------------------------- Baruch Siach (4): dt-bindings: add imx-audmux macro definitions arm: dts: hummingboard: add cubox/hummingboard DT (part 1 of 2) arm: dts: hummingboard: add cubox/hummingboard DT (part 2 of 2) mx6cuboxi: enable OF_CONTROL with DM_MMC and DM_USB Claudius Heine (2): ARM: dts: dh-imx6: add u-boot specific wdt-reboot node ARM: imx6: DHCOM i.MX6 PDK: Enable sysreset driver and wdt command Denis Zalevskiy (2): configs: ppd: DM for USB and regulators PPD board: ge: bx50v3: Enable DM for PCI and ethernet Fabio Estevam (5): mx7ulp: Add support for Embedded Artists COM board mx7dsabresd: Fix the pmic_get() parameter in the DM case mx6sllevk: Fix the pmic_get() parameter in the DM case mx6slevk: Fix the pmic_get() parameter in the DM case imx8mm_evk: Adjust the environment for booting a mainline kernel Frieder Schrempf (2): tools: imx8m_image: Change source path for DDR firmware to build dir ddr: imx8m: Return error values from LPDDR4 training Heiko Schocher (29): imx6: remove aristainetos board video: lg4573: convert to DM imx6: aristainetos: move defines to Kconfig imx6: aristainetos: remove 2b version imx6: aristainetos: disable gigabit support imx6: aristainetos: add device tree from linux imx6: aristainetos: add thumb build imx6: aristainetos: remove aristainetos-v2.c imx6: aristainetos: prepare dts for other board versions imx6: aristainetos: add DM_SERIAL support imx6: aristainetos: convert to DM_MMC imx6: aristainetos: convert gpio pins to DM and DTS imx6: aristainetos: convert to DM_USB imx6: aristainetos: convert CONFIG_DM_SPI imx6: aristainetos: enable DM_ETH imx6: aristainetos: add DM_VIDEO support imx6: aristainetos: add DM_I2C support imx6: aristainetos: convert to DM_PWM/DM_BACKLIGHT imx6: aristainetos: get rid of CONFIG_BOARDNAME imx6: aristainetos: add i2c eeprom support imx6: aristainetos: add AUTOBOOT_KEYED imx6: aristainetos: add version variable imx6: aristainetos: cleanup bootmode settings imx6: aristainetos: WDT DM conversion enable WDT reset imx6: aristainetos: cleanup default Environment imx6: aristainetos: enable HAB boot imx6: aristainetos: readd aristainetos 2b board imx6: aristainetos: add aristainetos 2b csl imx6: aristainetos: add support for rev C board Ian Ray (4): configs: bx50v3: Fix boot hang with video board: ge: bx50v3: Fix run-time warning board: ge: bx50v3: Fix message output to video console board: ge: pass rtc_status via device tree Igor Opaniuk (17): mach-imx: bootaux: print stack pointer and reset vector mach-imx: bootaux: add dcache flushing before enabling M4 colibri_imx7: add update_uboot wrapper apalis_imx6: add update_uboot wrapper colibri_imx6: add update_uboot wrapper colibri-imx6ull: add update_uboot wrapper colibri_vf: add update_uboot wrapper MAINTAINERS: change apalis_imx6/colibri_imx6 maintainers MAINTAINERS: change colibri_imx6/imx6ull/t30/vf maintainers ARM: dts: imx6_colibri: introduce fec node colibri_imx6: migrate to DM_ETH ARM: dts: imx6_apalis: introduce fec node apalis_imx6: migrate to DM_ETH ARM: dts: imx7: imx7_colibri: introduce fec node colibri_imx7: migrate to DM_ETH mach-imx: bootaux: elf firmware support mach-imx: nandbcb: improve cmd help Jagan Teki (2): ARM: dts: icorem6: Sync engicam device trees from v5.4 ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL Joris Offouga (3): mx7dsabre: Enable DM_ETH mx7dsabre: Convert to distroboot support mx7dsabre: Remove warning about DM_SPI_FLASH Lukasz Majewski (1): imx: Add support for i.MX28 based XEA board Marek Vasut (5): ARM: mx6: ddr: Make debug prints work with tiny printf ARM: mx6: ddr: Factor out SDQS configuration code ARM: mx6: ddr: Configure all SDQS pullups using loop ARM: mx6: ddr: Add support for iMX6SX pci: imx: Add iMX6SX compatible Michael Trimarchi (4): board: engicam: Cleanup fdt file and board mapping board: engicam: Fix the ethernet clock initialization configs: imx6-engicam: Drop fec phy address and mode ARM: dts: imx6qdl-icore-1.5: Remove duplicate phy reset methods Parthiban Nallathambi (1): imx: sync with kernel device tree for Phycore SoM Rasmus Villemoes (4): arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspX arm: mxs: fix comments in arch_cpu_init to match the code arm: mxs: be more careful when enabling gpmi_clk ARM: mxs: spl_boot.c: make early_delay more robust Robert Beckett (4): board: ge: bx50v3: sync devicetrees from Linux board: ge: ppd: sync device tree from Linux board: ge: bx50v3: use imx wdt board: ge: mx53ppd: use imx wdt Steffen Dirkwinkel (4): imx: cx9020: migrate cx9020 to CONFIG_DM_ETH imx: cx9020: migrate cx9020 to CONFIG_DM_USB imx: cx9020: enable vidconsole by default imx: cx9020: use distro boot Suniel Mahesh (3): board: cm_fx6: Enable DM support for video, fix build error board: cm_fx6: Enable CONFIG_DM_ETH arm: imx6: cm_fx6: Enable DM SPI and SPI_FLASH, fix SPL build errors Tom Rini (1): arm: imx: Default to SYS_THUMB_BUILD for i.MX6/7 arch/arm/Kconfig | 4 +- arch/arm/cpu/arm926ejs/mxs/mxs.c | 9 +- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 7 +- arch/arm/dts/Makefile | 43 ++++- arch/arm/dts/imx28-xea-u-boot.dtsi | 46 +++++ arch/arm/dts/imx28-xea.dts | 110 +++++++++++ arch/arm/dts/imx53-cx9020.dts | 42 +++-- arch/arm/dts/imx53-ppd-uboot.dtsi | 12 ++ arch/arm/dts/imx53-ppd.dts | 1081 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- arch/arm/dts/imx6-apalis.dts | 22 +++ arch/arm/dts/imx6-colibri.dts | 20 ++ arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi | 13 ++ arch/arm/dts/imx6dl-aristainetos2_4.dts | 51 ++++++ arch/arm/dts/imx6dl-aristainetos2_4.dtsi | 84 +++++++++ arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2_7.dts | 16 ++ arch/arm/dts/imx6dl-aristainetos2_7.dtsi | 58 ++++++ arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi | 13 ++ arch/arm/dts/imx6dl-aristainetos2b_4.dts | 50 +++++ arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2b_7.dts | 16 ++ arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi | 13 ++ arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts | 50 +++++ arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts | 16 ++ arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi | 13 ++ arch/arm/dts/imx6dl-aristainetos2c_4.dts | 50 +++++ arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2c_7.dts | 16 ++ arch/arm/dts/imx6dl-cubox-i-emmc-som-v15.dts | 52 ++++++ arch/arm/dts/imx6dl-cubox-i-som-v15.dts | 51 ++++++ arch/arm/dts/imx6dl-cubox-i.dts | 51 ++++++ arch/arm/dts/imx6dl-hummingboard-emmc-som-v15.dts | 53 ++++++ arch/arm/dts/imx6dl-hummingboard-som-v15.dts | 52 ++++++ arch/arm/dts/imx6dl-hummingboard.dts | 52 ++++++ arch/arm/dts/imx6dl-hummingboard2-emmc-som-v15-u-boot.dtsi | 1 + arch/arm/dts/imx6dl-hummingboard2-emmc-som-v15.dts | 55 ++++++ arch/arm/dts/imx6dl-hummingboard2-som-v15.dts | 54 ++++++ arch/arm/dts/imx6dl-hummingboard2.dts | 53 ++++++ arch/arm/dts/imx6dl-icore-mipi.dts | 13 +- arch/arm/dts/imx6dl-icore-rqs.dts | 43 +---- arch/arm/dts/imx6dl-icore.dts | 47 +---- arch/arm/dts/imx6q-b450v3.dts | 160 ++++++++++++++++ arch/arm/dts/imx6q-b650v3.dts | 159 ++++++++++++++++ arch/arm/dts/imx6q-b850v3.dts | 302 ++++++++++++++++++++++++++++++ arch/arm/dts/imx6q-ba16.dtsi | 640 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6q-bx50v3-uboot.dtsi | 12 ++ arch/arm/dts/imx6q-bx50v3.dts | 78 +------- arch/arm/dts/imx6q-bx50v3.dtsi | 381 ++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6q-cubox-i-emmc-som-v15.dts | 60 ++++++ arch/arm/dts/imx6q-cubox-i-som-v15.dts | 59 ++++++ arch/arm/dts/imx6q-cubox-i.dts | 59 ++++++ arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi | 11 ++ arch/arm/dts/imx6q-hummingboard-emmc-som-v15.dts | 61 +++++++ arch/arm/dts/imx6q-hummingboard-som-v15.dts | 60 ++++++ arch/arm/dts/imx6q-hummingboard.dts | 60 ++++++ arch/arm/dts/imx6q-hummingboard2-emmc-som-v15-u-boot.dtsi | 1 + arch/arm/dts/imx6q-hummingboard2-emmc-som-v15.dts | 63 +++++++ arch/arm/dts/imx6q-hummingboard2-som-v15.dts | 62 +++++++ arch/arm/dts/imx6q-hummingboard2.dts | 61 +++++++ arch/arm/dts/imx6q-icore-mipi.dts | 19 +- arch/arm/dts/imx6q-icore-ofcap10.dts | 40 ++++ arch/arm/dts/imx6q-icore-ofcap12.dts | 43 +++++ arch/arm/dts/imx6q-icore-rqs.dts | 43 +---- arch/arm/dts/imx6q-icore.dts | 72 ++++---- arch/arm/dts/imx6qdl-aristainetos2-common.dtsi | 492 +++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi | 101 ++++++++++ arch/arm/dts/imx6qdl-aristainetos2.dtsi | 244 +++++++++++++++++++++++++ arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi | 77 ++++++++ arch/arm/dts/imx6qdl-aristainetos2b.dtsi | 266 +++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi | 77 ++++++++ arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi | 248 +++++++++++++++++++++++++ arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi | 77 ++++++++ arch/arm/dts/imx6qdl-aristainetos2c.dtsi | 228 +++++++++++++++++++++++ arch/arm/dts/imx6qdl-cubox-i.dtsi | 269 +++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-hummingboard.dtsi | 368 +++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi | 36 ++++ arch/arm/dts/imx6qdl-hummingboard2-emmc.dtsi | 72 ++++++++ arch/arm/dts/imx6qdl-hummingboard2.dtsi | 577 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6qdl-icore-1.5.dtsi | 32 ++++ arch/arm/dts/imx6qdl-icore-rqs.dtsi | 326 ++++++++++++++++++++++++++++----- arch/arm/dts/imx6qdl-icore.dtsi | 255 +++++++++++++++++++++----- arch/arm/dts/imx6qdl-sr-som-brcm.dtsi | 144 +++++++++++++++ arch/arm/dts/imx6qdl-sr-som-emmc.dtsi | 70 +++++++ arch/arm/dts/imx6qdl-sr-som-ti.dtsi | 170 +++++++++++++++++ arch/arm/dts/imx6qdl-sr-som.dtsi | 121 ++++++++++++ arch/arm/dts/imx6ul-phycore-segin.dts | 81 --------- arch/arm/dts/{pcl063-common.dtsi => imx6ul-phytec-phycore-som.dtsi} | 130 +++++-------- arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 93 ++++++++++ arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi | 57 ++++++ arch/arm/dts/imx6ul-phytec-segin.dtsi | 346 +++++++++++++++++++++++++++++++++++ arch/arm/dts/imx6ull-phycore-segin.dts | 70 ------- arch/arm/dts/imx6ull-phytec-phycore-som.dtsi | 24 +++ arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 93 ++++++++++ arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi | 19 ++ arch/arm/dts/imx6ull-phytec-segin.dtsi | 38 ++++ arch/arm/dts/imx7-colibri.dtsi | 116 ++++++++++++ arch/arm/dts/imx7d-sdb-u-boot.dtsi | 3 + arch/arm/dts/imx7d-sdb.dts | 785 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------------- arch/arm/dts/imx7d.dtsi | 3 + arch/arm/dts/imx7s.dtsi | 1 + arch/arm/dts/imx7ulp-com.dts | 90 +++++++++ arch/arm/include/asm/arch-imx8m/ddr.h | 6 +- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h | 6 +- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h | 15 +- arch/arm/include/asm/mach-imx/sys_proto.h | 7 + arch/arm/mach-imx/cmd_nandbcb.c | 9 +- arch/arm/mach-imx/imx_bootaux.c | 103 ++++++++++- arch/arm/mach-imx/mx6/Kconfig | 39 +++- arch/arm/mach-imx/mx6/ddr.c | 69 ++++--- arch/arm/mach-imx/mx7/soc.c | 28 +++ arch/arm/mach-imx/mx7ulp/Kconfig | 6 + arch/arm/mach-imx/mxs/Kconfig | 4 + board/aristainetos/Kconfig | 34 +++- board/aristainetos/MAINTAINERS | 31 +++- board/aristainetos/aristainetos-v1.c | 278 ---------------------------- board/aristainetos/aristainetos-v2.c | 687 --------------------------------------------------------------------- board/aristainetos/aristainetos.c | 592 +++++++++++++++++++++++++++++++++++++++++++++-------------- board/aristainetos/aristainetos.cfg | 32 ---- board/aristainetos/aristainetos2.cfg | 3 + board/aristainetos/clocks.cfg | 23 --- board/aristainetos/common/Kconfig | 35 ++++ board/aristainetos/ddr-setup.cfg | 60 ------ board/aristainetos/mt41j128M.cfg | 69 ------- board/beckhoff/mx53cx9020/mx53cx9020.c | 10 - board/compulab/cm_fx6/cm_fx6.c | 5 + board/ea/mx7ulp_com/Kconfig | 12 ++ board/ea/mx7ulp_com/MAINTAINERS | 6 + board/ea/mx7ulp_com/Makefile | 6 + board/ea/mx7ulp_com/imximage.cfg | 137 ++++++++++++++ board/ea/mx7ulp_com/mx7ulp_com.c | 48 +++++ board/engicam/common/board.c | 96 ++++++++-- board/freescale/imx8mm_evk/README | 6 +- board/freescale/imx8mq_evk/README | 6 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sllevk/mx6sllevk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 64 +------ board/ge/bx50v3/bx50v3.c | 160 ++++++++-------- board/ge/common/ge_common.c | 20 +- board/ge/mx53ppd/mx53ppd.c | 8 +- board/liebherr/xea/Kconfig | 24 +++ board/liebherr/xea/MAINTAINERS | 6 + board/liebherr/xea/Makefile | 12 ++ board/liebherr/xea/README | 63 +++++++ board/liebherr/xea/spl_xea.c | 303 ++++++++++++++++++++++++++++++ board/liebherr/xea/xea.c | 153 ++++++++++++++++ board/phytec/pcl063/MAINTAINERS | 12 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 119 +++++++----- board/toradex/apalis_imx6/MAINTAINERS | 2 +- board/toradex/apalis_imx6/apalis_imx6.c | 51 ------ board/toradex/colibri-imx6ull/MAINTAINERS | 2 +- board/toradex/colibri_imx6/MAINTAINERS | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 59 +----- board/toradex/colibri_imx7/MAINTAINERS | 2 +- board/toradex/colibri_imx7/colibri_imx7.c | 44 ----- board/toradex/colibri_t30/MAINTAINERS | 2 +- board/toradex/colibri_vf/MAINTAINERS | 2 +- configs/apalis_imx6_defconfig | 3 + configs/aristainetos2_defconfig | 63 ++++++- configs/aristainetos2b_defconfig | 67 ++++++- configs/aristainetos2bcsl_defconfig | 115 ++++++++++++ configs/aristainetos2c_defconfig | 115 ++++++++++++ configs/aristainetos_defconfig | 69 ------- configs/cm_fx6_defconfig | 4 + configs/colibri_imx6_defconfig | 3 + configs/colibri_imx7_defconfig | 3 + configs/colibri_imx7_emmc_defconfig | 3 + configs/dh_imx6_defconfig | 3 + configs/ge_bx50v3_defconfig | 18 ++ configs/imx28_xea_defconfig | 108 +++++++++++ configs/imx8mm_evk_defconfig | 1 - configs/mx53cx9020_defconfig | 10 + configs/mx53ppd_defconfig | 5 + configs/mx6cuboxi_defconfig | 16 +- configs/mx7dsabresd_defconfig | 22 +-- configs/mx7dsabresd_qspi_defconfig | 20 +- configs/mx7ulp_com_defconfig | 60 ++++++ configs/phycore_pcl063_defconfig | 2 +- configs/phycore_pcl063_ull_defconfig | 2 +- drivers/ddr/imx/imx8m/ddr_init.c | 11 +- drivers/ddr/imx/imx8m/ddrphy_train.c | 9 +- drivers/ddr/imx/imx8m/ddrphy_utils.c | 8 +- drivers/pci/pcie_imx.c | 1 + drivers/video/lg4573.c | 175 ++++++++++++++---- include/configs/apalis_imx6.h | 18 +- include/configs/aristainetos-common.h | 195 -------------------- include/configs/aristainetos.h | 43 ----- include/configs/aristainetos2.h | 445 +++++++++++++++++++++++++++++++++++++++++++-- include/configs/aristainetos2b.h | 50 ----- include/configs/cm_fx6.h | 7 + include/configs/colibri-imx6ull.h | 7 + include/configs/colibri_imx6.h | 20 +- include/configs/colibri_imx7.h | 28 +-- include/configs/colibri_vf.h | 5 + include/configs/dh_imx6.h | 5 + include/configs/ge_bx50v3.h | 23 +-- include/configs/imx6-engicam.h | 11 -- include/configs/imx8mm_evk.h | 8 +- include/configs/mx53cx9020.h | 95 ++-------- include/configs/mx53ppd.h | 2 +- include/configs/mx6cuboxi.h | 6 +- include/configs/mx7dsabresd.h | 94 ++-------- include/configs/mx7ulp_com.h | 103 +++++++++++ include/configs/xea.h | 196 ++++++++++++++++++++ include/dt-bindings/sound/fsl-imx-audmux.h | 64 +++++++ scripts/config_whitelist.txt | 3 - tools/imx8m_image.sh | 28 ++- 207 files changed, 13920 insertions(+), 3247 deletions(-) create mode 100644 arch/arm/dts/imx28-xea-u-boot.dtsi create mode 100644 arch/arm/dts/imx28-xea.dts create mode 100644 arch/arm/dts/imx53-ppd-uboot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7.dts create mode 100644 arch/arm/dts/imx6dl-cubox-i-emmc-som-v15.dts create mode 100644 arch/arm/dts/imx6dl-cubox-i-som-v15.dts create mode 100644 arch/arm/dts/imx6dl-cubox-i.dts create mode 100644 arch/arm/dts/imx6dl-hummingboard-emmc-som-v15.dts create mode 100644 arch/arm/dts/imx6dl-hummingboard-som-v15.dts create mode 100644 arch/arm/dts/imx6dl-hummingboard.dts create mode 100644 arch/arm/dts/imx6dl-hummingboard2-emmc-som-v15-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-hummingboard2-emmc-som-v15.dts create mode 100644 arch/arm/dts/imx6dl-hummingboard2-som-v15.dts create mode 100644 arch/arm/dts/imx6dl-hummingboard2.dts create mode 100644 arch/arm/dts/imx6q-b450v3.dts create mode 100644 arch/arm/dts/imx6q-b650v3.dts create mode 100644 arch/arm/dts/imx6q-b850v3.dts create mode 100644 arch/arm/dts/imx6q-ba16.dtsi create mode 100644 arch/arm/dts/imx6q-bx50v3-uboot.dtsi create mode 100644 arch/arm/dts/imx6q-bx50v3.dtsi create mode 100644 arch/arm/dts/imx6q-cubox-i-emmc-som-v15.dts create mode 100644 arch/arm/dts/imx6q-cubox-i-som-v15.dts create mode 100644 arch/arm/dts/imx6q-cubox-i.dts create mode 100644 arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-hummingboard-emmc-som-v15.dts create mode 100644 arch/arm/dts/imx6q-hummingboard-som-v15.dts create mode 100644 arch/arm/dts/imx6q-hummingboard.dts create mode 100644 arch/arm/dts/imx6q-hummingboard2-emmc-som-v15-u-boot.dtsi create mode 100644 arch/arm/dts/imx6q-hummingboard2-emmc-som-v15.dts create mode 100644 arch/arm/dts/imx6q-hummingboard2-som-v15.dts create mode 100644 arch/arm/dts/imx6q-hummingboard2.dts create mode 100644 arch/arm/dts/imx6q-icore-ofcap10.dts create mode 100644 arch/arm/dts/imx6q-icore-ofcap12.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-common.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c.dtsi create mode 100644 arch/arm/dts/imx6qdl-cubox-i.dtsi create mode 100644 arch/arm/dts/imx6qdl-hummingboard.dtsi create mode 100644 arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-hummingboard2-emmc.dtsi create mode 100644 arch/arm/dts/imx6qdl-hummingboard2.dtsi create mode 100644 arch/arm/dts/imx6qdl-icore-1.5.dtsi create mode 100644 arch/arm/dts/imx6qdl-sr-som-brcm.dtsi create mode 100644 arch/arm/dts/imx6qdl-sr-som-emmc.dtsi create mode 100644 arch/arm/dts/imx6qdl-sr-som-ti.dtsi create mode 100644 arch/arm/dts/imx6qdl-sr-som.dtsi delete mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts rename arch/arm/dts/{pcl063-common.dtsi => imx6ul-phytec-phycore-som.dtsi} (56%) create mode 100644 arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts create mode 100644 arch/arm/dts/imx6ul-phytec-segin-peb-eval-01.dtsi create mode 100644 arch/arm/dts/imx6ul-phytec-segin.dtsi delete mode 100644 arch/arm/dts/imx6ull-phycore-segin.dts create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som.dtsi create mode 100644 arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts create mode 100644 arch/arm/dts/imx6ull-phytec-segin-peb-eval-01.dtsi create mode 100644 arch/arm/dts/imx6ull-phytec-segin.dtsi create mode 100644 arch/arm/dts/imx7d-sdb-u-boot.dtsi create mode 100644 arch/arm/dts/imx7ulp-com.dts delete mode 100644 board/aristainetos/aristainetos-v1.c delete mode 100644 board/aristainetos/aristainetos-v2.c delete mode 100644 board/aristainetos/aristainetos.cfg delete mode 100644 board/aristainetos/clocks.cfg create mode 100644 board/aristainetos/common/Kconfig delete mode 100644 board/aristainetos/ddr-setup.cfg delete mode 100644 board/aristainetos/mt41j128M.cfg create mode 100644 board/ea/mx7ulp_com/Kconfig create mode 100644 board/ea/mx7ulp_com/MAINTAINERS create mode 100644 board/ea/mx7ulp_com/Makefile create mode 100644 board/ea/mx7ulp_com/imximage.cfg create mode 100644 board/ea/mx7ulp_com/mx7ulp_com.c create mode 100644 board/liebherr/xea/Kconfig create mode 100644 board/liebherr/xea/MAINTAINERS create mode 100644 board/liebherr/xea/Makefile create mode 100644 board/liebherr/xea/README create mode 100644 board/liebherr/xea/spl_xea.c create mode 100644 board/liebherr/xea/xea.c create mode 100644 configs/aristainetos2bcsl_defconfig create mode 100644 configs/aristainetos2c_defconfig delete mode 100644 configs/aristainetos_defconfig create mode 100644 configs/imx28_xea_defconfig create mode 100644 configs/mx7ulp_com_defconfig delete mode 100644 include/configs/aristainetos-common.h delete mode 100644 include/configs/aristainetos.h delete mode 100644 include/configs/aristainetos2b.h create mode 100644 include/configs/mx7ulp_com.h create mode 100644 include/configs/xea.h create mode 100644 include/dt-bindings/sound/fsl-imx-audmux.h Best regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[PULL] u-boot-atmel-2020.04-a
by Eugen.Hristev＠microchip.com 07 Jan '20

07 Jan '20

Hi Tom, Please pull tag u-boot-atmel-2020.04-a , the first set of new features for the 2020.04 cycle. This feature set is a patch series from Tudor Ambarus which includes parsing of the spi flash SFDP parser for SST flashes, and using those tables to retrieve unique saved per device MAC address. This is then used as base mac address on the SAMA5D2 Wireless SOM EK board. Thanks ! Eugen The following changes since commit ef7c2af65966a57c98d3c47e6c2fe1ce2103b7f6: Prepare v2020.01-rc5 (2019-12-16 07:39:56 -0500) are available in the git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git tags/u-boot-atmel-2020.04-a for you to fetch changes up to 96b225b0c8359d6873bc09d651ab8d57a2be3aa5: configs: sama5d27_wlsom1_ek: mmc: Enable SPI NOR ethaddr retrieval (2019-12-17 09:49:05 +0200) ---------------------------------------------------------------- First set of u-boot-atmel features for 2020.04 cycle ---------------------------------------------------------------- Tudor Ambarus (4): mtd: spi: spi-nor-core: Add SST vendor specific SFDP parser board: atmel: sama5d27_wlsom1_ek: Set ethaddr from spi-nor flash configs: sama5d27_wlsom1_ek: qspiflash: Enable SPI NOR ethaddr retrieval configs: sama5d27_wlsom1_ek: mmc: Enable SPI NOR ethaddr retrieval arch/arm/mach-at91/include/mach/at91_common.h | 1 + board/atmel/common/Makefile | 1 + board/atmel/common/mac-spi-nor.c | 127 +++++++++++++++++++++ .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 3 + configs/sama5d27_wlsom1_ek_mmc_defconfig | 5 + configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 + drivers/mtd/spi/spi-nor-core.c | 46 +++++++- include/linux/mtd/spi-nor.h | 2 + 8 files changed, 184 insertions(+), 2 deletions(-) create mode 100644 board/atmel/common/mac-spi-nor.c

2 1

[PATCH 1/2] imx: add imx8x capricorn giedi board
by Anatolij Gustschin 07 Jan '20

07 Jan '20

Add support for i.MX8X based Capricorn Giedi SoM. Supported interfaces: GPIO, ENET, eMMC, I2C, UART. Console output: U-Boot SPL 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100) Trying to boot from MMC1 Load image from MMC/SD 0x3e400 U-Boot 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100) ##v01.07 CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 30C Model: Siemens Giedi Board: Capricorn Boot: MMC0 DRAM: 1022 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial@5a080000 Out: serial@5a080000 Err: serial@5a080000 Net: eth1: ethernet@5b050000 [PRIME] Autobooting in 1 seconds, press "<Esc><Esc>" to stop Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8-giedi.dts | 10 + arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi | 133 ++++++ arch/arm/dts/imx8qxp-capricorn.dtsi | 285 +++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 6 + board/siemens/capricorn/Kconfig | 12 + board/siemens/capricorn/MAINTAINERS | 9 + board/siemens/capricorn/Makefile | 12 + board/siemens/capricorn/board.c | 448 ++++++++++++++++++++ board/siemens/capricorn/imximage.cfg | 22 + board/siemens/capricorn/spl.c | 47 ++ board/siemens/capricorn/uboot-container.cfg | 13 + board/siemens/common/factoryset.c | 2 + configs/giedi_defconfig | 103 +++++ include/configs/capricorn-common.h | 185 ++++++++ include/configs/giedi.h | 19 + include/configs/siemens-ccp-common.h | 19 + include/configs/siemens-env-common.h | 201 +++++++++ 18 files changed, 1528 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8-giedi.dts create mode 100644 arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi create mode 100644 arch/arm/dts/imx8qxp-capricorn.dtsi create mode 100644 board/siemens/capricorn/Kconfig create mode 100644 board/siemens/capricorn/MAINTAINERS create mode 100644 board/siemens/capricorn/Makefile create mode 100644 board/siemens/capricorn/board.c create mode 100644 board/siemens/capricorn/imximage.cfg create mode 100644 board/siemens/capricorn/spl.c create mode 100644 board/siemens/capricorn/uboot-container.cfg create mode 100644 configs/giedi_defconfig create mode 100644 include/configs/capricorn-common.h create mode 100644 include/configs/giedi.h create mode 100644 include/configs/siemens-ccp-common.h create mode 100644 include/configs/siemens-env-common.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0127a91a82..c0298e5462 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -667,7 +667,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ - fsl-imx8qxp-mek.dtb + fsl-imx8qxp-mek.dtb \ + imx8-giedi.dtb dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ diff --git a/arch/arm/dts/imx8-giedi.dts b/arch/arm/dts/imx8-giedi.dts new file mode 100644 index 0000000000..0dbfef2ee9 --- /dev/null +++ b/arch/arm/dts/imx8-giedi.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +#include "imx8qxp-capricorn.dtsi" + +/ { + model = "Siemens Giedi"; +}; diff --git a/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi new file mode 100644 index 0000000000..1cf58fc3f9 --- /dev/null +++ b/arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Siemens AG + */ + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio6 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio7 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_dma_lpuart2 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&lpuart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8qxp-capricorn.dtsi b/arch/arm/dts/imx8qxp-capricorn.dtsi new file mode 100644 index 0000000000..db5653ea1f --- /dev/null +++ b/arch/arm/dts/imx8qxp-capricorn.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + * + * Copyright 2019 Siemens AG + * + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" +#include "imx8qxp-capricorn-u-boot.dtsi" + +/ { + model = "Siemens Giedi"; + compatible = "siemens,capricorn", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; + stdout-path = &lpuart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + run { + label = "run"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + flt { + label = "flt"; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + svc { + label = "svc"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_tx { + label = "com1-tx"; + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com1_rx { + label = "com1-rx"; + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_tx { + label = "com2-tx"; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + com2_rx { + label = "com2-rx"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + cloud { + label = "cloud"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + wlan { + label = "wlan"; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg1 { + label = "dbg1"; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg2 { + label = "dbg2"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg3 { + label = "dbg3"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + dbg4 { + label = "dbg4"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + muxcgrp: imx8qxp-som { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021 + SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021 + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021 + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020 + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021 + //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060 + + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */ + >; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + clock-frequency=<52000000>; + no-1-8-v; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&fec1 { + status ="disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rmii"; + + phy-handle = <&ethphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index cdb78afacf..bb45c8e3e6 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -55,6 +55,11 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP +config TARGET_GIEDI + bool "Support i.MX8QXP Capricorn Giedi board" + select BOARD_LATE_INIT + select IMX8QXP + config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" select BOARD_LATE_INIT @@ -78,5 +83,6 @@ source "board/freescale/imx8qxp_mek/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" +source "board/siemens/capricorn/Kconfig" endif diff --git a/board/siemens/capricorn/Kconfig b/board/siemens/capricorn/Kconfig new file mode 100644 index 0000000000..ed1f793e40 --- /dev/null +++ b/board/siemens/capricorn/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GIEDI + +config SYS_BOARD + default "capricorn" + +config SYS_VENDOR + default "siemens" + +config SYS_CONFIG_NAME + default "giedi" + +endif diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS new file mode 100644 index 0000000000..5d81aaf149 --- /dev/null +++ b/board/siemens/capricorn/MAINTAINERS @@ -0,0 +1,9 @@ +CAPRICORN BOARD +M: Anatolij Gustschin <agust(a)denx.de> +S: Maintained +F: board/siemens/capricorn/ +F: include/configs/capricorn-common.h +F: include/configs/giedi.h +F: include/configs/siemens-ccp-common.h +F: include/configs/siemens-env-common.h +F: configs/giedi_defconfig diff --git a/board/siemens/capricorn/Makefile b/board/siemens/capricorn/Makefile new file mode 100644 index 0000000000..d5846cc8e3 --- /dev/null +++ b/board/siemens/capricorn/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Siemens AG +# + +obj-y += board.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += ../common/factoryset.o +endif diff --git a/board/siemens/capricorn/board.c b/board/siemens/capricorn/board.c new file mode 100644 index 0000000000..00fd4b9658 --- /dev/null +++ b/board/siemens/capricorn/board.c @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + * + * Copyright 2019 Siemens AG + * + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <netdev.h> +#include <env_internal.h> +#include <fsl_esdhc_imx.h> +#include <i2c.h> +#include <led.h> +#include <pca953x.h> +#include <power-domain.h> +#include <asm/gpio.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/sys_proto.h> +#ifndef CONFIG_SPL +#include <asm/arch-imx8/clock.h> +#endif +#include "../common/factoryset.h" + +#define GPIO_PAD_CTRL \ + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL \ + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL \ + ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart2_pads[] = { + SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +int board_early_init_f(void) +{ + /* Set UART clock root to 80 MHz */ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + ret |= sc_pm_setup_uart(SC_R_UART_2, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#define ENET_PHY_RESET IMX_GPIO_NR(0, 3) +#define ENET_TEST_1 IMX_GPIO_NR(0, 8) +#define ENET_TEST_2 IMX_GPIO_NR(0, 9) + +/*#define ETH_IO_TEST*/ +static iomux_cfg_t enet_reset[] = { + SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +#ifdef ETH_IO_TEST + /* GPIO0.IO08 MODE3: TXD0 */ + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) | + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + /* GPIO0.IO09 MODE3: TXD1 */ + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) | + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +#endif +}; + +static void enet_device_phy_reset(void) +{ + int ret = 0; + + imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset)); + + ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset"); + if (!ret) { + gpio_direction_output(ENET_PHY_RESET, 1); + gpio_set_value(ENET_PHY_RESET, 0); + /* SMSC9303 TRM chapter 14.5.2 */ + udelay(200); + gpio_set_value(ENET_PHY_RESET, 1); + } else { + printf("ENET RESET failed!\n"); + } + +#ifdef ETH_IO_TEST + ret = gpio_request(ENET_TEST_1, "enet_test1"); + if (!ret) { + int i; + + printf("ENET TEST 1!\n"); + for (i = 0; i < 20; i++) { + gpio_direction_output(ENET_TEST_1, 1); + gpio_set_value(ENET_TEST_1, 0); + udelay(50); + gpio_set_value(ENET_TEST_1, 1); + udelay(50); + } + gpio_free(ENET_TEST_1); + } else { + printf("GPIO for ENET TEST 1 failed!\n"); + } + ret = gpio_request(ENET_TEST_2, "enet_test2"); + if (!ret) { + int i; + + printf("ENET TEST 2!\n"); + for (i = 0; i < 20; i++) { + gpio_direction_output(ENET_TEST_2, 1); + gpio_set_value(ENET_TEST_2, 0); + udelay(50); + gpio_set_value(ENET_TEST_2, 1); + udelay(50); + } + gpio_free(ENET_TEST_2); + } else { + printf("GPIO for ENET TEST 2 failed!\n"); + } +#endif +} + +int setup_gpr_fec(void) +{ + sc_ipc_t ipc_handle = -1; + sc_err_t err = 0; + unsigned int test; + + /* + * TX_CLK_SEL: it controls a mux between clock coming from the pad 50M + * input pin and clock generated internally to connectivity subsystem + * 0: internal clock + * 1: external clock ---> your choice for RMII + * + * CLKDIV_SEL: it controls a div by 2 on the internal clock path à + * it should be don’t care when using external clock + * 0: non-divided clock + * 1: clock divided by 2 + * 50_DISABLE or 125_DISABLE: + * it’s used to disable the clock tree going outside the chip + * when reference clock is generated internally. + * It should be don’t care when reference clock is provided + * externally. + * 0: clock is enabled + * 1: clock is disabled + * + * SC_C_TXCLK = 24, + * SC_C_CLKDIV = 25, + * SC_C_DISABLE_50 = 26, + * SC_C_DISABLE_125 = 27, + */ + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test); + + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1); + if (err != SC_ERR_NONE) + printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125); + + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test); + debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#endif + +static int setup_fec(void) +{ + setup_gpr_fec(); + /* Reset ENET PHY */ + enet_device_phy_reset(); + return 0; +} + +void reset_cpu(ulong addr) +{ +} + +#ifndef CONFIG_SPL_BUILD +/* LED's */ +static int board_led_init(void) +{ + struct udevice *bus, *dev; + u8 pca_led[2] = { 0x00, 0x00 }; + int ret; + + /* init all GPIO LED's */ + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + /* enable all leds on PCA9552 */ + ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus); + if (ret) { + printf("ERROR: I2C get %d\n", ret); + return ret; + } + + ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev); + if (ret) { + printf("ERROR: PCA9552 probe failed\n"); + return ret; + } + + ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led)); + if (ret) { + printf("ERROR: PCA9552 write failed\n"); + return ret; + } + + mdelay(1); + return ret; +} +#endif /* !CONFIG_SPL_BUILD */ + +int checkboard(void) +{ + puts("Board: Capricorn\n"); + + /* + * Running build_info() doesn't work with current SCFW blob. + * Uncomment below call when new blob is available. + */ + /*build_info();*/ + + print_bootinfo(); + return 0; +} + +int board_init(void) +{ + setup_fec(); + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if (autodetect_str && (strcmp(autodetect_str, "yes") == 0)) + return 1; + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +#ifndef CONFIG_SPL_BUILD +int factoryset_read_eeprom(int i2c_addr); + +static int load_parameters_from_factoryset(void) +{ + int ret; + + ret = factoryset_read_eeprom(EEPROM_I2C_ADDR); + if (ret) + return ret; + + return factoryset_env_set(); +} + +int board_late_init(void) +{ + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + /* Init LEDs */ + if (board_led_init()) + printf("I2C LED init failed\n"); + + /* Set environment from factoryset */ + if (load_parameters_from_factoryset()) + printf("Loading factoryset parameters failed!\n"); + + return 0; +} + +/* Service button */ +#define MAX_PIN_NUMBER 128 +#define BOARD_DEFAULT_BUTTON_GPIO IMX_GPIO_NR(1, 31) + +unsigned char get_button_state(char * const envname, unsigned char def) +{ + int button = 0; + int gpio; + char *ptr_env; + + /* If button is not found we take default */ + ptr_env = env_get(envname); + if (!ptr_env) { + printf("Using default: %u\n", def); + gpio = def; + } else { + gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0); + if (gpio > MAX_PIN_NUMBER) + gpio = def; + } + + gpio_request(gpio, ""); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + + return button; +} + +/* + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int button = 0; + + button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO); + + if (argc > 1) + printf("Button state: %u\n", button); + + return button; +} + +U_BOOT_CMD( + usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton, + "Return the status of user button", + "[print]" +); + +#define ERST IMX_GPIO_NR(0, 3) + +static int +do_eth_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + gpio_request(ERST, "ERST"); + gpio_direction_output(ERST, 0); + udelay(200); + gpio_set_value(ERST, 1); + return 0; +} + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset, + "Reset eth phy", + "[print]" +); +#endif /* ! CONFIG_SPL_BUILD */ diff --git a/board/siemens/capricorn/imximage.cfg b/board/siemens/capricorn/imximage.cfg new file mode 100644 index 0000000000..8660e50cbd --- /dev/null +++ b/board/siemens/capricorn/imximage.cfg @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU capricorn-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/siemens/capricorn/spl.c b/board/siemens/capricorn/spl.c new file mode 100644 index 0000000000..47fe86ccc0 --- /dev/null +++ b/board/siemens/capricorn/spl.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Copyright 2019 Siemens AG + * + */ +#include <common.h> +#include <spl.h> +#include <dm.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/siemens/capricorn/uboot-container.cfg b/board/siemens/capricorn/uboot-container.cfg new file mode 100644 index 0000000000..8165811818 --- /dev/null +++ b/board/siemens/capricorn/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QX +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c index 7715ddf307..0d3701c03c 100644 --- a/board/siemens/common/factoryset.c +++ b/board/siemens/common/factoryset.c @@ -13,7 +13,9 @@ #include <env_internal.h> #include <i2c.h> #include <asm/io.h> +#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB) #include <asm/arch/cpu.h> +#endif #include <asm/arch/sys_proto.h> #include <asm/unaligned.h> #include <net.h> diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig new file mode 100644 index 0000000000..6b54cc8af4 --- /dev/null +++ b/configs/giedi_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg" +CONFIG_TARGET_GIEDI=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0x2000 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MV88E61XX_SWITCH=y +CONFIG_MV88E61XX_CPU_PORT=5 +CONFIG_MV88E61XX_PHY_PORTS=0x7 +CONFIG_MV88E61XX_FIXED_PORTS=0x0 +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B050000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_SPL_WDT is not set +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h new file mode 100644 index 0000000000..254b3a5a76 --- /dev/null +++ b/include/configs/capricorn-common.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * Copyright 2019 Siemens AG + */ + +#ifndef __IMX8X_CAPRICORN_H +#define __IMX8X_CAPRICORN_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#include "siemens-env-common.h" +#include "siemens-ccp-common.h" + +/* SPL config */ +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_FACTORYSET + +#undef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07") + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Commands */ +#define CONFIG_CMD_READ + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +#define CONFIG_FEC_XCV_TYPE RMII +#define FEC_QUIRK_ENET_MAC + +/* ENET1 connects to base board and MUX with ESAI */ +#define CONFIG_FEC_ENET_DEV 1 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth1" + +/* I2C Configuration */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_I2C_SPEED 400000 +/* EEPROM */ +#define EEPROM_I2C_BUS 0 /* I2C0 */ +#define EEPROM_I2C_ADDR 0x50 +/* PCA9552 */ +#define PCA9552_1_I2C_BUS 1 /* I2C1 */ +#define PCA9552_1_I2C_ADDR 0x60 +#endif /* !CONFIG_SPL_BUILD */ + +/* AHAB */ +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#define MFG_ENV_SETTINGS_DEFAULT \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "clk_ignore_unused "\ + "\0" \ + "kboot=booti\0"\ + "bootcmd_mfg=run mfgtool_args;" \ + "if iminfo ${initrd_addr}; then " \ + "if test ${tee} = yes; then " \ + "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \ + "else " \ + "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \ + "fi; " \ + "else " \ + "echo \"Run fastboot ...\"; fastboot 0; " \ + "fi;\0" + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \ + "${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define CONFIG_MFG_ENV_SETTINGS \ + MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + AHAB_ENV \ + ENV_COMMON \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP2\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x88000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "netdev=eth0\0" \ + "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \ + "hostname=capricorn\0" \ + ENV_EMMC \ + ENV_NET + +#define CONFIG_BOOTCOMMAND \ + "if usrbutton; then " \ + "run flash_self_test; " \ + "reset; " \ + "fi;" \ + "run flash_self;" \ + "reset;" + +/* Default location for tftp and bootm */ +#define CONFIG_LOADADDR 0x80280000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_ENV + +/* Environment organisation */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1, eMMC */ +#define CONFIG_SYS_MMC_ENV_PART 2 /* 2nd boot partition */ + +/* On CCP board, USDHC1 is for eMMC */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +/* DDR3 board total DDR is 1 GB */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Console buffer and boot args */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 +#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ + +#endif /* __IMX8X_CAPRICORN_H */ diff --git a/include/configs/giedi.h b/include/configs/giedi.h new file mode 100644 index 0000000000..dabb1fb171 --- /dev/null +++ b/include/configs/giedi.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Siemens AG + * + */ + +#ifndef __GIEDI_H +#define __GIEDI_H + +#include "capricorn-common.h" + +#undef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07") + +/* DDR3 board total DDR is 1 GB */ +#undef PHYS_SDRAM_1_SIZE +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ + +#endif /* __GIEDI_H */ diff --git a/include/configs/siemens-ccp-common.h b/include/configs/siemens-ccp-common.h new file mode 100644 index 0000000000..01051c8ad7 --- /dev/null +++ b/include/configs/siemens-ccp-common.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Be very careful updating CONFIG_IDENT_STRING + * This string will control the update flow whether an U-Boot should be + * updated or not. If the version of installed U-Boot (in flash) is smaller + * than the version to be installed (from update file), an update will + * be performed. + * + * General rules: + * 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number + * to identify the following strings after easily. Don't change them! + * + * 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version + * change, e.g. from 2015.04 to 2018.03 + * + * 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade + * U-Boot within an U-Boot version. + */ +#define CCP_IDENT_MAGIC " ##v" +#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h new file mode 100644 index 0000000000..36fa5d936f --- /dev/null +++ b/include/configs/siemens-env-common.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* Common env settings */ + +/** set_bootargs() + * input: + * console: string, tty, etc. + * baudrate: string, tty baudrate + * testargs: string + * optargs: string + * output: + * bootargs: string, default boot string + */ +#define ENV_BOOTARGS_DEFAULT "set_bootargs=" \ + "setenv bootargs " \ + "console=${console} " \ + "${testargs} " \ + "${optargs}\0" + +/** set_bootargs_net() + * input: + * kernel_name: + * dtb_name: + * project_dir: + * output: + */ +#define ENV_NET_FCT_NETARGS "set_bootargs_net=" \ + "run set_bootargs;" \ + "setenv bootfile ${project_dir}/boot/${kernel_name};" \ + "setenv bootdtb ${project_dir}/boot/${dtb_name_nfs}.dtb;" \ + "setenv rootpath /home/projects/${project_dir}/;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" + +/** net_nfs() + * input: + * output: + */ +#define ENV_NET_FCT_BOOT "net_nfs=" \ + "echo Booting from network ...; " \ + "run set_bootargs_net; " \ + "tftpboot ${dtb_loadaddr} ${serverip}:${bootdtb};" \ + "if test $? -eq 1;" \ + "then " \ + "echo Loading default.dtb!;" \ + "tftpboot ${dtb_loadaddr} ${serverip}:${project_dir}/boot/${dtb_name_default}.dtb;" \ + "fi;" \ + "tftpboot ${kernel_loadaddr} ${serverip}:${bootfile};" \ + "printenv bootargs;" \ + "booti ${kernel_loadaddr} - ${dtb_loadaddr}\0" + +/** check_update() + * input: + * upgrade_available: [0|1], if set to 1 check bootcount variables + * bootcount: int, bootcount + * bootlimit: int, limit cootcount + * toggle_partition(): - toggles active partition set + * output: + * upgrade_available: [0|1], set to 0 if bootcount > bootlimit + */ +#define ENV_FCT_CHECK_UPGRADE "check_upgrade="\ + "if test ${upgrade_available} -eq 1; " \ + "then " \ + "echo upgrade_available is set; " \ + "if test ${bootcount} -gt ${bootlimit}; " \ + "then " \ + "setenv upgrade_available 0;" \ + "echo toggle partition;" \ + "run toggle_partition;" \ + "fi;" \ + "fi;\0" + +/** toggle_partition() + * input: + * partitionset_active: [A|B], selected partition set + * output: + * partitionset_active: [A|B], toggle + */ +#define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; " \ + "then " \ + "setenv partitionset_active B; " \ + "env delete A; " \ + "fi;" \ + "if test -n ${B}; "\ + "then " \ + "setenv partitionset_active A; " \ + "env delete B; " \ + "fi;" \ + "saveenv\0" + +/** set_partition() + * input: + * partitionset_active: [A|B], selected partition set + * rootfs_name: string, mmc device file in kernel, e.g. /dev/mmcblk0 + * output: + * mmc_active_vol: string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2 + * mmc_part_nr: int, partition number of mmc, e.g. /dev/mmcblk0p2 --> 2 + */ +#define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \ + "setenv ${partitionset_active} true;" \ + "if test -n ${A}; " \ + "then " \ + "setenv mmc_part_nr 1;" \ + "fi;" \ + "if test -n ${B}; " \ + "then " \ + "setenv mmc_part_nr 2;" \ + "fi;" \ + "setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} \0" + +/** set_bootargs_mmc() + * input: + * bootargs: string, default bootargs + * mmc_active_vol string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2 + * ip_method: string, [none|?] + * output: + * bootargs: string + */ +#define ENV_EMMC_FCT_SET_EMMC_BOOTARGS "set_bootargs_mmc=" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_active_vol} rw " \ + "rootdelay=1 rootwait " \ + "rootfstype=ext4 " \ + "ip=${ip_method} \0" + +/** mmc_load_bootfiles() + * input: + * mmc_part_nr: + * dtb_loadaddr: + * dtb_name: + * kernel_loadaddr: + * kernel_name: + */ +#define ENV_EMMC_FCT_LOADFROM_EMMC "mmc_load_bootfiles=" \ + "echo Loading from eMMC ...;" \ + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name}.dtb;" \ + "if test $? -eq 1;" \ + "then " \ + "echo Loading default.dtb!;" \ + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name_default}.dtb;" \ + "fi;" \ + "ext4load mmc 0:${mmc_part_nr} ${kernel_loadaddr} boot/${kernel_name};" \ + "printenv bootargs;\0" + +/** mmc_boot() + * input: + * mmc_part_nr: + * dtb_loadaddr: + * dtb_name: + * kernel_loadaddr: + * kernel_name: + */ +#define ENV_EMMC_FCT_EMMC_BOOT "mmc_boot=" \ + "run set_bootargs;" \ + "run check_upgrade; " \ + "run set_partition;" \ + "run set_bootargs_mmc;" \ + "run mmc_load_bootfiles;" \ + "echo Booting from eMMC ...; " \ + "booti ${kernel_loadaddr} - ${dtb_loadaddr} \0" + +#define ENV_EMMC_ALIASES "" \ + "flash_self=run mmc_boot\0" \ + "flash_self_test=setenv testargs test; " \ + "run mmc_boot\0" + +#define ENV_COMMON "" \ + "project_dir=targetdir/rootfs\0" \ + "serverip=192.168.251.2\0" \ + "ipaddr=192.168.251.1\0" \ + "dtb_name_nfs=default\0" \ + "dtb_name_default=default\0" \ + "kernel_name=Image\0" \ + "partitionset_active=A\0" \ + "dtb_loadaddr=0x83000000\0" \ + "kernel_loadaddr=0x80280000\0" \ + "ip_method=none\0" \ + "rootfs_name=/dev/mmcblk0\0" \ + "upgrade_available=0\0" \ + "bootlimit=3\0" \ + "altbootcmd=run bootcmd\0" \ + "optargs=\0" \ + +/**********************************************************************/ + +#define ENV_EMMC ENV_EMMC_FCT_EMMC_BOOT \ + ENV_EMMC_FCT_LOADFROM_EMMC \ + ENV_EMMC_FCT_SET_EMMC_BOOTARGS \ + ENV_EMMC_FCT_SET_ACTIVE_PARTITION \ + ENV_FCT_CHECK_UPGRADE \ + ENV_EMMC_ALIASES \ + ENV_FCT_TOGGLE_PARTITION + +#define ENV_NET ENV_NET_FCT_BOOT \ + ENV_NET_FCT_NETARGS \ + ENV_BOOTARGS_DEFAULT -- 2.17.1

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[ANN] U-Boot v2020.01 released
by Tom Rini 07 Jan '20

07 Jan '20

Hey all, It's once again release day. While we've had a few things pop up near the end of the cycle I think we've got things handled well enough. In fact, I'm going to be open to doing, if needed, a v2020.01.y, with a fairly strict set of rules, if we have problems arise that can be safely addressed. I'd like to thank all of our contributors for their efforts. The next thing I'd like to point out is that as part of this release we've re-synced with upstream for libfdt and it's now more strict in somme cases. What this means for the end user is that, especially on platforms where the DT that we use is passed in from upstream, you may need a more up-to-date ATF binary. I believe this is documented in the i.MX8-based board READMEs and for Renesas platforms the patch is currently at: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3025 and I would like to thank Marek Vasut for digging into the details on this at almost the literal last minute. Another important part of this release is that we've migrated fully from Python 2.7 to Python 3 (with 3.5 being the minimum version required). Thanks again to everyone that put in some time and energy to digging into our problems here and helping to fix it. In terms of a changelog, git log --merges v2020.01-rc5..v2020.01 or git log --merges v2019.10..v2020.01 The merge window is once again open and I plan to tag -rc1 on January 27th, bi-weekly -rcs thereafter and final release on April 6th, 2020. -- Tom

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