January 2020 - U-Boot

[PATCH] arm: zynq: Remove low level UART setting
by Michal Simek 16 Jan '20

16 Jan '20

There is no reason to do serial initializationin low level code. Uart driver does it already based on DT. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- .../zynq/zynq-syzygy-hub/ps7_init_gpl.c | 4 - .../zynq/zynq-topic-miami/ps7_init_gpl.c | 8 - .../zynq/zynq-topic-miamilite/ps7_init_gpl.c | 8 - .../zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 8 - board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c | 12 -- .../zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c | 4 - .../xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 186 ------------------ board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 186 ------------------ board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 186 ------------------ .../zynq/zynq-zc770-xm010/ps7_init_gpl.c | 12 -- .../zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c | 12 -- .../zynq/zynq-zc770-xm011/ps7_init_gpl.c | 12 -- .../zynq/zynq-zc770-xm012/ps7_init_gpl.c | 12 -- .../zynq/zynq-zc770-xm013/ps7_init_gpl.c | 12 -- board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 186 ------------------ board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c | 8 - board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c | 4 - board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 186 ------------------ 18 files changed, 1046 deletions(-) diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c index 500dcce4da5c..80f2b83b5899 100644 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c @@ -220,10 +220,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0XF8000004, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U), diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c index 8be3fb1e35a8..360beaef8ecf 100644 --- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c @@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c index afec4038d3e7..ae4666f7d590 100644 --- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c index d90a350d3fe0..717955808de6 100644 --- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c @@ -171,14 +171,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c index 218307f861c1..82f270c2e18e 100644 --- a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c @@ -227,10 +227,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), @@ -474,10 +470,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), @@ -714,10 +706,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c index 5366956e5bfd..75095ee3d4c7 100644 --- a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c @@ -219,10 +219,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0xF8000004, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index 39afd82195c2..337af2d9649f 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -7894,70 +7836,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12094,70 +11972,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index 88ff7947f20e..248c72861c8e 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -3666,64 +3666,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -8046,70 +7988,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12359,70 +12237,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index e9e4e4d077b7..c84ee6b1f214 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -3635,64 +3635,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -7984,70 +7926,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12266,70 +12144,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c index 95cc25a03ed9..b4663818ddb9 100644 --- a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c @@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -461,10 +457,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -699,10 +691,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c index 209f5ed7aa2f..254a512ccb6d 100644 --- a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c @@ -212,10 +212,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -446,10 +442,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -678,10 +670,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), diff --git a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c index 31c497b3e699..f4362b943b02 100644 --- a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c @@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -442,10 +438,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -672,10 +664,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), diff --git a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c index e966304e4a4d..621de09cc656 100644 --- a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c @@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU), @@ -467,10 +463,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU), @@ -711,10 +703,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU), diff --git a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c index 5770c4d5d34c..eefd46d932c8 100644 --- a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c @@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -439,10 +435,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -666,10 +658,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index df7d3535ddb7..7a15ea572969 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -7860,70 +7802,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12026,70 +11904,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c index d4f0ee796f72..5d573868cb1a 100644 --- a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c @@ -222,14 +222,6 @@ static unsigned long ps7_peripherals_init_data[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0xF8000004, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U), diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c index f1b935778047..7c6bc9fa3f42 100644 --- a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c @@ -235,10 +235,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0xF8000004, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U), diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c index c41283704caa..fda6d18dd92c 100644 --- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c @@ -3647,64 +3647,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. FINISH: LOCK IT BACK */ /* .. START: SRAM/NOR SET OPMODE */ /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -7944,70 +7886,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. FINISH: LOCK IT BACK */ /* .. START: SRAM/NOR SET OPMODE */ /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. IRMODE = 0x0 */ - /* .. ==> 0XE0001004[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. UCLKEN = 0x0 */ - /* .. ==> 0XE0001004[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -12172,70 +12050,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. FINISH: LOCK IT BACK */ /* .. START: SRAM/NOR SET OPMODE */ /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. IRMODE = 0x0 */ - /* .. ==> 0XE0001004[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. UCLKEN = 0x0 */ - /* .. ==> 0XE0001004[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ -- 2.24.0

2 1

[PATCH] arm64: zynqmp: Enable bind/unbind commands for all boards
by Michal Simek 16 Jan '20

16 Jan '20

These commands are useful in connection to usb and other devices that's why enable it by default. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 + configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 + configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 + configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu1275_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu1275_revB_defconfig | 1 + configs/xilinx_zynqmp_zcu216_revA_defconfig | 1 + 17 files changed, 17 insertions(+) diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 73617cedd236..f79d803d3225 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index 3341af14443f..bc3d0dfe2201 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index af79cf755249..65ce1ff2d337 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 986754018278..0492aba7f4a2 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index b22ebdac1505..84a2cd77f766 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index a59194288ba9..e6ea056a77d2 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index e1cc92425188..92cfe22d16a1 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index e924c0347f17..af4a6df5933a 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 5274c6f30188..05f25c262af4 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 23341d609dae..62b66f55f6bd 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_ATF=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 8a81111f4b39..84b714a3256d 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index ca7724052ce8..62fecca1c698 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index 2878d2d008e7..3fb48cb3c21d 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index 40cae18ab69b..231bf521d1f2 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig index 279fa5d43526..9d7efe0ca5f0 100644 --- a/configs/xilinx_zynqmp_zcu1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig index 0a334260ed08..87d486702851 100644 --- a/configs/xilinx_zynqmp_zcu1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y diff --git a/configs/xilinx_zynqmp_zcu216_revA_defconfig b/configs/xilinx_zynqmp_zcu216_revA_defconfig index 48d760a962af..14a3d84a2d46 100644 --- a/configs/xilinx_zynqmp_zcu216_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu216_revA_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y -- 2.24.0

2 1

[PATCH] arm64: zynqmp: Remove nand partition description from mini-nand
by Michal Simek 16 Jan '20

16 Jan '20

There shouldn't be a need to use any partition description because it can be used for writing data anywhere. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-mini-nand.dts | 49 ------------------------------- 1 file changed, 49 deletions(-) diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 93aa193f0178..d376ade83472 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -50,55 +50,6 @@ #size-cells = <1>; arasan,has-mdma; num-cs = <2>; - - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1C00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xFCC00000>; - }; - partition@6 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x1 0x0 0x400000>; - }; - partition@7 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x1 0x400000 0x1400000>; - }; - partition@8 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x1 0x1800000 0x400000>; - }; - partition@9 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x1 0x1C00000 0x1400000>; - }; - partition@10 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x1 0x3000000 0x400000>; - }; - partition@11 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x1 0x3400000 0xFCC00000>; - }; }; }; }; -- 2.24.0

2 1

[PATCH] arm64: zynqmp: Fix symlinks to SC psu_init* files
by Michal Simek 16 Jan '20

16 Jan '20

Names have to match device tree file names. Also add missing one. Fixes: 50d92833477e ("arm64: zynqmp: Sync names for SC with Versal") Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- .../zynqmp/{zynqmp-a2197-g-revA => zynqmp-g-a2197-00-revA} | 0 .../zynqmp/{zynqmp-a2197-m-revA => zynqmp-m-a2197-01-revA} | 0 .../zynqmp/{zynqmp-a2197-p-revA => zynqmp-m-a2197-02-revA} | 0 board/xilinx/zynqmp/zynqmp-m-a2197-03-revA | 1 + board/xilinx/zynqmp/zynqmp-p-a2197-00-revA | 1 + 5 files changed, 2 insertions(+) rename board/xilinx/zynqmp/{zynqmp-a2197-g-revA => zynqmp-g-a2197-00-revA} (100%) rename board/xilinx/zynqmp/{zynqmp-a2197-m-revA => zynqmp-m-a2197-01-revA} (100%) rename board/xilinx/zynqmp/{zynqmp-a2197-p-revA => zynqmp-m-a2197-02-revA} (100%) create mode 120000 board/xilinx/zynqmp/zynqmp-m-a2197-03-revA create mode 120000 board/xilinx/zynqmp/zynqmp-p-a2197-00-revA diff --git a/board/xilinx/zynqmp/zynqmp-a2197-g-revA b/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA similarity index 100% rename from board/xilinx/zynqmp/zynqmp-a2197-g-revA rename to board/xilinx/zynqmp/zynqmp-g-a2197-00-revA diff --git a/board/xilinx/zynqmp/zynqmp-a2197-m-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA similarity index 100% rename from board/xilinx/zynqmp/zynqmp-a2197-m-revA rename to board/xilinx/zynqmp/zynqmp-m-a2197-01-revA diff --git a/board/xilinx/zynqmp/zynqmp-a2197-p-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA similarity index 100% rename from board/xilinx/zynqmp/zynqmp-a2197-p-revA rename to board/xilinx/zynqmp/zynqmp-m-a2197-02-revA diff --git a/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA new file mode 120000 index 000000000000..a64c140b860a --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA @@ -0,0 +1 @@ +zynqmp-a2197-revA \ No newline at end of file diff --git a/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA new file mode 120000 index 000000000000..a64c140b860a --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA @@ -0,0 +1 @@ +zynqmp-a2197-revA \ No newline at end of file -- 2.24.0

2 1

[PATCH] arm64: zynqmp: Add board_boot_order for MMC boot extension
by Michal Simek 16 Jan '20

16 Jan '20

In past SPL_ZYNQMP_TWO_SDHCI symbol was introduced to handle boards with two sdhci controllers. The problem was that U-Boot is registering controllers based on aliases in DT but bootmode targets specific controller ID. That's why on boards with one "second" sdhci controller bootmode was pointing to second controller(MMC2) but alias was setup to mmc0 (the first controller). And SPL requires to point to mmc0 in this case. Long time ago commit f101e4bd3703 ("spl: add support for alternative boot device") added support for handling multiple bootmodes in SPL. Use this functionality and setup second sdhci controller as backup boot device. Below is table with behavior: HW/bootmode bootorder sd0/sd0 mmc0/mmc1 (mmc1 never called) sd1/sd1 mmc1/mmc0 (mmc0 fails and mmc1 is called) sd0+sd1/sd0 mmc0/mmc1 (mmc1 never called) sd0+sd1/sd1 mmc1/mmc0 (mmc0 never called) All other bootmodes are not affected but order can be extended to cover advance boot flows. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/mach-zynqmp/Kconfig | 11 ----------- arch/arm/mach-zynqmp/spl.c | 14 ++++++++++---- ...ltrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 - configs/xilinx_zynqmp_p_a2197_00_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - 5 files changed, 10 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 6cf17eb94e11..d82a737a699e 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -117,17 +117,6 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED config ZYNQ_SDHCI_MAX_FREQ default 200000000 -config SPL_ZYNQMP_TWO_SDHCI - bool "Enable booting from both SDHCIs" - depends on SPL - help - This option reflects that board has two SDHCI controllers which - platform can use as boot device. This option ensures that SPL will - setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for - SDHCI0 controller. Platforms which have only one SDHCI controller - shouldn't enable this option because it for software SDHCI0 or SDHCI1 - are both covered by BOOT_DEVICE_MMC1. - config SPL_ZYNQMP_ALT_BOOTMODE hex default 0x0 if JTAG_MODE diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 8bb1cdf69e1b..37f690d9b958 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -65,6 +65,16 @@ void spl_board_init(void) } #endif +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + + if (spl_boot_list[0] == BOOT_DEVICE_MMC1) + spl_boot_list[1] = BOOT_DEVICE_MMC2; + if (spl_boot_list[0] == BOOT_DEVICE_MMC2) + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} + u32 spl_boot_device(void) { u32 reg = 0; @@ -88,11 +98,7 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_MMC_SUPPORT case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ -/* if both controllers enabled, then these two are the second controller */ -#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI return BOOT_DEVICE_MMC2; -/* else, fall through, the one SDHCI controller that is enabled is number 1 */ -#endif case SD_MODE: case EMMC_MODE: return BOOT_DEVICE_MMC1; diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 177558db4198..280983d187a1 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig index ba2cbaba58e9..f206be8a3145 100644 --- a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig +++ b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig @@ -9,7 +9,6 @@ CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ZYNQMP_USB=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 65ce1ff2d337..c7524f630788 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_PMUFW_INIT_FILE="/mnt/disk/u-boot-bins/zynqmp/zynqmp-zc1751-xm015-dc1/pmufw.bin" CONFIG_ZYNQMP_USB=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y -- 2.24.0

2 1

[PATCH] arm64: zynqmp: Fix return value of board_fit_config_name_match
by Michal Simek 16 Jan '20

16 Jan '20

Empty implementation should not return 0 (success) because that mean that passed name matches the board configuration. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/mach-zynqmp/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 37f690d9b958..76bafcdd2a38 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -139,6 +139,6 @@ int board_fit_config_name_match(const char *name) /* Just empty function now - can't decide what to choose */ debug("%s: %s\n", __func__, name); - return 0; + return -1; } #endif -- 2.24.0

2 1

[PATCH] arm: xilinx: Use device tree which can be passed on cmd line
by Michal Simek 16 Jan '20

16 Jan '20

DEVICE_TREE variable has been added by commit 6ab6b2afa091 ("dts: re-write dts/Makefile more simply with Kbuild") where DT can be specified on command line. If it is not then CONFIG_DEFAULT_DEVICE_TREE is used to ensure backward compatibility. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynq/Makefile | 2 +- board/xilinx/zynqmp/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 8d3301543959..6a2acee108fa 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -14,7 +14,7 @@ spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F endif ifeq ($(init-objs),) -hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) +hw-platform-y :=$(shell echo $(DEVICE_TREE)) init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\ $(hw-platform-y)/ps7_init_gpl.o) endif diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 5ace6cc1b478..174f4ed24be3 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -14,7 +14,7 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN endif ifeq ($(init-objs),) -hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) +hw-platform-y :=$(shell echo $(DEVICE_TREE)) init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\ $(hw-platform-y)/psu_init_gpl.o) endif -- 2.24.0

2 1

[PATCH 0/2] mtd: nand: Move zynq nand driver to driver model
by Michal Simek 16 Jan '20

16 Jan '20

Hi, This series is moving Xilinx Zynq NAND driver to driver model. It allows us to remove hardcoded base address of smc and nand controller and get base addresses from device tree. Thanks, Michal Ashok Reddy Soma (2): zynq: mtd: nand: Move zynq nand driver to driver model zynq: mtd: nand: Remove hardcoded base addresses arch/arm/mach-zynq/include/mach/hardware.h | 2 - drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/zynq_nand.c | 132 ++++++++++++++------- 3 files changed, 88 insertions(+), 47 deletions(-) -- 2.24.0

2 3

[PATCH] ARM: zynq: Remove unused QSPI and USB addresses
by Michal Simek 16 Jan '20

16 Jan '20

All drivers should be converted to DM already that's why these hardcoded base addresses are not needed anymore. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/mach-zynq/include/mach/hardware.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index 0fe49aeb2276..89eb565c9412 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -9,11 +9,8 @@ #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 -#define ZYNQ_QSPI_BASEADDR 0xE000D000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 -#define ZYNQ_USB_BASEADDR0 0xE0002000 -#define ZYNQ_USB_BASEADDR1 0xE0003000 #define ZYNQ_OCM_BASEADDR 0xFFFC0000 /* Bootmode setting values */ -- 2.24.0

2 1

[PATCH v2] test/py: hush_if_test: Add tests to cover octal/hex values
by Michal Simek 16 Jan '20

16 Jan '20

Extend test suite to cover also automatic octal/hex converstions which haven't been implemented in past. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Acked-by: Stephen Warren <swarren(a)nvidia.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- Changes in v2: - Based on discussion with Simon add TODO Depends on https://lists.denx.de/pipermail/u-boot/2019-September/383309.html There are of course other tests which we can run but not sure if make sense to have there all combinations. The most interesting are mixed tests which are failing before patch above is applied. Definitely please let me know if you want to add any other test. --- test/py/tests/test_hush_if_test.py | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py index bba8d41d9648..d117921a6ac7 100644 --- a/test/py/tests/test_hush_if_test.py +++ b/test/py/tests/test_hush_if_test.py @@ -7,6 +7,10 @@ import os import os.path import pytest +# TODO: These tests should be converted to a C test. +# For more information please take a look at the thread +# https://lists.denx.de/pipermail/u-boot/2019-October/388732.html + pytestmark = pytest.mark.buildconfigspec('hush_parser') # The list of "if test" conditions to test. @@ -52,6 +56,33 @@ subtests = ( ('test 123 -ge 123', True), ('test 123 -ge 456', False), + # Octal tests + + ('test 010 -eq 010', True), + ('test 010 -eq 011', False), + + ('test 010 -ne 011', True), + ('test 010 -ne 010', False), + + # Hexadecimal tests + + ('test 0x2000000 -gt 0x2000001', False), + ('test 0x2000000 -gt 0x2000000', False), + ('test 0x2000000 -gt 0x1ffffff', True), + + # Mixed tests + + ('test 010 -eq 10', False), + ('test 010 -ne 10', True), + ('test 0xa -eq 10', True), + ('test 0xa -eq 012', True), + + ('test 2000000 -gt 0x1ffffff', False), + ('test 0x2000000 -gt 1ffffff', True), + ('test 0x2000000 -lt 1ffffff', False), + ('test 0x2000000 -eq 2000000', False), + ('test 0x2000000 -ne 2000000', True), + ('test -z ""', True), ('test -z "aaa"', False), -- 2.24.0

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