January 2020 - U-Boot

[PATCH v2 0/7] Add Support for MMC/SD in J721e
by Faiz Abbas 20 Jan '20

20 Jan '20

The following patches add support for MMC/SD in J721e. Currently, SD card is capped at 25 MBps and eMMC is capped at 50 MBps. Support for higher speeds and eMMC boot support will be added in futures series. v2: 1. Dropped FAT_WRITE patch because its already merged. 2. Fixed up environment patch to support latest CONFIGS. 3. Rebased to the latest u-boot-ti next branch Faiz Abbas (7): mmc: am654_sdhci: Get Xin clock by name mmc: am654_sdhci: Add Support for configuring PHY in J721e arm: dts: k3-j721e-common-proc-board: Remove voltage-ranges from sdhci nodes arm: dts: k3-j721e-common-proc-board: Add pinmux for SD card configs: j721e_evm: Add configs for ADMA Support configs: j721e_evm_a72: Add Support for GPT partitions configs: j721e_evm: Add configs for environment in eMMC arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 3 +- .../k3-j721e-common-proc-board-u-boot.dtsi | 4 + arch/arm/dts/k3-j721e-common-proc-board.dts | 22 ++- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 16 +++ configs/j721e_evm_a72_defconfig | 9 +- configs/j721e_evm_r5_defconfig | 7 +- drivers/mmc/am654_sdhci.c | 129 ++++++++++++++---- include/configs/j721e_evm.h | 12 ++ 8 files changed, 166 insertions(+), 36 deletions(-) -- 2.19.2

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[PATCH v4 00/10] dma: ti: k3-udma: Add support for J721e
by Vignesh Raghavendra 20 Jan '20

20 Jan '20

This series adds DMA support for J721e using exist K3 UDMA driver. One main change is thati, on J721e, DMA resources such as DMA channels are shared between different entities running on different cores of the SoC. Therefore, U-Boot running on A72 core should request range of resources allocated to it from centralized resource management core (DMSC) and use only the allocated resource. First two patches adds support for dynamically querying and using allocated resources. Remaining patches fix issues when using UDMA driver on a 32 bit core like R5. Last patch adds a new compatible for J721e v4: Rebase onto latest master and fix a compliation error due to recent changes in master. v3: Address comments by Grygorii and add R-by Vignesh Raghavendra (10): lib: Import few bitmap functions from Linux dma: ti: k3-udma: Query DMA channels allocated from Resource Manager soc: ti: k3-navss-ringacc: Flush/invalidate caches on ring push/pop soc: ti: k3-navss-ringacc: Get SYSFW reference from DT phandle dma: ti: k3-udma: Remove coherency check for cache ops dma: ti: k3-udma: Fix debug prints during enabling MEM_TO_DEV transfers dma: ti: k3-udma: Switch to exposed ring mode dma: ti: k3-udma: Fix ring push operation for 32 bit cores dma: ti: k3-udma: Fix build warnings when building for 32 bit platforms dma: ti: k3-udma: Add new compatible to J721e drivers/dma/ti/k3-udma.c | 365 ++++++++++++++++++++---------- drivers/soc/ti/k3-navss-ringacc.c | 14 +- include/linux/bitmap.h | 133 +++++++++++ include/linux/bitops.h | 12 + 4 files changed, 404 insertions(+), 120 deletions(-) -- 2.24.0

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[U-Boot] [PATCH] ARM: dts: da850-lcdk: Update DTS files for SPL device tree support
by Adam Ford 20 Jan '20

20 Jan '20

Currently, the da850-lcdk uses SPL_OF_PLATDATA and manually loads the necessary source code instead of using the auto-generated, because the drivers don't properly autogenerate the code. This patch simply enables the various device tree options to mimic the da850-evm which doesn't need or use OF_PLATDATA for device tree support. It does not disable OF_PLATDATA. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi index 541f4ca200..b372d06ca9 100644 --- a/arch/arm/dts/da850-lcdk-u-boot.dtsi +++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi @@ -8,9 +8,23 @@ / { aliases { i2c0 = &i2c0; + mmc0 = &mmc0; + serial2 = &serial2; + }; + + soc@1c00000 { + u-boot,dm-spl; }; nand { compatible = "ti,davinci-nand"; }; }; + +&mmc0 { + u-boot,dm-spl; +}; + +&serial2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/da850-lcdk.dts b/arch/arm/dts/da850-lcdk.dts index 0177e3ed20..db8ae566f3 100644 --- a/arch/arm/dts/da850-lcdk.dts +++ b/arch/arm/dts/da850-lcdk.dts @@ -18,7 +18,7 @@ }; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = &serial2; }; memory@c0000000 { -- 2.20.1

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[U-Boot] [PATCH] thermal: ti-bandgap: Fix adc value datatype
by Faiz Abbas 20 Jan '20

20 Jan '20

The CORE_TEMP_SENSOR_MPU register gives a raw adc value which needs to be indexed into a lookup table to get the actual temperature. Fix the naming and datatype of the adc value variable. Signed-off-by: Faiz Abbas <faiz_abbas(a)ti.com> --- drivers/thermal/ti-bandgap.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c index b490391e96..8b332f116c 100644 --- a/drivers/thermal/ti-bandgap.c +++ b/drivers/thermal/ti-bandgap.c @@ -26,7 +26,7 @@ struct ti_bandgap { ulong base; - int temperature; /* in mili degree celsius */ + uint adc_val; }; /* @@ -162,8 +162,8 @@ static int ti_bandgap_get_temp(struct udevice *dev, int *temp) { struct ti_bandgap *bgp = dev_get_priv(dev); - bgp->temperature = 0x3ff & readl(bgp->base + CTRL_CORE_TEMP_SENSOR_MPU); - *temp = dra752_adc_to_temp[bgp->temperature - DRA752_ADC_START_VALUE]; + bgp->adc_val = 0x3ff & readl(bgp->base + CTRL_CORE_TEMP_SENSOR_MPU); + *temp = dra752_adc_to_temp[bgp->adc_val - DRA752_ADC_START_VALUE]; return 0; } -- 2.19.2

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[U-Boot] [PATCH 0/4] J721e: Add USB support
by Vignesh Raghavendra 20 Jan '20

20 Jan '20

Add USB support for J721e SoC. First patch fixes a compile issue with Cadence USB driver. Rest of the patches add env, DT and configs related to USB. Vignesh Raghavendra (4): usb: cdns3: Fix include file path environment: ti: Add DFU environment variables k3_dfu.h arm: dts: k3-j721e: Add DT nodes for USB configs: j721e_evm_a72_defconfig: Enable USB related configs .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++ arch/arm/dts/k3-j721e-common-proc-board.dts | 37 ++++++++++ arch/arm/dts/k3-j721e-main.dtsi | 70 +++++++++++++++++++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 7 ++ configs/j721e_evm_a72_defconfig | 28 ++++++++ drivers/usb/cdns3/core.c | 2 +- drivers/usb/cdns3/host.c | 2 +- include/configs/j721e_evm.h | 10 +++ include/environment/ti/k3_dfu.h | 46 ++++++++++++ 9 files changed, 214 insertions(+), 2 deletions(-) create mode 100644 include/environment/ti/k3_dfu.h -- 2.24.0

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[U-Boot] [PATCH] ARM: reset: use do_reset in SPL/TPL if SYSRESET was not enabled for them
by Claudius Heine 19 Jan '20

19 Jan '20

In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available anywere, even if SYSRESET is disabled for SPL/TPL. 'do_reset' is called from SPL for instance from the panic handler and PANIC_HANG is not set Signed-off-by: Claudius Heine <ch(a)denx.de> --- arch/arm/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 9de9a9acee..7bf2c077ba 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -56,7 +56,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_SYSRESET +ifndef CONFIG_$(SPL_TPL_)SYSRESET obj-y += reset.o endif -- 2.21.0

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[PATCH v2 01/21] mips: add support to restore exception vector base before booting linux
by Weijie Gao 19 Jan '20

19 Jan '20

In U-Boot the exception vector base will be moved to top of memory, to be used to display register dump when exception occurs. But some old linux kernel does not honor the base set in CP0_EBASE. A modified exception vector base will cause kernel crash. This patch adds an option to enable reset exception vector base to its previous value, or a user configured value before booting linux kernel. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v1: Moved core operations to trap_restore() in arch/mips/lib/traps.c. Save previous ebase instead of using 0x80000000 directly. Add options to use customized ebase. --- arch/mips/Kconfig | 30 +++++++++++++++++++++++++++++ arch/mips/include/asm/u-boot-mips.h | 2 ++ arch/mips/lib/bootm.c | 3 +++ arch/mips/lib/traps.c | 19 ++++++++++++++++++ 4 files changed, 54 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a3ae603044..5e20feeefb 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -287,6 +287,36 @@ config MIPS_RELOCATION_TABLE_SIZE If unsure, leave at the default value. +config RESTORE_EXCEPTION_VECTOR_BASE + bool "Restore exception vector base before booting linux kernel" + default n + help + In U-Boot the exception vector base will be moved to top of memory, + to be used to display register dump when exception occurs. + But some old linux kernel does not honor the base set in CP0_EBASE. + A modified exception vector base will cause kernel crash. + + This option will restore the exception vector base to its previous + value. + + If unsure, say N. + +config OVERRIDE_EXCEPTION_VECTOR_BASE + bool "Override the exception vector base to be restored" + depends on RESTORE_EXCEPTION_VECTOR_BASE + default n + help + Enable this option if you want to use a different exception vector + base rather than the previously saved one. + +config NEW_EXCEPTION_VECTOR_BASE + hex "New exception vector base" + depends on OVERRIDE_EXCEPTION_VECTOR_BASE + range 0x80000000 0xbffff000 + default 0x80000000 + help + The exception vector base to be restored before booting linux kernel + endmenu menu "OS boot interface" diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h index 88438b9576..8b37cc4029 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h @@ -9,4 +9,6 @@ void except_vec_ejtag_debug(void); int arch_misc_init(void); +void trap_restore(void); + #endif /* _U_BOOT_MIPS_H_ */ diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 8c0d7672f2..f1db6d23b8 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -294,6 +294,9 @@ static void boot_jump_linux(bootm_headers_t *images) bootstage_report(); #endif + if (CONFIG_IS_ENABLED(RESTORE_EXCEPTION_VECTOR_BASE)) + trap_restore(); + if (images->ft_len) kernel(-2, (ulong)images->ft_addr, 0, 0); else diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 6fe8ebd16b..20f45fc4ed 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -19,6 +19,8 @@ DECLARE_GLOBAL_DATA_PTR; +static unsigned long saved_ebase; + static void show_regs(const struct pt_regs *regs) { const int field = 2 * sizeof(unsigned long); @@ -101,7 +103,24 @@ void trap_init(ulong reloc_addr) set_handler(0x180, &except_vec3_generic, 0x80); set_handler(0x280, &except_vec_ejtag_debug, 0x80); + saved_ebase = read_c0_ebase() & 0xfffff000; + write_c0_ebase(ebase); clear_c0_status(ST0_BEV); execution_hazard_barrier(); } + +void trap_restore(void) +{ + set_c0_status(ST0_BEV); + execution_hazard_barrier(); + +#ifdef CONFIG_OVERRIDE_EXCEPTION_VECTOR_BASE + write_c0_ebase(CONFIG_NEW_EXCEPTION_VECTOR_BASE & 0xfffff000); +#else + write_c0_ebase(saved_ebase); +#endif + + clear_c0_status(ST0_BEV); + execution_hazard_barrier(); +} -- 2.17.1

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[PATCH v2 19/21] mips: mtmips: add SPL support
by Weijie Gao 19 Jan '20

19 Jan '20

This patch adds SPL support for mtmips platform. The lowlevel architecture is split into SPL and the rest parts are built into a memory loadable u-boot image. Optional SPL_DM and OF_CONTROL are also supported. The increment of size is very small (< 10 KiB) if SPL_DM and OF_CONTROL are not enabled and the memory bootable u-boot (u-boot.img) is generated automatically so there is not need to add a separate config for it. A lzma compressed payload (u-boot-lzma.img) is also generated and it will be combined with u-boot-spl.bin to form the unified ROM bootable binary u-boot-mtmips.bin. A spl loader is added to support uncompress the payload. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v1: move spl loader into this patch. add full pinmux for all three uarts. add optional DM & DT support. --- Makefile | 9 ++ arch/mips/Kconfig | 3 + arch/mips/dts/mt7628-u-boot.dtsi | 24 ++++ arch/mips/mach-mtmips/Kconfig | 24 ++++ arch/mips/mach-mtmips/Makefile | 1 + arch/mips/mach-mtmips/include/mach/serial.h | 13 +++ arch/mips/mach-mtmips/include/mach/spl.h | 14 +++ arch/mips/mach-mtmips/mt7628/Makefile | 1 + arch/mips/mach-mtmips/mt7628/serial.c | 34 ++++++ arch/mips/mach-mtmips/spl.c | 31 +++++ arch/mips/mach-mtmips/spl_load.c | 121 ++++++++++++++++++++ 11 files changed, 275 insertions(+) create mode 100644 arch/mips/dts/mt7628-u-boot.dtsi create mode 100644 arch/mips/mach-mtmips/include/mach/serial.h create mode 100644 arch/mips/mach-mtmips/include/mach/spl.h create mode 100644 arch/mips/mach-mtmips/mt7628/serial.c create mode 100644 arch/mips/mach-mtmips/spl.c create mode 100644 arch/mips/mach-mtmips/spl_load.c diff --git a/Makefile b/Makefile index 8013cbd9f9..1e18a37913 100644 --- a/Makefile +++ b/Makefile @@ -895,6 +895,7 @@ ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin endif ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin +ALL-$(CONFIG_ARCH_MTMIPS) += u-boot-mtmips.bin # Add optional build target if defined in board/cpu/soc headers ifneq ($(CONFIG_BUILD_TARGET),) @@ -1664,6 +1665,14 @@ u-boot-mtk.bin: u-boot.bin FORCE $(call if_changed,mkimage) endif +ifeq ($(CONFIG_SPL),y) +u-boot-mtmips.bin: u-boot.dtb u-boot-lzma.img spl/u-boot-spl.bin FORCE + $(call if_changed,binman) +else +u-boot-mtmips.bin: u-boot.bin FORCE + $(call if_changed,copy) +endif + ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink) # Rule to link u-boot diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5f82caf8be..5f74f549b5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -98,6 +98,9 @@ config ARCH_MTMIPS select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_LITTLE_ENDIAN select SYSRESET + select SUPPORT_SPL + select SPL_LZMA + select BINMAN config ARCH_JZ47XX bool "Support Ingenic JZ47xx" diff --git a/arch/mips/dts/mt7628-u-boot.dtsi b/arch/mips/dts/mt7628-u-boot.dtsi new file mode 100644 index 0000000000..213959105f --- /dev/null +++ b/arch/mips/dts/mt7628-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +/ { + binman { + filename = "u-boot-mtmips.bin"; + pad-byte = <0xff>; + +#ifdef CONFIG_SPL + u-boot-spl { + }; + + u-boot-lzma-img { + }; +#else + u-boot { + }; +#endif + }; +}; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 3f25de8b85..9b42d5b581 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -20,8 +20,16 @@ config SYS_ICACHE_LINE_SIZE default 32 config SYS_TEXT_BASE + default 0x9c000000 if !SPL + default 0x80200000 if SPL + +config SPL_TEXT_BASE default 0x9c000000 +config SPL_LOADER_SUPPORT + bool + default y + choice prompt "MediaTek MIPS SoC select" @@ -34,6 +42,14 @@ config SOC_MT7628 select PINCTRL_MT7628 select MTK_SERIAL select SYSRESET_RESETCTL + select SPL_SEPARATE_BSS if SPL + select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL + select SPL_OF_CONTROL if SPL_DM + select SPL_SIMPLE_BUS if SPL_DM + select SPL_DM_SERIAL if SPL_DM + select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT + select SPL_SYSRESET if SPL_DM + select SPL_OF_LIBFDT if SPL_OF_CONTROL help This supports MediaTek MT7628/MT7688. @@ -88,6 +104,14 @@ endchoice config SUPPORTS_BOOT_RAM bool +config SPL_UART2_SPIS_PINMUX + bool "Use alternative pinmux for UART2 in SPL stage" + depends on SPL_SERIAL_SUPPORT + default n + help + Select this if the UART2 of your board is connected to GPIO 16/17 + (shared with SPIS) rather than the usual GPIO 20/21. + source "board/gardena/smart-gateway-mt7688/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach-mtmips/Makefile index 72f0369030..08d2a236d0 100644 --- a/arch/mips/mach-mtmips/Makefile +++ b/arch/mips/mach-mtmips/Makefile @@ -3,5 +3,6 @@ obj-y += cpu.o obj-y += ddr_init.o obj-y += ddr_cal.o +obj-$(CONFIG_SPL_BUILD) += spl.o spl_load.o obj-$(CONFIG_SOC_MT7628) += mt7628/ diff --git a/arch/mips/mach-mtmips/include/mach/serial.h b/arch/mips/mach-mtmips/include/mach/serial.h new file mode 100644 index 0000000000..bfa246b428 --- /dev/null +++ b/arch/mips/mach-mtmips/include/mach/serial.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#ifndef _MTMIPS_SERIAL_H_ +#define _MTMIPS_SERIAL_H_ + +void mtmips_spl_serial_init(void); + +#endif /* _MTMIPS_SERIAL_H_ */ diff --git a/arch/mips/mach-mtmips/include/mach/spl.h b/arch/mips/mach-mtmips/include/mach/spl.h new file mode 100644 index 0000000000..5674dd533e --- /dev/null +++ b/arch/mips/mach-mtmips/include/mach/spl.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ +#ifndef _MACH_MTMIPS_SPL_H_ +#define _MACH_MTMIPS_SPL_H_ + +#include <asm/spl.h> + +#define BOOT_DEVICE_MTMIPS_NOR (BOOT_DEVICE_BOOTROM + 0x100) + +#endif /* _MACH_MTMIPS_SPL_H_ */ diff --git a/arch/mips/mach-mtmips/mt7628/Makefile b/arch/mips/mach-mtmips/mt7628/Makefile index db62e90d77..7e139d5adf 100644 --- a/arch/mips/mach-mtmips/mt7628/Makefile +++ b/arch/mips/mach-mtmips/mt7628/Makefile @@ -3,3 +3,4 @@ obj-y += lowlevel_init.o obj-y += init.o obj-y += ddr.o +obj-$(CONFIG_SPL_BUILD) += serial.o diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c new file mode 100644 index 0000000000..a7d324792d --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/serial.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#include <common.h> +#include <asm/io.h> +#include "mt7628.h" + +void mtmips_spl_serial_init(void) +{ +#ifdef CONFIG_SPL_SERIAL_SUPPORT + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + +#if CONFIG_CONS_INDEX == 1 + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M); +#elif CONFIG_CONS_INDEX == 2 + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M); +#elif CONFIG_CONS_INDEX == 3 + setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M); +#ifdef CONFIG_SPL_UART2_SPIS_PINMUX + setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M); + clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M, + 1 << UART2_MODE_S); +#else + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M); + clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M, + 1 << SPIS_MODE_S); +#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */ +#endif /* CONFIG_CONS_INDEX */ +#endif /* CONFIG_SPL_SERIAL_SUPPORT */ +} diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c new file mode 100644 index 0000000000..f12fb70d75 --- /dev/null +++ b/arch/mips/mach-mtmips/spl.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#include <common.h> +#include <spl.h> +#include <linux/sizes.h> +#include <mach/serial.h> +#include <mach/spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +void __noreturn board_init_f(ulong dummy) +{ + spl_init(); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + mtmips_spl_serial_init(); + preloader_console_init(); +#endif + + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MTMIPS_NOR; +} diff --git a/arch/mips/mach-mtmips/spl_load.c b/arch/mips/mach-mtmips/spl_load.c new file mode 100644 index 0000000000..95dd491baa --- /dev/null +++ b/arch/mips/mach-mtmips/spl_load.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao(a)mediatek.com> + */ + +#include <common.h> +#include <cpu_func.h> +#include <asm/sections.h> +#include <linux/compiler.h> +#include <linux/sizes.h> +#include <mach/spl.h> +#include <spl.h> + +#ifdef CONFIG_SPL_LZMA +#include <lzma/LzmaTypes.h> +#include <lzma/LzmaDec.h> +#include <lzma/LzmaTools.h> +#endif /* CONFIG_SPL_LZMA */ + +#if CONFIG_IS_ENABLED(OF_CONTROL) && defined(CONFIG_OF_SEPARATE) +#include <fdt.h> +#endif + +static ulong spl_dtb_size(void) +{ +#if CONFIG_IS_ENABLED(OF_CONTROL) + void *fdt = __image_copy_end; + + if (fdt_magic(fdt) == FDT_MAGIC) + return fdt_totalsize(fdt); +#endif + + return 0; +} + +static int spl_try_load_image(struct spl_image_info *spl_image, + void *image_addr) +{ + int ret; + uintptr_t dataptr; + struct image_header hdr; + size_t __maybe_unused lzma_len; + + memcpy(&hdr, (const void *)image_addr, sizeof(hdr)); + + ret = spl_parse_image_header(spl_image, &hdr); + if (ret) + return ret; + + if (!spl_image->entry_point) + spl_image->entry_point = spl_image->load_addr; + + dataptr = (uintptr_t)image_addr + sizeof(hdr); + + switch (hdr.ih_comp) { + case IH_COMP_NONE: + /* + * Load real U-Boot from its location to its defined location + * in SDRAM + */ + if (spl_image->load_addr != dataptr) { + memmove((void *)spl_image->load_addr, (void *)dataptr, + spl_image->size); + } + break; +#ifdef CONFIG_SPL_LZMA + case IH_COMP_LZMA: + /* + * Uncompress real U-Boot to its defined location in SDRAM + */ + lzma_len = SZ_8M; + + ret = lzmaBuffToBuffDecompress((u8 *)spl_image->load_addr, + &lzma_len, (u8 *)dataptr, + spl_image->size); + + if (ret) { + printf("Error: LZMA uncompression error: %d\n", ret); + return ret; + } + + spl_image->size = lzma_len; + break; +#endif /* CONFIG_SPL_LZMA */ + default: + debug("Warning: Unsupported compression method found in image " + "header at offset 0x%p\n", image_addr); + return -EINVAL; + } + + flush_cache((unsigned long)spl_image->load_addr, spl_image->size); + + return 0; +} + +static int spl_mtk_nor_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + ulong offset = spl_dtb_size(); + + /* + * Loading of the payload to SDRAM is done with skipping of + * the mkimage header + */ + spl_image->flags |= SPL_COPY_PAYLOAD_ONLY; + + /* Try to boot without padding */ + if (!spl_try_load_image(spl_image, (u8 *)__image_copy_end + offset)) + return 0; + +#ifdef CONFIG_SYS_UBOOT_BASE + /* Try user defined offset */ + if (!spl_try_load_image(spl_image, (void *)CONFIG_SYS_UBOOT_BASE)) + return 0; +#endif + + return -EINVAL; +} +SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_MTMIPS_NOR, spl_mtk_nor_load_image); -- 2.17.1

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[PATCH v2 11/21] dts: mtmips: remove all unusable nodes and properties from mt7628s.dtsi
by Weijie Gao 19 Jan '20

19 Jan '20

This patch removes all unused and unusable nodes and properties from mt7628s.dtsi. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v1: splitted from another patch --- arch/mips/dts/mt7628a.dtsi | 68 -------------------------------------- 1 file changed, 68 deletions(-) diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index cdc643fe37..3d7b839e6d 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -7,24 +7,6 @@ #size-cells = <1>; compatible = "ralink,mt7628a-soc"; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mti,mips24KEc"; - device_type = "cpu"; - reg = <0>; - }; - }; - - cpuintc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - clk48m: clk48m@0 { compatible = "fixed-clock"; @@ -41,11 +23,6 @@ #address-cells = <1>; #size-cells = <1>; - sysc: system-controller@0 { - compatible = "ralink,mt7620a-sysc", "syscon"; - reg = <0x0 0x100>; - }; - resetctl-reboot { compatible = "resetctl-reboot"; @@ -223,32 +200,6 @@ resets = <&rstctrl MT7628_TIMER_RST>; reset-names = "wdt"; - - interrupt-parent = <&intc>; - interrupts = <24>; - }; - - intc: interrupt-controller@200 { - compatible = "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - resets = <&rstctrl MT7628_INT_RST>; - reset-names = "intc"; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; - - ralink,intc-registers = <0x9c 0xa0 - 0x6c 0xa4 - 0x80 0x78>; - }; - - memory-controller@300 { - compatible = "ralink,mt7620a-memc"; - reg = <0x300 0x100>; }; gpio@600 { @@ -261,9 +212,6 @@ resets = <&rstctrl MT7628_PIO_RST>; reset-names = "pio"; - interrupt-parent = <&intc>; - interrupts = <6>; - gpio0: bank@0 { reg = <0>; compatible = "mtk,mt7621-gpio-bank"; @@ -311,9 +259,6 @@ resets = <&rstctrl MT7628_UART0_RST>; reset-names = "uart0"; - interrupt-parent = <&intc>; - interrupts = <20>; - reg-shift = <2>; }; @@ -329,9 +274,6 @@ resets = <&rstctrl MT7628_UART1_RST>; reset-names = "uart1"; - interrupt-parent = <&intc>; - interrupts = <21>; - reg-shift = <2>; }; @@ -347,9 +289,6 @@ resets = <&rstctrl MT7628_UART2_RST>; reset-names = "uart2"; - interrupt-parent = <&intc>; - interrupts = <22>; - reg-shift = <2>; }; }; @@ -361,8 +300,6 @@ resets = <&rstctrl MT7628_EPHY_RST>; reset-names = "ephy"; - - syscon = <&sysc>; }; usb_phy: usb-phy@10120000 { @@ -371,8 +308,6 @@ #phy-cells = <0>; - ralink,sysctl = <&sysc>; - resets = <&rstctrl MT7628_UPHY_RST>; reset-names = "phy"; @@ -386,9 +321,6 @@ phys = <&usb_phy>; phy-names = "usb"; - - interrupt-parent = <&intc>; - interrupts = <18>; }; mmc: mmc@10130000 { -- 2.17.1

2 2

[PATCH v2 09/21] mips: add a option to support not reserving malloc space on initial stack
by Weijie Gao 19 Jan '20

19 Jan '20

The initial stack on some platforms is too small to hold a large malloc space. This patch adds a option to allow these platforms not reserving the malloc space on initial stack. These platforms should set the malloc base after DRAM is usable. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- Changes since v1: newly added --- arch/mips/Kconfig | 18 ++++++++++++++++++ arch/mips/cpu/start.S | 6 ++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bf30a56101..5f82caf8be 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -317,6 +317,24 @@ config NEW_EXCEPTION_VECTOR_BASE help The exception vector base to be restored before booting linux kernel +config INIT_STACK_WITHOUT_MALLOC_F + bool "Do not reserve malloc space on initial stack" + default n + help + Enable this option if you don't want to reserve malloc space on + initial stack. This is useful if the initial stack can't hold large + malloc space. Platform should set the malloc_base later when DRAM is + ready to use. + +config SPL_INIT_STACK_WITHOUT_MALLOC_F + bool "Do not reserve malloc space on initial stack in SPL" + default n + help + Enable this option if you don't want to reserve malloc space on + initial stack. This is useful if the initial stack can't hold large + malloc space. Platform should set the malloc_base later when DRAM is + ready to use. + endmenu menu "OS boot interface" diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index dd93df9e4a..6de9a2f362 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -59,7 +59,8 @@ sp, sp, GD_SIZE # reserve space for gd and sp, sp, t0 # force 16 byte alignment move k0, sp # save gd pointer -#if CONFIG_VAL(SYS_MALLOC_F_LEN) +#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \ + !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) li t2, CONFIG_VAL(SYS_MALLOC_F_LEN) PTR_SUBU \ sp, sp, t2 # reserve space for early malloc @@ -75,7 +76,8 @@ blt t0, t1, 1b nop -#if CONFIG_VAL(SYS_MALLOC_F_LEN) +#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \ + !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset #endif .endm -- 2.17.1

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