January 2020 - U-Boot

[U-Boot] [PATCH V2 0/7] ARM: imx: Update Novena to DM/DT
by Marek Vasut 27 Jan '20

27 Jan '20

Update Kosagi Novena to DM / DT and remove the warnings. This depends on the following patches / series: https://patchwork.ozlabs.org/patch/1095618/ https://patchwork.ozlabs.org/patch/1101171/ https://patchwork.ozlabs.org/project/uboot/list/?series=108463 Marek Vasut (7): ARM: dts: imx: novena: Import Novena DT from Linux ARM: imx: novena: Enable DM pin control ARM: imx: novena: Enable DM GPIO ARM: imx: novena: Convert block devices to DM ARM: imx: novena: Enable DM USB ARM: imx: novena: Enable DM PCI ARM: imx: novena: Convert to DM VIDEO arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6q-novena.dts | 797 ++++++++++++++++++++++++++++++++++ board/kosagi/novena/novena.c | 77 +--- board/kosagi/novena/video.c | 3 + configs/novena_defconfig | 18 +- include/configs/novena.h | 9 +- 6 files changed, 838 insertions(+), 69 deletions(-) create mode 100644 arch/arm/dts/imx6q-novena.dts Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Vagrant Cascadian <vagrant(a)debian.org> -- 2.20.1

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[PATCH] riscv: Try to get cpu frequency from device tree
by Sean Anderson 26 Jan '20

26 Jan '20

Instead of always using the "clock-frequency" property to determine cpu frequency, try using a clock in "clocks" if it exists. Signed-off-by Sean Anderson <seanga2(a)gmail.com> --- This patch depends on <https://patchwork.ozlabs.org/patch/1223933/>. drivers/cpu/riscv_cpu.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 1e32bb5678..280c9de376 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -3,6 +3,7 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn(a)gmail.com> */ +#include <clk.h> #include <common.h> #include <cpu.h> #include <dm.h> @@ -27,11 +28,24 @@ static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) { + int err; + struct clk clk; const char *mmu; /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ info->cpu_freq = 0; - dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); + + /* First try getting the frequency from the assigned clock */ + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + info->cpu_freq = err; + clk_free(&clk); + } + + if (!info->cpu_freq) + dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); mmu = dev_read_string(dev, "mmu-type"); if (!mmu) -- 2.24.1

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[PATCH 1/2] arm: mvebu: fix A38x breakage from commit bb872dd930cc
by Joel Johnson 26 Jan '20

26 Jan '20

This function parameter usage of load_addr was incorrectly caught in the clarifying renames of commit bb872dd930cc, which results in boot failures on Marvell A38x. Signed-off-by: Joel Johnson <mrjoel(a)lixil.net> Patch-to: Simon Glass <sjg(a)chromium.org> --- drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c index 9293d54e5a..1eababeebd 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c @@ -615,7 +615,7 @@ int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, ODPG_DATA_BUFFER_OFFS_REG, - image_load_addr, MASK_ALL_BITS)); + load_addr, MASK_ALL_BITS)); return MV_OK; } -- 2.20.1

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[PATCH 0/3] fix pllv3 defects reported by Coverity
by Giulio Benetti 26 Jan '20

26 Jan '20

Giulio Benetti (3): clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() drivers/clk/imx/clk-pllv3.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) -- 2.20.1

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Pull request: u-boot-sunxi/master
by Jagan Teki 26 Jan '20

26 Jan '20

Hi Tom, Please pull this PR. Summary: - Libre Computer ALL-H3-IT/ALL-H5-CC board (Chen-Yu Tsai) - Allwinner R40 Ethernet, usb phy enablement (Andre Przywara) - Sunxi auto load from 128KB MMC offset (Andre Przywara) - Orange Pi Win Ethernet phy enablement (Jernej Skrabec) Thanks, Jagan. The following changes since commit 5692e8f7b44c0794ecfe8de92bc64897518623d0: common: Update comment to show progress (2020-01-24 23:06:49 +0530) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi master for you to fetch changes up to 2936eb2d550a642275113464fc9dcbb03357c049: configs: Orange Pi Win: enable ethernet phy (2020-01-26 20:59:51 +0530) ---------------------------------------------------------------- Andre Przywara (7): sunxi: dts: R40: Update Bananapi M2 Berry .dts sunxi: defconfig: Bananapi M2 Berry: enable Ethernet phy: sun4i-usb: Add Allwinner R40 support sunxi: defconfig: R40 boards: enable USB sunxi: move CONFIG_SYS_SPI_U_BOOT_OFFS out of defconfig sunxi: SPL: Factor out sunxi_get_boot_source() sunxi: Automate loading from 128KB MMC offset Chen-Yu Tsai (3): sunxi: H3/H5 Sync DT files from upstream Linux kernel as of next-20200108 sunxi: Add Libre Computer ALL-H3-IT H5 board sunxi: Add Libre Computer ALL-H5-CC H5 board Jernej Skrabec (1): configs: Orange Pi Win: enable ethernet phy arch/arm/dts/Makefile | 9 +- arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts | 11 ++ .../arm/dts/sun50i-h5-emlid-neutis-n5-devboard.dts | 137 ++------------- arch/arm/dts/sun50i-h5-emlid-neutis-n5.dtsi | 95 +---------- arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts | 10 +- arch/arm/dts/sun50i-h5-libretech-all-h3-it.dts | 11 ++ arch/arm/dts/sun50i-h5-libretech-all-h5-cc.dts | 61 +++++++ arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts | 53 +----- arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 45 +---- arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 47 +----- arch/arm/dts/sun50i-h5-orangepi-prime.dts | 52 +----- arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts | 11 +- arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts | 46 +---- arch/arm/dts/sun50i-h5.dtsi | 186 +++++++++++++++------ arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 40 ++++- arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts | 2 - arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 22 ++- arch/arm/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts | 13 ++ arch/arm/dts/sun8i-h3-beelink-x2.dts | 11 +- .../dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts | 72 ++++++++ arch/arm/dts/sun8i-h3-emlid-neutis-n5h3.dtsi | 11 ++ arch/arm/dts/sun8i-h3-mapleboard-mp130.dts | 152 +++++++++++++++++ arch/arm/dts/sun8i-h3-nanopi-duo2.dts | 173 +++++++++++++++++++ arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts | 28 +++- arch/arm/dts/sun8i-h3-nanopi-m1.dts | 2 +- arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 2 +- arch/arm/dts/sun8i-h3-nanopi.dtsi | 25 +-- arch/arm/dts/sun8i-h3-orangepi-2.dts | 34 +--- arch/arm/dts/sun8i-h3-orangepi-lite.dts | 27 +-- arch/arm/dts/sun8i-h3-orangepi-one.dts | 28 +--- arch/arm/dts/sun8i-h3-orangepi-pc.dts | 27 +-- arch/arm/dts/sun8i-h3-orangepi-plus.dts | 23 ++- arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts | 2 +- arch/arm/dts/sun8i-h3-rervision-dvk.dts | 114 +++++++++++++ arch/arm/dts/sun8i-h3.dtsi | 86 +++++++++- arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 135 +++++++++++++-- arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 30 ++++ arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 7 +- arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi | 170 +++++++++++++++++++ arch/arm/dts/sunxi-h3-h5.dtsi | 137 +++++++++------ arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 65 ++++++- arch/arm/dts/sunxi-libretech-all-h3-it.dtsi | 180 ++++++++++++++++++++ arch/arm/mach-sunxi/Kconfig | 1 + arch/arm/mach-sunxi/board.c | 38 ++++- board/sunxi/MAINTAINERS | 10 ++ common/spl/Kconfig | 1 + configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/Bananapi_M2_Ultra_defconfig | 4 + configs/bananapi_m2_berry_defconfig | 6 + configs/libretech_all_h3_it_h5_defconfig | 21 +++ configs/libretech_all_h5_cc_h5_defconfig | 22 +++ configs/oceanic_5205_5inmfd_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_r1_defconfig | 1 - configs/orangepi_win_defconfig | 3 +- configs/orangepi_zero_defconfig | 1 - configs/pine64-lts_defconfig | 1 - configs/sopine_baseboard_defconfig | 1 - drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++ include/dt-bindings/clock/sun8i-h3-ccu.h | 11 +- include/dt-bindings/reset/sun8i-h3-ccu.h | 5 +- 61 files changed, 1782 insertions(+), 751 deletions(-) create mode 100644 arch/arm/dts/sun50i-h5-bananapi-m2-plus-v1.2.dts create mode 100644 arch/arm/dts/sun50i-h5-libretech-all-h3-it.dts create mode 100644 arch/arm/dts/sun50i-h5-libretech-all-h5-cc.dts create mode 100644 arch/arm/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts create mode 100644 arch/arm/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts create mode 100644 arch/arm/dts/sun8i-h3-emlid-neutis-n5h3.dtsi create mode 100644 arch/arm/dts/sun8i-h3-mapleboard-mp130.dts create mode 100644 arch/arm/dts/sun8i-h3-nanopi-duo2.dts create mode 100644 arch/arm/dts/sun8i-h3-rervision-dvk.dts create mode 100644 arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi create mode 100644 arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi create mode 100644 arch/arm/dts/sunxi-libretech-all-h3-it.dtsi create mode 100644 configs/libretech_all_h3_it_h5_defconfig create mode 100644 configs/libretech_all_h5_cc_h5_defconfig

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[PATCH] mtd: spinand: winbond: Add support for W25N01GV
by Robert Marko 26 Jan '20

26 Jan '20

Linux has supported W25N01GV for a long time, so lets import it. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- drivers/mtd/nand/spi/winbond.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index eac811d97c..6ba8bc5c7b 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -86,6 +86,14 @@ static const struct spinand_info winbond_spinand_table[] = { 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), + SPINAND_INFO("W25N01GV", 0xAA, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(1, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), }; /** -- 2.24.1

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[PATCH 0/2] sunxi: Support automated booting from 128KB
by Andre Przywara 26 Jan '20

26 Jan '20

The Allwinner Boot ROM on all later SoCs can load the initial SPL code from offset 128KB or from offset 8KB of an SD card or eMMC. We support this in the SPL for a while now, but so far needed to manually adjust the U-Boot image MMC load sector during compile time. Since the Boot ROM writes a different boot source ID into the SRAM when loaded from the higher offset, we can check this value and dynamically adjust the raw MMC load sector for the U-Boot proper image. This allows to generate *one* image file, which can be written to either offset 8KB or to offset 128KB. The latter has the advantange of not overlapping with a standard GPT partition table. Tested on Bananapi M2 Berry (R40), Orangepi Zero (H2+), Orangepi PC 2 (H5), Pine64-LTS (A64), Bananapi-M64 (A64, both SD card and eMMC) and Pine H64 (H6), on all boards writing the same image to both 8K and 128K. Cheers, Andre. Andre Przywara (2): sunxi: SPL: Factor out sunxi_get_boot_source() sunxi: Automate loading from 128KB MMC offset arch/arm/mach-sunxi/board.c | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) -- 2.14.5

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[PATCH] configs: Orange Pi Win: enable ethernet
by Jernej Skrabec 26 Jan '20

26 Jan '20

Orange Pi Win has gigabit ethernet port, but default U-Boot configuration for that board didn't enable it. Fix that. Signed-off-by: Jernej Skrabec <jernej.skrabec(a)siol.net> --- configs/orangepi_win_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index ad74febe10..7a713ff0e2 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_MACH_SUN50I=y +CONFIG_MACPWR="PD14" CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -12,6 +13,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000 # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -- 2.25.0

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MMC on I.MX7/8MM break on U-Boot 2020.01-00630-gad647690b1
by Joris Offouga 26 Jan '20

26 Jan '20

Hi Tom I tested latest U-Boot master and it looks like commit 1526bcce (common: add blkcache init)[1] breaks load environment in mmc on my Pico-imx7d, imx7dsabre and imx8mm-evk: see logs after: U-Boot 2020.01-00731-g40521a6c90-dirty (Jan 26 2020 - 12:12:49 +0100) CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 29C Reset cause: POR Model: TechNexion PICO-IMX7D Board and PI baseboard Board: i.MX7D PICOSOM I2C: ready DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 2, FSL_SDHC: 1, FSL_SDHC: 0 Loading Environment from MMC... data abort pc : [<9feb0d4e>] lr : [<9feab5e5>] reloc pc : [<8781ad4e>] lr : [<878155e5>] sp : 9de8ac60 ip : 00000002 fp : 9fef3d1c r10: 00000000 r9 : 9de95ea0 r8 : 00000000 r7 : 00000006 r6 : feffff7f r5 : 9fefb620 r4 : feffff7f r3 : ffffefff r2 : 62168365 r1 : 00000000 r0 : 00000006 Flags: NzCv IRQs off FIQs off Mode SVC_32 (T) Code: 3b01 f8cb 3008 4634 (6836) e7df Resetting CPU ... resetting ... after revert it : U-Boot SPL 2020.01-00732-g80dd068886-dirty (Jan 26 2020 - 12:19:49 +0100) Trying to boot from USB SDP SDP: initialize... SDP: handle requests... Downloading file of size 482142 to 0x877fffc0... done Jumping to header at 0x877fffc0 Header Tag is not an IMX image -Boot 2020.01-00732-g80dd068886-dirty (Jan 26 2020 - 12:19:49 +0100) CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 40C Reset cause: POR Model: TechNexion PICO-IMX7D Board and PI baseboard Board: i.MX7D PICOSOM I2C: ready DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 2, FSL_SDHC: 1, FSL_SDHC: 0 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 So, can you consider this commit 'not applicable' for next release ? [1] https://gitlab.denx.de/u-boot/u-boot/commit/1526bcce0f7285087621e16e6720636… Best regards, Joris Offouga

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[PATCH V2 1/3] mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGA
by Marek Vasut 26 Jan '20

26 Jan '20

On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes leads to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- V2: Reword the commit message --- drivers/mtd/nand/raw/denali_spl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index dbaba3cab2..b8b29812aa 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -173,6 +173,13 @@ void nand_init(void) page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE); oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE); pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK); + + /* Do as denali_hw_init() does. */ + writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, + denali_flash_reg + SPARE_AREA_SKIP_BYTES); + writel(0x0F, denali_flash_reg + RB_PIN_ENABLED); + writel(CHIP_EN_DONT_CARE__FLAG, denali_flash_reg + CHIP_ENABLE_DONT_CARE); + writel(0xffff, denali_flash_reg + SPARE_AREA_MARKER); } int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) -- 2.24.1

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