January 2020 - U-Boot

[PATCH v4] board/lx2160aqds: Update the DSPI status fixup
by Xiaowei Bao 27 Jan '20

27 Jan '20

The dts node of the DSPI controller in kernel is spi instead of dspi, it is not correct if use "/soc/dspi@" to fix up the status of the dts in kernel, so, modify it to "/soc/spi@". The DSPI2 and I2C5 are muxed, and the status of DSPI2 node in kernel dts default value is okay, So set the status of DSPI2 node in kernel dts to disabled if it is muxed as I2C5. Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Modify the subject and commit message. v3: - Modify the Copyright. v4: - Modify the commit message. board/freescale/lx2160a/lx2160a.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index eff5d9f..184e111 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP */ #include <common.h> @@ -210,9 +210,9 @@ void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; const char esdhc1_path[] = "/soc/esdhc@2150000"; - const char dspi0_path[] = "/soc/dspi@2100000"; - const char dspi1_path[] = "/soc/dspi@2110000"; - const char dspi2_path[] = "/soc/dspi@2120000"; + const char dspi0_path[] = "/soc/spi@2100000"; + const char dspi1_path[] = "/soc/spi@2110000"; + const char dspi2_path[] = "/soc/spi@2120000"; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 sdhc1_base_pmux; @@ -262,10 +262,12 @@ void esdhc_dspi_status_fixup(void *blob) & FSL_CHASSIS3_IIC5_PMUX_MASK; iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; - if (iic5_pmux == IIC5_PMUX_SPI3) { + if (iic5_pmux == IIC5_PMUX_SPI3) do_fixup_by_path(blob, dspi2_path, "status", "okay", sizeof("okay"), 1); - } + else + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); } #endif -- 2.9.5

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[PATCH v2] drivers: net: fsl_enetc: Pass on primary MAC address to Linux
by Alex Marginean 27 Jan '20

27 Jan '20

Passes on the primary address used by u-boot to Linux. The code does a DT fix-up for ENETC PFs and sets the primary MAC address in IERB. The address in IERB is restored on ENETC PCI functions at FLR. Signed-off-by: Alex Marginean <alexandru.marginean(a)nxp.com> --- The code is called fom ft_board_setup in board/freescale/ls1028a/ls1028a.c mostly for consistency with other LS parts. I'm open to suggestions though. Changes in v2: - fixed warning for fdt_fixup_enetc_mac being implicitly declared board/freescale/ls1028a/ls1028a.c | 5 +++ drivers/net/fsl_enetc.c | 65 ++++++++++++++++++++++++++++++- drivers/net/fsl_enetc.h | 3 ++ 3 files changed, 72 insertions(+), 1 deletion(-) diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index a9606b8865..1a82c95402 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -25,6 +25,7 @@ #include <fdtdec.h> #include <miiphy.h> #include "../common/qixis.h" +#include "../drivers/net/fsl_enetc.h" DECLARE_GLOBAL_DATA_PTR; @@ -150,6 +151,10 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_icid(blob); +#ifdef CONFIG_FSL_ENETC + fdt_fixup_enetc_mac(blob); +#endif + return 0; } #endif diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 0ca7e838a8..3c043888db 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -14,6 +14,69 @@ #include "fsl_enetc.h" +#define ENETC_DRIVER_NAME "enetc_eth" + +/* + * sets the MAC address in IERB registers, this setting is persistent and + * carried over to Linux. + */ +static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn, + const u8 *enetaddr) +{ +#ifdef CONFIG_ARCH_LS1028A +/* + * LS1028A is the only part with IERB at this time and there are plans to change + * its structure, keep this LS1028A specific for now + */ +#define IERB_BASE 0x1f0800000ULL +#define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \ + + (n) * 4) + +static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; + + u16 lower = *(const u16 *)(enetaddr + 4); + u32 upper = *(const u32 *)enetaddr; + + if (ierb_fn_to_pf[devfn] < 0) + return; + + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); + out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); +#endif +} + +/* sets up primary MAC addresses in DT/IERB */ +void fdt_fixup_enetc_mac(void *blob) +{ + struct pci_child_platdata *ppdata; + struct eth_pdata *pdata; + struct udevice *dev; + struct uclass *uc; + char path[256]; + int offset; + int devfn; + + uclass_get(UCLASS_ETH, &uc); + uclass_foreach_dev(dev, uc) { + if (!dev->driver || !dev->driver->name || + strcmp(dev->driver->name, ENETC_DRIVER_NAME)) + continue; + + pdata = dev_get_platdata(dev); + ppdata = dev_get_parent_platdata(dev); + devfn = PCI_FUNC(ppdata->devfn); + + enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr); + + snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", + PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); + offset = fdt_path_offset(blob, path); + if (offset < 0) + continue; + fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); + } +} + /* * Bind the device: * - set a more explicit name on the interface @@ -583,7 +646,7 @@ static const struct eth_ops enetc_ops = { }; U_BOOT_DRIVER(eth_enetc) = { - .name = "enetc_eth", + .name = ENETC_DRIVER_NAME, .id = UCLASS_ETH, .bind = enetc_bind, .probe = enetc_probe, diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index 0bb4cdff47..e441891468 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -226,4 +226,7 @@ int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad, int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad, int reg, u16 val); +/* sets up primary MAC addresses in DT/IERB */ +void fdt_fixup_enetc_mac(void *blob); + #endif /* _ENETC_H */ -- 2.17.1

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[PATCH] board: lx2160aqds: Add support of new serdes protocols.
by Vikas Singh 27 Jan '20

27 Jan '20

Add 8_10_0, 21_2_0 and 10_12_3 seredes protocols. Add the IOSLOT and the mezzanine card mapping against each serdes protocol. Signed-off-by: Vikas Singh <vikas.singh(a)nxp.com> --- board/freescale/lx2160a/eth_lx2160aqds.c | 84 +++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 55e8a42..741cca7 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -75,6 +75,29 @@ struct serdes_phy_config { * This table has limited serdes protocol entries. It can be expanded as per * requirement. */ +/***************************************************************** + | SERDES_1 PROTOCOL | IO_SLOT | CARD | + ***************************************************************** + | 3 | IO_SLOT_1 | M11-USXGMII | + | 7 | IO_SLOT_1 | M11-USXGMII | + | | IO_SLOT_2 | M4-PCIE-SGMII | + | 8 | IO_SLOT_1 | M12-XFI | + | 10 | IO_SLOT_1 | M11-USXGMII | + | | IO_SLOT_2 | M12-XFI | + | 13 | IO_SLOT_1 | M8-100G | + | | IO_SLOT_2 | M8-100G | + | 14 | IO_SLOT_1 | M8-100G | + | 15 | IO_SLOT_1 | M13-25G | + | 17 | IO_SLOT_1 | M13-25G | + | 19 | IO_SLOT_1 | M11-USXGMII | + | | IO_SLOT_2 | M7-40G | + | | IO_SLOT_6 | M13-25G | + | 20 | IO_SLOT_1 | M7-40G | + | | IO_SLOT_2 | M7-40G | + | 21 | IO_SLOT_1 | M13-25G | + | | IO_SLOT_2 | M13-25G | + ***************************************************************** + */ static const struct serdes_phy_config serdes1_phy_config[] = { {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, EMI1, IO_SLOT_1}, @@ -101,6 +124,12 @@ static const struct serdes_phy_config serdes1_phy_config[] = { {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1}, EMI1, IO_SLOT_2} } }, {8, {} }, + {10, {{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1}, + EMI1, IO_SLOT_1} } }, {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, EMI1, IO_SLOT_1}, {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, @@ -132,13 +161,49 @@ static const struct serdes_phy_config serdes1_phy_config[] = { {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1}, EMI1, IO_SLOT_1}, {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1}, - EMI1, IO_SLOT_2} } } + EMI1, IO_SLOT_2} } }, + {21, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC9, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_2}, + {WRIOP1_DPMAC10, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_2} } } }; +/***************************************************************** + | SERDES_2 PROTOCOL | IO_SLOT | CARD | + ***************************************************************** + | 2 | IO_SLOT_7 | M4-PCIE-SGMII | + | | IO_SLOT_8 | M4-PCIE-SGMII | + | 3 | IO_SLOT_7 | M4-PCIE-SGMII | + | | IO_SLOT_8 | M4-PCIE-SGMII | + | 5 | IO_SLOT_7 | M4-PCIE-SGMII | + | 10 | IO_SLOT_7 | M4-PCIE-SGMII | + | | IO_SLOT_8 | M4-PCIE-SGMII | + | 11 | IO_SLOT_7 | M4-PCIE-SGMII | + | | IO_SLOT_8 | M4-PCIE-SGMII | + | 12 | IO_SLOT_7 | M4-PCIE-SGMII | + | | IO_SLOT_8 | M4-PCIE-SGMII | + ***************************************************************** + */ static const struct serdes_phy_config serdes2_phy_config[] = { {2, {} }, {3, {} }, {5, {} }, + {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } }, {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, EMI1, IO_SLOT_7}, {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, @@ -151,8 +216,25 @@ static const struct serdes_phy_config serdes2_phy_config[] = { EMI1, IO_SLOT_8}, {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1}, EMI1, IO_SLOT_8} } }, + {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } } }; +/***************************************************************** + | SERDES_3 PROTOCOL | IO_SLOT | CARD | + ***************************************************************** + | 2 | IO_SLOT_5 | M4-PCIE-SGMII | + | | IO_SLOT_6 | M4-PCIE-SGMII | + | 3 | IO_SLOT_5 | M4-PCIE-SGMII | + | | IO_SLOT_6 | M4-PCIE-SGMII | + ***************************************************************** + */ static const struct serdes_phy_config serdes3_phy_config[] = { {2, {} }, {3, {} } -- 2.7.4

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[PATCH v4 0/4] Enablement of PCIe controller for lx2160a rev2
by Wasim Khan 27 Jan '20

27 Jan '20

lx2160a rev1 PCIe controller uses pcie_layerscape_gen4 driver and lx2160a rev2 PCIe controller uses pcie_layerscape driver. This patch set enables support for lx2160a rev2 and uses pcie_layerscape or pcie_layerscape_gen4 driver based on SoC. Also organize the device tree fixup in common, layerscape and layerscape_gen4 specific code. Some patches from this patch series are already accepted. Changes in v4: 1-Fixup compilation warnings faced with pcie_layerscape_fixup_common.c file 2-Updated NXP copyright 3-remove num-lanes fixup Changes in v3: 1-Updated patch subject and description based on Priyanka Jain review comments 2-fix compilation errors with lx2160aqds_tfa_SECURE_BOOT_defconfig and lx2160ardb_tfa_SECURE_BOOT_defconfig 3-Enabled CONFIG_OF_BOARD_FIXUP for lx2160aqds_tfa_SECURE_BOOT_defconfig and lx2160ardb_tfa_SECURE_BOOT_defconfig Changes in v2: Updated patch subject and description based on Priyanka Jain Wasim Khan (4): pci: layerscape: Common device tree fixup for NXP SoCs pci: layerscape: Move streamId allocation to common device tree fixup pci: layerscape: device tree fixup based on SoC and configs: lx2160a: enable CONFIG_OF_BOARD_FIXUP for SECURE_BOOT defconfig configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 2 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 2 + configs/lx2160ardb_tfa_defconfig | 1 + drivers/pci/Makefile | 5 +- drivers/pci/pcie_layerscape_fixup.c | 23 ++--- drivers/pci/pcie_layerscape_fixup_common.c | 124 +++++++++++++++++++++++++++ drivers/pci/pcie_layerscape_fixup_common.h | 22 +++++ drivers/pci/pcie_layerscape_gen4_fixup.c | 24 ++---- 9 files changed, 170 insertions(+), 34 deletions(-) create mode 100644 drivers/pci/pcie_layerscape_fixup_common.c create mode 100644 drivers/pci/pcie_layerscape_fixup_common.h -- 2.7.4

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[PATCH] armv8: ls1012a: Make USB masters snoopable
by Ran Wang 27 Jan '20

27 Jan '20

Program register bit of SCFG_SNPCNFGCR_USBRDSNP and SCFG_SNPCNFGCR_USBWRSNP to drive USB read/write snoop signal on LS1012A. Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ac75c58..e5090d2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -645,6 +645,11 @@ void fsl_lsch2_early_init_f(void) SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | SCFG_SNPCNFGCR_SATAWRSNP); +#elif defined(CONFIG_ARCH_LS1012A) + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); #else setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | -- 2.7.4

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[PATCH v2 1/2] drivers: net: fsl_enetc: use write_hwaddr()
by Michael Walle 27 Jan '20

27 Jan '20

Intead of setting the MAC address in enetc_start() use the proper write_hwaddr(). U-Boot takes care of the random MAC address, too. Signed-off-by: Michael Walle <michael(a)walle.cc> Signed-off-by: Alex Marginean <alexandru.marginean(a)nxp.com> --- changes since v1: - none, but added a second patch which also handles the ls1028a drivers/net/fsl_enetc.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 02c1ee70d9..52aae61fa9 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -267,14 +267,19 @@ static int enetc_remove(struct udevice *dev) return 0; } -/* ENETC Port MAC address registers, accepts big-endian format */ -static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr) +static int enetc_write_hwaddr(struct udevice *dev) { + struct eth_pdata *plat = dev_get_platdata(dev); + struct enetc_priv *priv = dev_get_priv(dev); + u8 *addr = plat->enetaddr; + u16 lower = *(const u16 *)(addr + 4); u32 upper = *(const u32 *)addr; enetc_write_port(priv, ENETC_PSIPMAR0, upper); enetc_write_port(priv, ENETC_PSIPMAR1, lower); + + return 0; } /* Configure port parameters (# of rings, frame size, enable port) */ @@ -405,7 +410,6 @@ static void enetc_setup_rx_bdr(struct udevice *dev) */ static int enetc_start(struct udevice *dev) { - struct eth_pdata *plat = dev_get_platdata(dev); struct enetc_priv *priv = dev_get_priv(dev); /* reset and enable the PCI device */ @@ -413,12 +417,6 @@ static int enetc_start(struct udevice *dev) dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - if (!is_valid_ethaddr(plat->enetaddr)) { - enetc_dbg(dev, "invalid MAC address, generate random ...\n"); - net_random_ethaddr(plat->enetaddr); - } - enetc_set_primary_mac_addr(priv, plat->enetaddr); - enetc_enable_si_port(priv); /* setup Tx/Rx buffer descriptors */ @@ -548,6 +546,7 @@ static const struct eth_ops enetc_ops = { .send = enetc_send, .recv = enetc_recv, .stop = enetc_stop, + .write_hwaddr = enetc_write_hwaddr, }; U_BOOT_DRIVER(eth_enetc) = { -- 2.20.1

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[PATCH v3] board: ls1046afwry: Disable sgmii support
by Pramod Kumar 27 Jan '20

27 Jan '20

LS1046A SoC serdes protocol 0x3040 supports both sgmi and qsgmii, however ls1046afrwy supports only QSGMI on board. Disable unsupported sgmii on board. Signed-off-by: Pramod Kumar <pramod.kumar_1(a)nxp.com> --- Changes in v2: - Incorporated review comment Changes in v3: - incorporated review comment for commit message board/freescale/ls1046afrwy/eth.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c index 9f8bd92..d38e4d7 100644 --- a/board/freescale/ls1046afrwy/eth.c +++ b/board/freescale/ls1046afrwy/eth.c @@ -53,6 +53,8 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(FM1_DTSEC10, dev); fm_info_set_mdio(FM1_DTSEC1, dev); + fm_disable_port(FM1_DTSEC9); + cpu_eth_init(bis); #endif -- 2.7.4

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[PATCH 0/2] pci: layerscape: Fix the BARs disable function in RC mode
by Z.q. Hou 27 Jan '20

27 Jan '20

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> The Expansion ROM BAR is not disabled by clearing the BAR_EN bit in current code, fix it. Add disabling of BARs of PCIe controller with SRIOV feature. Hou Zhiqiang (2): pci: layerscape: Fix the disabling of Expansion ROM BAR pci: layerscape: Fix the BARs disable function drivers/pci/pcie_layerscape.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) -- 2.17.1

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[RESEND v2 0/2] spi: cadence-qspi: Move to spi-mem APIs
by Vignesh Raghavendra 27 Jan '20

27 Jan '20

First patch moves driver over to spi-mem framework and implement spi_mem_ops. This is require to support more SPI Flash opcodes like SFDP parsing etc. Series is in prepartion to add Octal mode for support for the same driver to support OSPI version of the controller. Second patch adds DAC mode that provide memory mapped access to flash. This greatly increases the read throughput. Tested with mt25qu512 flash and s25fl512 flash Resend v2: Rebase onto the latest master (no functional change) Vignesh Raghavendra (2): spi: cadence_qspi: Move to spi-mem framework spi: cadence-qspi: Add direct mode support drivers/spi/cadence_qspi.c | 148 +++++++++++--------------- drivers/spi/cadence_qspi.h | 24 +++-- drivers/spi/cadence_qspi_apb.c | 185 ++++++++++++++++----------------- 3 files changed, 164 insertions(+), 193 deletions(-) -- 2.25.0

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[PATCH v2 0/3] Ethernet support for Raspberry Pi 4
by Andre Przywara 27 Jan '20

27 Jan '20

This series adds Ethernet support for the Raspberry Pi 4. The SoC includes a "Broadcom Genet v5 MAC" IP, connected as a proper platform device (no USB anymore!). Patch 1 provides a driver for that. There does not seem to be publicly available documentation, so this is based on the Linux driver, but stripped down to just provide what U-Boot needs. Patch 2 fixes up the RPi4 memory map to accommodate the MMIO area the MAC lives in, while patch 3 enables it in the respective defconfigs. This version addresses the comments by the diligent reviewers and testers, for a changelog see below. To see the individual changes as patches, refer to [1]. Please have a look and test it, I hope this helps to simplify development, as you spare the SD card and its slot from heavy swapping. I dropped the Tested-by's, as there were changes in the code. Happy to reapply them when people confirm that it still works for them. Cheers, Andre. [1] https://github.com/apritzel/u-boot/commits/rpi4-eth-v2 Changelog v1 ... v2: - use native endianess functions when accessing MMIO registers - use dev_* DM wrappers for accessing devicetree data - round base and length for flush_dcache_range, plus a comment - check and round length for invalidate_cache_range - support RGMII_RXID PHY mode, to support mainline .dtb Amit Singh Tomar (3): net: Add support for Broadcom GENETv5 Ethernet controller rpi4: Update memory map to accommodate scb devices rpi4: Enable GENET Ethernet controller arch/arm/mach-bcm283x/init.c | 6 +- configs/rpi_4_32b_defconfig | 2 + configs/rpi_4_defconfig | 2 + configs/rpi_arm64_defconfig | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 738 insertions(+), 3 deletions(-) create mode 100644 drivers/net/bcmgenet.c -- 2.14.5

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