January 2020 - U-Boot

[U-Boot] [PATCH v2 00/16] Add Intel Stratix 10 SoC support
by Ley Foon Tan 11 Jun '20

11 Jun '20

This is 2nd version of patchset to adds support for Intel Stratix 10 SoC. This patchset is work on top of patchset in [1]. Changes: - update base addresses header - use reset framework for periperhals (16550 UART, MMC, EMAC) - change to use serial DM driver - move bridge command to misc common driver and reuse for other platforms - rework board_init_f() in SPL - update S10 dts and dtsi - Mailbox: - change to use register offset to access register instead of register structure - rename function with __xxx prefix - DDR: - rework DDR driver - change to use register offset to access register instead of register structure - remove union bitwise structure - use wait_for_bit to poll Patchset history: [v1]: https://patchwork.ozlabs.org/cover/900499/ [1]: https://patchwork.ozlabs.org/cover/910018/ Ley Foon Tan (16): arm: socfpga: stratix10: Add watchdog and firewall base addresses arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch arm: socfpga: misc: Move bridge command to misc common arm: socfpga: stratix10: Add misc support for Stratix10 SoC arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC arm: socfpga: stratix10: Add MMU support for Stratix10 SoC arm: socfpga: Restructure the SPL file arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC arm: socfpga: stratix10: Add timer support for Stratix10 SoC ddr: altera: stratix10: Add DDR support for Stratix10 SoC board: altera: stratix10: Add socdk board support for Stratix10 SoC arm: dts: socfpga: stratix10: update dtsi and dts arm: socfpga: stratix10: Enable Stratix10 SoC build arch/arm/Kconfig | 9 +- arch/arm/dts/socfpga_stratix10.dtsi | 22 +- arch/arm/dts/socfpga_stratix10_socdk.dts | 3 + arch/arm/mach-socfpga/Kconfig | 16 + arch/arm/mach-socfpga/Makefile | 23 +- arch/arm/mach-socfpga/clock_manager.c | 4 +- arch/arm/mach-socfpga/clock_manager_s10.c | 380 +++++++++++++++++++ arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 11 + arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 + .../mach-socfpga/include/mach/clock_manager_s10.h | 210 +++++++++++ arch/arm/mach-socfpga/include/mach/firewall_s10.h | 120 ++++++ arch/arm/mach-socfpga/include/mach/handoff_s10.h | 34 ++ arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 144 ++++++++ arch/arm/mach-socfpga/include/mach/misc.h | 2 + arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 + .../mach-socfpga/include/mach/reset_manager_s10.h | 116 ++++++ arch/arm/mach-socfpga/include/mach/sdram_s10.h | 183 +++++++++ .../arm/mach-socfpga/include/mach/system_manager.h | 5 +- .../mach-socfpga/include/mach/system_manager_s10.h | 176 +++++++++ arch/arm/mach-socfpga/mailbox_s10.c | 380 +++++++++++++++++++ arch/arm/mach-socfpga/misc.c | 34 ++ arch/arm/mach-socfpga/misc_gen5.c | 26 +-- arch/arm/mach-socfpga/misc_s10.c | 133 +++++++ arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 ++++ arch/arm/mach-socfpga/reset_manager.c | 13 + arch/arm/mach-socfpga/reset_manager_s10.c | 140 +++++++ arch/arm/mach-socfpga/spl_a10.c | 105 ++++++ arch/arm/mach-socfpga/{spl.c => spl_gen5.c} | 57 +--- arch/arm/mach-socfpga/spl_s10.c | 199 ++++++++++ arch/arm/mach-socfpga/system_manager_s10.c | 91 +++++ arch/arm/mach-socfpga/timer_s10.c | 26 ++ arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 +++ arch/arm/mach-socfpga/wrap_pll_config_s10.c | 59 +++ board/altera/stratix10-socdk/MAINTAINERS | 7 + board/altera/stratix10-socdk/Makefile | 7 + board/altera/stratix10-socdk/socfpga.c | 7 + configs/socfpga_stratix10_defconfig | 58 +++ drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_s10.c | 388 ++++++++++++++++++++ include/configs/socfpga_stratix10_socdk.h | 222 +++++++++++ 40 files changed, 3459 insertions(+), 83 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c create mode 100644 arch/arm/mach-socfpga/misc_s10.c create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c create mode 100644 arch/arm/mach-socfpga/spl_a10.c rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (82%) create mode 100644 arch/arm/mach-socfpga/spl_s10.c create mode 100644 arch/arm/mach-socfpga/system_manager_s10.c create mode 100644 arch/arm/mach-socfpga/timer_s10.c create mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c create mode 100644 board/altera/stratix10-socdk/MAINTAINERS create mode 100644 board/altera/stratix10-socdk/Makefile create mode 100644 board/altera/stratix10-socdk/socfpga.c create mode 100644 configs/socfpga_stratix10_defconfig create mode 100644 drivers/ddr/altera/sdram_s10.c create mode 100644 include/configs/socfpga_stratix10_socdk.h

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[PATCH 1/2] ARM: at91: Enable SPL_SEPARATE_BSS by default
by Gregory CLEMENT 05 Jun '20

05 Jun '20

According to the linker script for both armv7 and arm926ejs based SoC, BSS section was all the time separated for SPL but this symbol was only enabled on some boards. However, it is necessary to have it enabled for OF_SEPARATE configuration where DTB is appended to u-boot with DTB. Signed-off-by: Gregory CLEMENT <gregory.clement(a)bootlin.com> --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9dab073ea..e558024652 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -492,6 +492,7 @@ choice config ARCH_AT91 bool "Atmel AT91" select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB + select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" -- 2.24.1

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[U-Boot] [PATCH v1 0/3] reset: Add a managed API
by Jean-Jacques Hiblot 31 May '20

31 May '20

This is the 3rd of a few series, the goal of which is to facilitate porting drivers from the linux kernel. Most of the series will be about adding managed API to existing infrastructure (GPIO, reset, phy,...) This particular series is about reset controllers. It adds a managed API, close to that of linux. The main difference is that bulk and reset_ctl are handled with different functions. Jean-Jacques Hiblot (3): drivers: reset: Handle gracefully NULL pointers drivers: reset: Add a managed API to get reset controllers from the DT test: reset: Add tests for the managed API arch/sandbox/include/asm/reset.h | 1 + drivers/reset/reset-uclass.c | 146 +++++++++++++++++++++++++---- drivers/reset/sandbox-reset-test.c | 50 ++++++++-- drivers/reset/sandbox-reset.c | 19 ++++ include/reset.h | 135 +++++++++++++++++++++++++- test/dm/reset.c | 59 ++++++++++++ 6 files changed, 387 insertions(+), 23 deletions(-) -- 2.17.1

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[U-Boot] [PATCH 0/2] misc: i2c_eeprom: add paritioning and size query
by Robert Beckett 28 May '20

28 May '20

Add ability to specify paritions for eeprom in device tree, and query eeprom device sizes. Each partition creates a child device, allowing board code to find the eeprom parition by name. Robert Beckett (2): misc: i2c_eeprom: add fixed partitions support misc: i2c_eeprom: add size query drivers/misc/i2c_eeprom.c | 243 +++++++++++++++++++++++++++++++++++--- include/i2c_eeprom.h | 12 ++ 2 files changed, 236 insertions(+), 19 deletions(-) -- 2.20.1

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[Patch v4] net: pfe_eth: Use spi_flash_read API to access flash memory
by Kuldeep Singh 28 May '20

28 May '20

Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- v4: -Return -ENODEV if flash probe fails v3: -Replace ret with 0 if flash probe fails v2: -Add return error code -Changes in displayed error log drivers/net/pfe_eth/pfe_firmware.c | 45 +++++++++++++++++++++++++++++++++++++- include/configs/ls1012a_common.h | 5 ++++- 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index e4563f1..27ae8ae 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -12,13 +12,14 @@ #include <net/pfe_eth/pfe_eth.h> #include <net/pfe_eth/pfe_firmware.h> +#include <spi_flash.h> #ifdef CONFIG_CHAIN_OF_TRUST #include <fsl_validate.h> #endif #define PFE_FIRMWARE_FIT_CNF_NAME "config@1" -static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR; +static const void *pfe_fit_addr; /* * PFE elf firmware loader. @@ -159,6 +160,44 @@ static int pfe_fit_check(void) return ret; } +int pfe_spi_flash_init(void) +{ + struct spi_flash *pfe_flash; + int ret = 0; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + /* speed and mode will be read from DT */ + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, 0, 0, &new); + + pfe_flash = dev_get_uclass_priv(new); +#else + pfe_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE); +#endif + if (!pfe_flash) { + printf("SF: probe for pfe failed\n"); + return -ENODEV; + } + + ret = spi_flash_read(pfe_flash, + CONFIG_SYS_LS_PFE_FW_ADDR, + CONFIG_SYS_QE_FMAN_FW_LENGTH, + addr); + if (ret) + printf("SF: read for pfe failed\n"); + + pfe_fit_addr = addr; + spi_flash_free(pfe_flash); + + return ret; +} + /* * PFE firmware initialization. * Loads different firmware files from FIT image. @@ -183,6 +222,10 @@ int pfe_firmware_init(void) int ret = 0; int fw_count; + ret = pfe_spi_flash_init(); + if (ret) + goto err; + ret = pfe_fit_check(); if (ret) goto err; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 2579e2f..cbc5bff 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -36,9 +36,12 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +/* PFE */ +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 + /*SPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT) -#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_SPI_FLASH_SPANSION #define CONFIG_FSL_SPI_INTERFACE #define CONFIG_SF_DATAFLASH -- 2.7.4

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[U-Boot] u-boot Marvell ethernet switch development
by Dennis Jacobs 26 May '20

26 May '20

Dear U-boot mailing list, Its the first time I make use of this U-boot mailing list. I am here for a problem I am having recently with u-boot which is part of my graduation project. I am developing firmware for a Marvell Ethernet switch chip (98DX3336) on the RD-XC3-24G4XG-B (Marvell Ethernet switch). Marvell has provided me with U-boot binary files for UART, SPI etc. I managed to load the U-boot UART binary file trough the UART interface. Showing: [cid:image003.png@01D3E22C.D21A6560] Ok so that is good... now I need to set up my own u-boot environment to add some changes. So I did. I Downloaded u-boot 2013.01 and added marvell configurations. I was able to compile and load the U-boot Uart binary trough the UART interface. The terminal is showing the following: [cid:image004.png@01D3E22D.C73E7040] So ok its loads! But now... I can not perform any commands. All commands are Unknown... So what I did was checking the configurations and I found out that I have set the CMD configurations. Like CMD_NET etc etc [cid:image005.png@01D3E22E.7D8A6070] Anny one that could help me here? I would really appreciate it. I am struggling with this problem for almost 2 full days now. Actions I have been taken - Tested if help command was realy executed and no other invisible fragments where added. - Tested the compilation with 7 different armv7-marvell cross compilers Left binary is the working one the second binary is mine. It only differs 26 bytes. I noticed that a different cross compiler also changes the size. Sometime more sometimes less. All of the binarys I compiled where executing correctly but not reacting on anny commands [cid:image006.png@01D3E22F.61EE8C00] Please help me. Kind regards, Dennis Jacobs Designer [Prodrive B.V.]<http://www.prodrive-technologies.com/> Mobile +31 62 57 28 194 Phone +31 40 26 76 200 www.prodrive-technologies.com<http://www.prodrive-technologies.com> [cid:image002.png@01D3E22B.A33384D0] Disclaimer: The content of this e-mail is intended solely for the use of the Individual or entity to whom it is addressed. If you have received this communication in error, be aware that forwarding it, copying it, or in any way disclosing its content to any other person, is strictly prohibited. If you have received this communication in error, please notify the author by replying to this e-mail immediately.

3 2

[U-Boot] [ANN] Monthly developer call
by Tom Rini 21 May '20

21 May '20

Hey all, So as I mentioned back in December[1], I was thinking of doing a recurring community conference call. I've gone ahead and scheduled one now with Zoom (https://zoom.us/) as they work well enough with Linux as a host. For now, the time is 4PM UTC, which is 11AM US Eastern, 8AM US Pacific. The meeting URL is: https://zoom.us/j/203089062 (and so the meeting number is 203089062) For dial-in: +1 (646) 876-9923 and world-wide local dial-in numbers are found on: https://zoom.us/u/acnOQeSN Since we don't do attachments, we do inline patches, what follows is the ics file for the meeting, to import to your favorite (or, least-disliked) calendaring solution: BEGIN:VCALENDAR PRODID:-//zoom.us//iCalendar Event//EN VERSION:2.0 CALSCALE:GREGORIAN METHOD:PUBLISH CLASS:PUBLIC BEGIN:VTIMEZONE TZID:America/New_York TZURL:http://tzurl.org/zoneinfo-outlook/America/New_York X-LIC-LOCATION:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20190211T165035Z DTSTART;TZID=America/New_York:20190218T110000 DTEND;TZID=America/New_York:20190218T120000 SUMMARY:U-Boot community meeting RRULE:FREQ=MONTHLY;WKST=SU;UNTIL=20191216T170000;INTERVAL=1;BYDAY=3MO UID:ZOOM203089062 TZID:America/New_York DESCRIPTION:Tom Rini is inviting you to a scheduled Zoom meeting.\n\nJoin Zoom Meeting\nhttps://zoom.us/j/203089062\n\nOne tap mobile\n+164687699 23\,\,203089062# US (New York)\n+16699006833\,\,203089062# US (San Jose) \n\nDial by your location\n +1 646 876 9923 US (New York)\n +1 669 900 6833 US (San Jose)\nMeeting ID: 203 089 062\nFind your loca l number: https://zoom.us/u/acnOQeSNf\n LOCATION:https://zoom.us/j/203089062 BEGIN:VALARM TRIGGER:-PT10M ACTION:DISPLAY DESCRIPTION:Reminder END:VALARM END:VEVENT END:VCALENDAR [1]: https://lists.denx.de/pipermail/u-boot/2018-December/350346.html -- Tom

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[U-Boot] [PPC] Internet connection on qemu-ppce500
by vnktux 12 May '20

12 May '20

Hello guys, I am running an image of U-boot 2018.09 in qemu 3.0, the goal would be to load an OS-9 rom file from tftp. The problem is that I can't manage to have an Internet connection in U-boot. No matter how I run the image I always have Net: "No Ethernet found". I run qemu 3.0 with the following command: > qemu-system-ppc -cpu e500v2 -M ppce500 -nographic -kernel ~/u-boot -net nic -net tap,ifname=tap0,script=no I tried to use different -net options in qemu but the problem is always the same. And from the u-boot source code I have edited the board file qemu-ppce500.c in order to have a few ENV variables (since I can't save any env variables from the running U-boot in qemu). > ethact=eTSEC1 > ethprime=eTSEC1 > ethaddr=192.168.10.40 > netmask=255.255.254.0 > serverip=192.168.10.2 > gatewayip=192.168.10.254 The image is compiled using of course: qemu-ppce500_defconfig. What am I doing wrong? Is it even possible to initialize the Ethernet port? Thanks in advance, Vincenzo Sent with [ProtonMail](https://protonmail.com) Secure Email.

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[U-Boot] [PATCH v6 1/4] dm: spi: Convert Freescale ESPI driver to driver model
by Xiaowei Bao 12 May '20

12 May '20

From: Chuanhua Han <chuanhua.han(a)nxp.com> Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems: ===================== WARNING ====================== This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Chuanhua Han <chuanhua.han(a)nxp.com> Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- depends on: https://patchwork.ozlabs.org/cover/1146494/ Changes in v6: - Change #ifndef CONFIG_DM_SPI to #if !CONFIG_IS_ENABLED(DM_SPI). Changes in v5: - Modify the function spi_cs_activate to fsl_spi_cs_activate. - Move cs to the parameter of the fsl_spi_cs_activate function. Changes in v4: - Update copyright information. - Move the fsl_espi_platdata data structure to the include/dm/platform_data/. - Merge the contents of the fsl_espi_priv structure into the fsl_spi_slave structure. - Implement the fsl_espi_set_speed function. - Implement the fsl_espi_set_mode function. - Implement the espi_release_bus function. - Remove unwanted fsl_espi_bind functions. - Implement the fsl_espi_child_pre_probe function as needed. - Use #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA). Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - The fsl_espi driver support both OF_CONTROL and PLATDATA. drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- include/dm/platform_data/fsl_espi.h | 16 ++ 2 files changed, 337 insertions(+), 124 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7444ae1..fd5ac97 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,18 +3,25 @@ * eSPI controller driver. * * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) + * Chuanhua Han (chuanhua.han(a)nxp.com) */ #include <common.h> - #include <malloc.h> #include <spi.h> #include <asm/immap_85xx.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <dm/platform_data/fsl_espi.h> struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi; + u32 speed_hz; + unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout; @@ -28,6 +35,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL +/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000 + #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32 @@ -62,116 +72,27 @@ struct fsl_spi_slave { #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_spi_slave *fsl; - sys_info_t sysinfo; - unsigned long spibrg = 0; - unsigned long spi_freq = 0; - unsigned char pm = 0; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); - if (!fsl) - return NULL; - - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - fsl->mode = mode; - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; - - /* Set eSPI BRG clock source */ - get_sys_info(&sysinfo); - spibrg = sysinfo.freq_systembus / 2; - fsl->div16 = 0; - if ((spibrg / max_hz) > 32) { - fsl->div16 = ESPI_CSMODE_DIV16; - pm = spibrg / (max_hz * 16 * 2); - if (pm > 16) { - pm = 16; - debug("Requested speed is too low: %d Hz, %ld Hz " - "is used.\n", max_hz, spibrg / (32 * 16)); - } - } else - pm = spibrg / (max_hz * 2); - if (pm) - pm--; - fsl->pm = pm; - - if (fsl->div16) - spi_freq = spibrg / ((pm + 1) * 2 * 16); - else - spi_freq = spibrg / ((pm + 1) * 2); - - /* set tx_timeout to 10 times of one espi FIFO entry go out */ - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT - * 10), spi_freq); - - return &fsl->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - free(fsl); -} - -int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi; - unsigned char pm = fsl->pm; - unsigned int cs = slave->cs; - unsigned int mode = fsl->mode; - unsigned int div16 = fsl->div16; - int i; - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); - - /* Enable eSPI interface */ - out_be32(&espi->mode, ESPI_MODE_RXTHR(3) - | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); - - out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ - out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ - - /* Init CS mode interface */ - for (i = 0; i < ESPI_MAX_CS_NUM; i++) - out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); - - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & - ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 - | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK - | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); - - /* Set eSPI BRG clock source */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_PM(pm) | div16); - - /* Set eSPI mode */ - if (mode & SPI_CPHA) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CP_BEGIN_EDGCLK); - if (mode & SPI_CPOL) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CI_INACTIVEHIGH); - - /* Character bit order: msb first */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_REV_MSB_FIRST); - - /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_LEN(7)); + unsigned int com = 0; + size_t data_len = fsl->data_len; - return 0; + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); } -void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) { + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi; + /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); } static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -204,7 +125,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) debug("***spi_xfer:...Tx timeout! event = %08x\n", event); } -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, + unsigned int bytes) { ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -236,10 +158,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) +void espi_release_bus(struct fsl_spi_slave *fsl) { - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + /* Disable the SPI hardware */ + out_be32(&fsl->espi->mode, + in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); +} + +int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL; @@ -258,13 +187,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN: - cmd_len = fsl->cmd_len = data_len; + cmd_len = data_len; + fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) { - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); @@ -304,7 +234,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; - spi_cs_activate(slave); + fsl_spi_cs_activate(slave, cs); /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); @@ -347,37 +277,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, *(int *)buffer += tran_len; } } - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); } free(buffer); return 0; } +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned char pm = fsl->pm; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); +} + +void espi_setup_slave(struct fsl_spi_slave *fsl) +{ + unsigned int max_hz; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned long spi_freq = 0; + unsigned char pm = 0; + + max_hz = fsl->speed_hz; + + get_sys_info(&sysinfo); + spibrg = sysinfo.freq_systembus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("max_hz is too low: %d Hz, %ld Hz is used.\n", + max_hz, spibrg / (32 * 16)); + } + } else { + pm = spibrg / (max_hz * 2); + } + if (pm) + pm--; + fsl->pm = pm; + + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq);/* Set eSPI BRG clock source */ +} + +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; } -void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_spi_slave *fsl; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); + if (!fsl) + return NULL; + + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = max_hz; + + espi_setup_slave(fsl); + + return &fsl->slave; +} + +void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int com = 0; - size_t data_len = fsl->data_len; - com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); - com |= ESPI_COM_CS(slave->cs); - com |= ESPI_COM_TRANLEN(data_len - 1); - out_be32(&espi->com, com); + free(fsl); } -void spi_cs_deactivate(struct spi_slave *slave) +int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - /* clear the RXCNT and TXCNT */ - out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); - out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); + espi_claim_bus(fsl, slave->cs); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + + espi_release_bus(fsl); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave; + + return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); +} +#else +static void __espi_set_speed(struct fsl_spi_slave *fsl) +{ + espi_setup_slave(fsl); + + /* Set eSPI BRG clock source */ + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); +} + +static void __espi_set_mode(struct fsl_spi_slave *fsl) +{ + /* Set eSPI mode */ + if (fsl->mode & SPI_CPHA) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (fsl->mode & SPI_CPOL) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); +} + +static int fsl_espi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_claim_bus(fsl, fsl->cs); + + return 0; +} + +static int fsl_espi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_release_bus(fsl); + + return 0; +} + +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); +} + +static int fsl_espi_set_speed(struct udevice *bus, uint speed) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s speed %u\n", __func__, speed); + fsl->speed_hz = speed; + + __espi_set_speed(fsl); + + return 0; +} + +static int fsl_espi_set_mode(struct udevice *bus, uint mode) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + fsl->mode = mode; + + __espi_set_mode(fsl); + + return 0; } + +static int fsl_espi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s cs %u\n", __func__, slave_plat->cs); + fsl->cs = slave_plat->cs; + + return 0; +} + +static int fsl_espi_probe(struct udevice *bus) +{ + struct fsl_espi_platdata *plat = dev_get_platdata(bus); + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr); + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = plat->speed_hz; + + debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); + + return 0; +} + +static const struct dm_spi_ops fsl_espi_ops = { + .claim_bus = fsl_espi_claim_bus, + .release_bus = fsl_espi_release_bus, + .xfer = fsl_espi_xfer, + .set_speed = fsl_espi_set_speed, + .set_mode = fsl_espi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) +{ + fdt_addr_t addr; + struct fsl_espi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + addr = dev_read_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs_addr = lower_32_bits(addr); + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_ESPI_DEFAULT_SCK_FREQ); + + debug("ESPI: regs=%p, max-frequency=%d\n", + &plat->regs_addr, plat->speed_hz); + + return 0; +} + +static const struct udevice_id fsl_espi_ids[] = { + { .compatible = "fsl,mpc8536-espi" }, + { } +}; +#endif + +U_BOOT_DRIVER(fsl_espi) = { + .name = "fsl_espi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = fsl_espi_ids, + .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, +#endif + .ops = &fsl_espi_ops, + .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_spi_slave), + .probe = fsl_espi_probe, + .child_pre_probe = fsl_espi_child_pre_probe, +}; +#endif diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000..812933f --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_platdata { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */ -- 2.9.5

4 12

[U-Boot] [PATCH 00/29] Add the SPI DM support for PPC
by Xiaowei Bao 12 May '20

12 May '20

Add the SPI DM support for PPC. depends on: http://patchwork.ozlabs.org/project/uboot/list/?series=127282 Xiaowei Bao (29): dts: P1020: Add ESPI DT nodes dts: P1020RDB: Add ESPI slave device node configs: P1020RDB: Enable ESPI driver dts: P2020: Add ESPI DT nodes dts: P2020RDB: Add ESPI slave device node configs: P2020RDB: Enable ESPI driver dts: P2041: Add ESPI DT nodes dts: P2041RDB: Add ESPI slave device node configs: P2041RDB: Enable ESPI driver dts: P3041: Add ESPI DT nodes dts: P3041DS: Add ESPI slave device node configs: P3041DS: Enable ESPI driver dts: P4080: Add ESPI DT nodes dts: P4080DS: Add ESPI slave device node configs: P4080DS: Enable ESPI driver dts: P5040: Add ESPI DT nodes dts: P5040DS: Add ESPI slave device node configs: P5040DS: Enable ESPI driver dts: T102x: Add ESPI DT nodes dts: T1024RDB: Add ESPI slave device node configs: T1024RDB: Enable ESPI driver dts: T104x: Add ESPI DT nodes dts: T1042D4RDB: Add ESPI slave device node configs: T1042D4RDB: Enable ESPI driver dts: T2080RDB: Add ESPI slave device node configs: T2080RDB: Enable ESPI driver dts: T4240: Add ESPI DT nodes dts: T4240RDB: Add ESPI slave device node configs: T4240RDB: Enable ESPI driver arch/powerpc/dts/p1020-post.dtsi | 9 +++++++++ arch/powerpc/dts/p1020rdb-pc.dts | 15 +++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 15 +++++++++++++++ arch/powerpc/dts/p1020rdb-pd.dts | 15 +++++++++++++++ arch/powerpc/dts/p2020-post.dtsi | 9 +++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 15 +++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 15 +++++++++++++++ arch/powerpc/dts/p2041.dtsi | 9 +++++++++ arch/powerpc/dts/p2041rdb.dts | 14 ++++++++++++++ arch/powerpc/dts/p3041.dtsi | 9 +++++++++ arch/powerpc/dts/p3041ds.dts | 14 ++++++++++++++ arch/powerpc/dts/p4080.dtsi | 9 +++++++++ arch/powerpc/dts/p4080ds.dts | 14 ++++++++++++++ arch/powerpc/dts/p5040.dtsi | 9 +++++++++ arch/powerpc/dts/p5040ds.dts | 14 ++++++++++++++ arch/powerpc/dts/t1024rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t102x.dtsi | 9 +++++++++ arch/powerpc/dts/t1042d4rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t104x.dtsi | 9 +++++++++ arch/powerpc/dts/t2080rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t4240.dtsi | 9 +++++++++ arch/powerpc/dts/t4240rdb.dts | 15 +++++++++++++++ configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_defconfig | 2 ++ configs/P1020RDB-PC_NAND_defconfig | 2 ++ configs/P1020RDB-PC_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_defconfig | 2 ++ configs/P1020RDB-PD_NAND_defconfig | 2 ++ configs/P1020RDB-PD_SDCARD_defconfig | 2 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_defconfig | 2 ++ configs/P2020RDB-PC_NAND_defconfig | 2 ++ configs/P2020RDB-PC_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 2 ++ configs/P2041RDB_SDCARD_defconfig | 2 ++ configs/P2041RDB_SPIFLASH_defconfig | 2 ++ configs/P2041RDB_defconfig | 2 ++ configs/P3041DS_NAND_defconfig | 2 ++ configs/P3041DS_SDCARD_defconfig | 2 ++ configs/P3041DS_SPIFLASH_defconfig | 2 ++ configs/P3041DS_defconfig | 2 ++ configs/P4080DS_SDCARD_defconfig | 2 ++ configs/P4080DS_SPIFLASH_defconfig | 2 ++ configs/P4080DS_defconfig | 2 ++ configs/P5040DS_NAND_defconfig | 2 ++ configs/P5040DS_SDCARD_defconfig | 2 ++ configs/P5040DS_SPIFLASH_defconfig | 2 ++ configs/P5040DS_defconfig | 2 ++ configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ configs/T1042D4RDB_NAND_defconfig | 2 ++ configs/T1042D4RDB_SDCARD_defconfig | 2 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1042D4RDB_defconfig | 2 ++ configs/T2080RDB_NAND_defconfig | 2 ++ configs/T2080RDB_SDCARD_defconfig | 2 ++ configs/T2080RDB_SPIFLASH_defconfig | 2 ++ configs/T2080RDB_defconfig | 2 ++ configs/T4240RDB_SDCARD_defconfig | 2 ++ configs/T4240RDB_defconfig | 2 ++ 71 files changed, 370 insertions(+) -- 2.9.5

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