September 2019 - U-Boot

[U-Boot] [PATCH 0/9] efi_loader: rework bootefi/bootmgr
by AKASHI Takahiro 06 Jan '20

06 Jan '20

There are several reasons that I want to rework/refactor bootefi command as well as bootmgr: * Some previous commits on bootefi.c have made the code complicated and a bit hard to understand. * do_bootefi_exec() would better be implemented using load_image() along with start_image() to be aligned with UEFI interfaces. * Contrary to the other part, efi_selftest part of the code is unusual in terms of loading/execution path in do_bootefi(). * When we will support "secure boot" in the future, EFI Boot Manager is expected to be invoked as a standalone command without any arguments to mitigate security surfaces. In this patch set, Patch#1 to #7 are preparatory patches for patch#8. Patch#8 is a core part of reworking. Patch#9 is for standalone boot manager. # Please note that some patches, say patch#2 and #3, can be combined into one # but I intentionally keep them separated to clarify my intentions of changes. Issues: * It would be better off to change the semantics of efi_dp_from_name(). no chance to free loaded_image_info->load_options. (see patch #8) -Takahiro Akashi Changes in v1 (Apr 19, 2019) * Travis CI: https://travis-ci.org/t-akashi/u-boot/builds/521984187 * rebased on efi-2019-07 * delete already-merged patches * rework set_load_options() (patch#1 and #8) * fix compile/Travis CI errors (patch#2, #7 and #8) * rename do_boot_efi() to do_bootefi_image() (patch#7) * free file_path in do_bootefi_image() (patch#8) * use EFI_PRINT instead of debug() (patch#8) * remove improper warning messages (patch#8) Changes in RFC v3 (Apr 16, 2019) * rebased on v2019.04 * delete already-merged patches * add patch#2 for exporting root node * use correct/more appropriate return code (CMD_RET_xxx) (patch#3,5,7) * remove a message at starting an image in bootefi command, instead adding a debug message in efi_start_image() * use root node as a dummy parent handle when calling efi_start_image() * remove efi_unload_image() in bootefi command Changes in RFC v2 (Mar 27, 2019) * rebased on v2019.04-rc4 * use load_image API in do_bootmgr_load() * merge efi_install_fdt() and efi_process_fdt() * add EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL to image (patch#1) * lots of minor changes AKASHI Takahiro (9): cmd: bootefi: rework set_load_options() cmd: bootefi: carve out fdt handling from do_bootefi() cmd: bootefi: merge efi_install_fdt() and efi_process_fdt() cmd: bootefi: carve out efi_selftest code from do_bootefi() cmd: bootefi: move do_bootefi_bootmgr_exec() forward cmd: bootefi: carve out bootmgr code from do_bootefi() cmd: bootefi: carve out do_bootefi_image() from do_bootefi() efi_loader: rework bootmgr/bootefi using load_image API cmd: add efibootmgr command cmd/Kconfig | 8 + cmd/bootefi.c | 540 ++++++++++++++++++++++------------ include/efi_loader.h | 5 +- lib/efi_loader/efi_bootmgr.c | 43 +-- lib/efi_loader/efi_boottime.c | 2 + 5 files changed, 383 insertions(+), 215 deletions(-) -- 2.20.1

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[U-Boot] [PATCH 0/4] arm: mxs: mxs_set_gpmiclk
by Rasmus Villemoes 04 Jan '20

04 Jan '20

While trying to implement an mxs_set_gpmiclk() I stumbled on a few minor things. Rasmus Villemoes (4): arm: mxs: fix register definitions for clkctrl_gpmi and clkctrl_sspX arm: mxs: fix comments in arch_cpu_init to match the code arm: mxs: be more careful when enabling gpmi_clk arm: mxs: implement mxs_set_gpmiclk arch/arm/cpu/arm926ejs/mxs/clock.c | 41 +++++++++++++++++++ arch/arm/cpu/arm926ejs/mxs/mxs.c | 9 ++-- arch/arm/include/asm/arch-mxs/clock.h | 1 + .../include/asm/arch-mxs/regs-clkctrl-mx23.h | 6 ++- .../include/asm/arch-mxs/regs-clkctrl-mx28.h | 15 ++++--- 5 files changed, 62 insertions(+), 10 deletions(-) -- 2.20.1

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[U-Boot] [PATCH 00/26] Add and update drivers for MediaTek MT76x8 SoCs
by Weijie Gao 02 Jan '20

02 Jan '20

This patch series have the following changes: - Add pinctrl(both pinmux and pinconf) driver, reset controller driver and clock gating driver for mt7628. - Add mt7628 platform to mtk-sd driver. - Modify mt7628's ethernet & usb phy driver to take advantages from the new drivers. - Update mt7621-spi driver with a new transfer method. - Enable fifo, disable flow control, and enable non-DM implementation for mtk hsuart driver. - Enanble the new drivers for currently existed mt7628 boards. Weijie Gao (26): serial: serial_mtk: enable FIFO and disable flow control serial: serial_mtk: add non-DM version for SPL dts: mtmips: move uart property clock-frequency into mt7628an.dtsi dts: mtmips: enable high-speed UART support for mt7628 spi: mt7621-spi: remove data cache and rewrite its xfer function spi: mt7621-spi: restore default register value after each xfer pinctrl: add support for MediaTek MT7628 dts: mtmips: add pinctrl node for mt7628 dts: mtmips: add default pinctrl for uart nodes reset: add reset controller driver for MediaTek MIPS platform dts: mtmips: update reset controller node for mt7628 clk: add clock gating driver for MediaTek MIPS platform dts: mtmips: add gate clock node for mt7628 phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 part net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy reset net: mt7628-eth: remove phy link up detection net: mt7628-eth: free rx descriptor on receiving failure net: mt7628-eth: add support to isolate LAN/WAN ports dts: mtmips: enable eth port0 led function for all boards mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCs mmc: mtk-sd: add a dts property cd-active-high for builtin-cd mode dts: mtmips: add mmc related nodes for mt7628an.dtsi dts: mtmips: add default pinctrl for gardena-smart-gateway-mt7688 dts: mtmips: add default pinctrl to eth nodes for all boards configs: mtmips: change all boards to use mtk high-speed uart driver configs: mtmips: add necessary drivers for mtmips boards .../mips/dts/gardena-smart-gateway-mt7688.dts | 18 +- arch/mips/dts/linkit-smart-7688.dts | 15 +- arch/mips/dts/mt7628a.dtsi | 241 +++++++- ...gardena-smart-gateway-mt7688-ram_defconfig | 2 +- .../gardena-smart-gateway-mt7688_defconfig | 8 +- configs/linkit-smart-7688-ram_defconfig | 2 +- configs/linkit-smart-7688_defconfig | 8 +- drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-mtmips-cg.c | 63 ++ drivers/mmc/Kconfig | 2 +- drivers/mmc/mtk-sd.c | 32 +- drivers/net/mt7628-eth.c | 108 ++-- drivers/phy/Kconfig | 2 + drivers/phy/mt76x8-usb-phy.c | 225 +++++-- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/mtmips/Kconfig | 13 + drivers/pinctrl/mtmips/Makefile | 7 + drivers/pinctrl/mtmips/pinctrl-mt7628.c | 585 ++++++++++++++++++ .../pinctrl/mtmips/pinctrl-mtmips-common.c | 87 +++ .../pinctrl/mtmips/pinctrl-mtmips-common.h | 53 ++ drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-mtmips.c | 82 +++ drivers/serial/serial.c | 2 + drivers/serial/serial_mtk.c | 223 ++++++- drivers/spi/mt7621_spi.c | 227 ++++--- .../configs/gardena-smart-gateway-mt7688.h | 2 +- include/configs/linkit-smart-7688.h | 2 +- include/dt-bindings/clk/mt7628-clk.h | 31 + include/dt-bindings/reset/mt7628-reset.h | 36 ++ 32 files changed, 1795 insertions(+), 300 deletions(-) create mode 100644 drivers/clk/clk-mtmips-cg.c create mode 100644 drivers/pinctrl/mtmips/Kconfig create mode 100644 drivers/pinctrl/mtmips/Makefile create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7628.c create mode 100644 drivers/pinctrl/mtmips/pinctrl-mtmips-common.c create mode 100644 drivers/pinctrl/mtmips/pinctrl-mtmips-common.h create mode 100644 drivers/reset/reset-mtmips.c create mode 100644 include/dt-bindings/clk/mt7628-clk.h create mode 100644 include/dt-bindings/reset/mt7628-reset.h -- 2.17.1

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[U-Boot] [PATCH v2] spl: Introduce SPL_DM_GPIO Kconfig define
by Lukasz Majewski 27 Dec '19

27 Dec '19

This define indicates if DM_GPIO shall be supported in SPL. This allows proper operation of DM converted GPIO drivers in SPL, which use boards. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- Changes in v2: - Add dependency on DM_GPIO common/spl/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f467eca2be..e3df8efa7e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -452,6 +452,12 @@ config SPL_DMA_SUPPORT the CPU moving the data. Enable this option to build the drivers in drivers/dma as part of an SPL build. +config SPL_DM_GPIO + bool "Support Driver Model GPIO drivers" + depends on SPL_GPIO_SUPPORT && DM_GPIO + help + Enable support for Driver Model based GPIO drivers in SPL. + config SPL_DRIVERS_MISC_SUPPORT bool "Support misc drivers" help -- 2.20.1

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[U-Boot] SUNXI : CONFIG_VIDEO_SUNXI is never set
by Arjan van Vught 22 Dec '19

22 Dec '19

Version: u-boot-2018.09 This is a follow-up for : "SUNXI : setenv video-mode not working" Although I have added CONFIG_VIDEO_SUNXI=y in configs/orangepi_one_defconfig the source file sunxi_display.c is not compiled. Hence the setenv video-mode is not working ? Please advice. Many thanks in advance, Arjan http://www.orangepi-dmx.org/allwinner-h3

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[U-Boot] [PATCH 00/17] Add i.MX8MN support
by Peng Fan 17 Dec '19

17 Dec '19

This patchset is to support i.MX8MN This is a splitted patchset from http://u-boot.10912.n7.nabble.com/PATCH-00-52-Support-i-MX8MM-N-td374879.ht… with clk converted to ccf. i.MX8MN has similar architecture as i.MX8MM, but it supports romapi load and no HDMI. This patchset is developed based on i.MX8MM, and ddr4 fixes. Not expect this patchset be accpeted in this release cycle, preparing for next release. Peng Fan (17): imx: add i.MX8MN kconfig entry imx8mn: support get_cpu_rev imx8m: add clk support for i.MX8MN imx8mn: set BYPASS ID SWAP to avoid AXI bus errors imx: add i.MX8MN PE property imx8mn: add pin header imx: spl: use spl_board_boot_device for i.MX8MN imx: add rom api support imx: cpu: restrict get_boot_device imx8mn: add get_boot_device tools: imx8mimage: add ROM VERSION pinctrl: imx8m: support i.MX8MN tools: imx8m_image: support ddr4 firmware clk: imx: add i.MX8MN ccf driver imx8m: add i.MX8MN ddr4 image cfg file imx: add dtsi for i.MX8MN imx: add i.MX8MN DDR4 board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mm-evk.dts | 6 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 92 ++ arch/arm/dts/imx8mn-ddr4-evk.dts | 221 +++++ arch/arm/dts/imx8mn-pinfunc.h | 646 +++++++++++++ arch/arm/dts/imx8mn.dtsi | 712 ++++++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/arch-imx8m/clock.h | 2 +- arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 78 ++ arch/arm/include/asm/arch-imx8m/imx8mn_pins.h | 763 +++++++++++++++ arch/arm/include/asm/mach-imx/iomux-v3.h | 2 +- arch/arm/include/asm/mach-imx/sys_proto.h | 34 + arch/arm/mach-imx/Kconfig | 4 + arch/arm/mach-imx/Makefile | 2 + arch/arm/mach-imx/cpu.c | 4 +- arch/arm/mach-imx/imx8m/Kconfig | 11 + arch/arm/mach-imx/imx8m/Makefile | 2 +- arch/arm/mach-imx/imx8m/clock_slice.c | 4 +- arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg | 17 + arch/arm/mach-imx/imx8m/soc.c | 54 +- arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-imx/spl_imx_romapi.c | 292 ++++++ board/freescale/imx8mn_evk/Kconfig | 14 + board/freescale/imx8mn_evk/MAINTAINERS | 6 + board/freescale/imx8mn_evk/Makefile | 12 + board/freescale/imx8mn_evk/ddr4_timing.c | 1214 ++++++++++++++++++++++++ board/freescale/imx8mn_evk/imx8mn_evk.c | 29 + board/freescale/imx8mn_evk/spl.c | 123 +++ configs/imx8mn_ddr4_evk_defconfig | 78 ++ drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imx8mn.c | 415 ++++++++ drivers/pinctrl/nxp/pinctrl-imx8m.c | 1 + include/configs/imx8mn_evk.h | 156 +++ include/dt-bindings/clock/imx8mn-clock.h | 215 +++++ include/imximage.h | 1 + tools/imx8m_image.sh | 10 + tools/imx8mimage.c | 24 +- 38 files changed, 5254 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-ddr4-evk.dts create mode 100644 arch/arm/dts/imx8mn-pinfunc.h create mode 100644 arch/arm/dts/imx8mn.dtsi create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mn_pins.h create mode 100644 arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg create mode 100644 arch/arm/mach-imx/spl_imx_romapi.c create mode 100644 board/freescale/imx8mn_evk/Kconfig create mode 100644 board/freescale/imx8mn_evk/MAINTAINERS create mode 100644 board/freescale/imx8mn_evk/Makefile create mode 100644 board/freescale/imx8mn_evk/ddr4_timing.c create mode 100644 board/freescale/imx8mn_evk/imx8mn_evk.c create mode 100644 board/freescale/imx8mn_evk/spl.c create mode 100644 configs/imx8mn_ddr4_evk_defconfig create mode 100644 drivers/clk/imx/clk-imx8mn.c create mode 100644 include/configs/imx8mn_evk.h create mode 100644 include/dt-bindings/clock/imx8mn-clock.h -- 2.16.4

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[U-Boot] 答复: 答复: 答复: [PATCH 0/4] Make some changes to SDP
by Sherry Sun 12 Dec '19

12 Dec '19

Hi Angus, Hi Sherry, On Aug. 8, 2019 2:38 a.m., Sherry Sun <sherry.sun(a)nxp.com<mailto:sherry.sun@nxp.com>> wrote: Hi Angus, Sorry for the late reply. > -----邮件原件----- > 发件人: Angus Ainslie <angus(a)akkea.ca<mailto:angus@akkea.ca>> > 发送时间: 2019年8月2日 10:30 > 收件人: Peng Fan <peng.fan(a)nxp.com<mailto:peng.fan@nxp.com>> > 抄送: Sherry Sun <sherry.sun(a)nxp.com<mailto:sherry.sun@nxp.com>>; sbabic(a)denx.de<mailto:sbabic@denx.de>; > festevam(a)gmail.com<mailto:festevam@gmail.com>; lukma(a)denx.de<mailto:lukma@denx.de>; marex(a)denx.de<mailto:marex@denx.de>; > u-boot(a)lists.denx.de<mailto:u-boot@lists.denx.de>; dl-uboot-imx <uboot-imx(a)nxp.com<mailto:uboot-imx@nxp.com>> > 主题: Re: 答复: [U-Boot] [PATCH 0/4] Make some changes to SDP > > Hi Peng, > > On 2019-08-01 18:01, Peng Fan wrote: > > Angus, > > > >> Subject: Re: 答复: [U-Boot] [PATCH 0/4] Make some changes to SDP > >> > >> Hi Sherry, > >> > >> On 2019-07-31 19:56, Sherry Sun wrote: > >> > Hi Angus > >> > > >> >> > >> >> Hi Sherry, > >> >> > >> >> On 2019-07-17 18:40, sherry sun wrote: > >> >> > From: Sherry Sun <sherry.sun(a)nxp.com<mailto:sherry.sun@nxp.com>> > >> >> > > >> >> > This patchset adds: > >> >> > 1. Add usb_gadget_initialize() and usb_gadget_release() to > >> >> > initialize and release UDC during sdp download. > >> >> > 2. Add high speed endpoint descriptor for sdp. > >> >> > 3. Add a macro definition--CONFIG_SDP_LOADADDR as default sdp > >> >> > load address while SDP_WRITE and SDP_JUMP command addr is zero. > >> >> > > >> >> > Sherry Sun (4): > >> >> > imx: spl: Change USB boot device type > >> >> > SDP: use CONFIG_SDP_LOADADDR as default load address > >> >> > SDP: fix wrong usb request size and add high speed endpoint > >> >> > descriptor > >> >> > SDP: Call usb_gadget_initialize and usb_gadget_release to > >> >> > support UDC > >> >> > >> >> These changes look like like they target SDP on imx8. For imx8mq > >> >> is this all that is required to get SDP working with uuu or are > >> >> there additional changes required ? > >> >> > >> > > >> > The changes in patch 1/4 are target on both imx8 and imx8m. > >> > The rest three patches are target on all boards which used SDP. > >> > So for imx8mq, if your usb gadget driver is ready ,these changes > >> > are enough to get SDP working with UUU. > >> > > >> > >> I'm trying to use SDP on the imx8mq-evk but it doesn't look like it's > >> enabled there. Do you have patches to enable SDP on the imx8mq-evk , > >> even if they aren't ready to go upstream ? > > > > You could try downstream code, > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsour > > > ce.codeaurora.org%2Fexternal%2Fimx%2Fuboot-imx%2F&data=02%7C01 > %7Cs > > > herry.sun%40nxp.com%7C6d63289fbb104168bce308d716f157c4%7C686ea1 > d3bc2b4 > > > c6fa92cd99c5c301635%7C0%7C0%7C637003098143081621&sdata=beh > 08%2Fv3f > > s8ZZPP29F1iVMfo3uNTWGf91SYYyak2GVU%3D&reserved=0 > > branch: imx_v2019.04_4.19.35_1.0.0 > > > > I already have SDP working with the vendor u-boot. I'm trying to switch to > mainline u-boot so I'm looking for mainline patches. > May I ask, is your usb gadget driver is working? Such as you can use it for fastboot or ums. >If I enable dwc3 gadget and DM for the SPL then I must start removing other SPL features to get it to fit in the 124k allocation. > >It sounds like you haven't tested this on the imx8mq-evk then ? Yes, I have not used imx8mq-evk yet. I will try to test it later. Best regards Sherry sun >Thanks >Angus Best regards Sherry sun > Thanks > Angus > > > Regards, > > Peng. > > > >> > >> Thanks > >> Angus > >> > >> > Best regards > >> > Sherry sun > >> > > >> >> Thanks > >> >> Angus > >> >> > >> >> > > >> >> > arch/arm/mach-imx/spl.c | 2 +- > >> >> > common/spl/spl_sdp.c | 4 ++++ > >> >> > drivers/usb/gadget/Kconfig | 4 ++++ > >> >> > drivers/usb/gadget/f_sdp.c | > >> >> > 39 > >> >> > +++++++++++++++++++++++++++++++++----- > >> >> > 4 files changed, 43 insertions(+), 6 deletions(-)

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[U-Boot] [PATCH v2] Prevented possible null dereference.
by Niv Shetrit 05 Dec '19

05 Dec '19

Signed-off-by: Niv Shetrit <niv.shetrit(a)altair-semi.com> --- common/cli_hush.c | 73 ++++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/common/cli_hush.c b/common/cli_hush.c index 8f86e4aa4a..c14302c3ad 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -3539,41 +3539,44 @@ static char *insert_var_value_sub(char *inp, int tag_subst) } inp = ++p; /* find the ending marker */ - p = strchr(inp, SPECIAL_VAR_SYMBOL); - *p = '\0'; - /* look up the value to substitute */ - if ((p1 = lookup_param(inp))) { - if (tag_subst) - len = res_str_len + strlen(p1) + 2; - else - len = res_str_len + strlen(p1); - res_str = xrealloc(res_str, (1 + len)); - if (tag_subst) { - /* - * copy the variable value to the result - * string - */ - strcpy((res_str + res_str_len + 1), p1); - - /* - * mark the replaced text to be accepted as - * is - */ - res_str[res_str_len] = SUBSTED_VAR_SYMBOL; - res_str[res_str_len + 1 + strlen(p1)] = - SUBSTED_VAR_SYMBOL; - } else - /* - * copy the variable value to the result - * string - */ - strcpy((res_str + res_str_len), p1); - - res_str_len = len; - } - *p = SPECIAL_VAR_SYMBOL; - inp = ++p; - done = 1; + p = strchr(inp, SPECIAL_VAR_SYMBOL) + if (p != NULL) { + *p = '\0'; + /* look up the value to substitute */ + p1 = lookup_param(inp) + if (p1 != NULL) { + if (tag_subst) + len = res_str_len + strlen(p1) + 2; + else + len = res_str_len + strlen(p1); + res_str = xrealloc(res_str, (1 + len)); + if (tag_subst) { + /* + * copy the variable value to the + * result string + */ + strcpy((res_str + res_str_len + 1), p1); + + /* + * mark the replaced text to be + * accepted as is + */ + res_str[res_str_len] = SUBSTED_VAR_SYMBOL; + res_str[res_str_len + 1 + strlen(p1)] = + SUBSTED_VAR_SYMBOL; + } else + /* + * copy the variable value to the result + * string + */ + strcpy((res_str + res_str_len), p1); + + res_str_len = len; + } + *p = SPECIAL_VAR_SYMBOL; + inp = ++p; + done = 1; + } } if (done) { res_str = xrealloc(res_str, (1 + res_str_len + strlen(inp))); -- 2.17.1

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[U-Boot] [PATCHv2 1/2] PCI: layerscape: Add Support for ls2088 PCIe EP mode
by Xiaowei Bao 05 Dec '19

05 Dec '19

From: Xiaowei Bao <xiaowei.bao(a)nxp.com> Signed-off-by: hongbo.wang <hongbo.wang(a)nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian(a)nxp.com> Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- v2: - Add the NXP copyright and make the function readability. drivers/pci/pcie_layerscape.c | 117 +++++++++++++++++++++++++++-------------- drivers/pci/pcie_layerscape.h | 19 +++++-- 2 files changed, 91 insertions(+), 45 deletions(-) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index db1375a..8f5ebda 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver */ @@ -105,13 +105,14 @@ static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, } /* Use bar match mode and MEM type as default */ -static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, - int bar, u64 phys) +static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, int idx, + int bar, u64 phys) { dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT); dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET); dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET); - dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); + dbi_writel(pcie, PCIE_ATU_TYPE_MEM | PCIE_CTRL1_FUNC_NUM(pf), + PCIE_ATU_CR1); dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2); } @@ -341,50 +342,61 @@ static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) ls_pcie_disable_bars(pcie); } -static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) +static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie, u32 pf) { - u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE; + pci_size_t atu_size = CONFIG_SYS_PCI_MEMORY_SIZE; + u64 phys = 0; + phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_2M; + + phys = ALIGN(phys, PCIE_BAR0_SIZE); /* ATU 0 : INBOUND : map BAR0 */ - ls_pcie_atu_inbound_set(pcie, 0, 0, phys); + ls_pcie_atu_inbound_set(pcie, pf, 0 + pf * BAR_NUM, 0, phys); /* ATU 1 : INBOUND : map BAR1 */ - phys += PCIE_BAR1_SIZE; - ls_pcie_atu_inbound_set(pcie, 1, 1, phys); + phys = ALIGN(phys + PCIE_BAR0_SIZE, PCIE_BAR1_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 1 + pf * BAR_NUM, 1, phys); /* ATU 2 : INBOUND : map BAR2 */ - phys += PCIE_BAR2_SIZE; - ls_pcie_atu_inbound_set(pcie, 2, 2, phys); - /* ATU 3 : INBOUND : map BAR4 */ - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE; - ls_pcie_atu_inbound_set(pcie, 3, 4, phys); + phys = ALIGN(phys + PCIE_BAR1_SIZE, PCIE_BAR2_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 2 + pf * BAR_NUM, 2, phys); + /* ATU 3 : INBOUND : map BAR2 */ + phys = ALIGN(phys + PCIE_BAR2_SIZE, PCIE_BAR2_SIZE); + ls_pcie_atu_inbound_set(pcie, pf, 3 + pf * BAR_NUM, 4, phys); /* ATU 0 : OUTBOUND : map MEM */ - ls_pcie_atu_outbound_set(pcie, 0, - PCIE_ATU_TYPE_MEM, - pcie->cfg_res.start, - 0, - CONFIG_SYS_PCI_MEMORY_SIZE); + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start, + 0, atu_size); + + /* ATU 1 : OUTBOUND : map MEM */ + ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_MEM, (u64)pcie->cfg_res.start + + atu_size, atu_size, atu_size); } /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) { + u32 mask; + /* The least inbound window is 4KiB */ - if (size < 4 * 1024) - return; + if (size < SZ_4K) + mask = 0; + else + mask = size - 1; switch (bar) { case 0: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); + writel(mask, bar_base + PCI_BASE_ADDRESS_0); break; case 1: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); + writel(mask, bar_base + PCI_BASE_ADDRESS_1); break; case 2: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); + writel(mask, bar_base + PCI_BASE_ADDRESS_2); writel(0, bar_base + PCI_BASE_ADDRESS_3); break; case 4: - writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); + writel(mask, bar_base + PCI_BASE_ADDRESS_4); writel(0, bar_base + PCI_BASE_ADDRESS_5); break; default: @@ -394,13 +406,28 @@ static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size) static void ls_pcie_ep_setup_bars(void *bar_base) { - /* BAR0 - 32bit - 4K configuration */ + /* BAR0 - 32bit - configuration */ + ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); + /* BAR1 - 32bit - MSIX*/ + ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); + /* BAR2 - 64bit - MEM descriptor */ + ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); + /* BAR4 - 64bit - MEM*/ + ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); +} + +static void ls_pcie_ep_setup_vf_bars(void *bar_base) +{ + /* VF BAR0 MASK register at offset 0x19c*/ + bar_base += PCIE_SRIOV_VFBAR0 - PCI_BASE_ADDRESS_0; + + /* VF-BAR0 - 32bit - configuration */ ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE); - /* BAR1 - 32bit - 8K MSIX*/ + /* VF-BAR1 - 32bit - MSIX*/ ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE); - /* BAR2 - 64bit - 4K MEM desciptor */ + /* VF-BAR2 - 64bit - MEM descriptor */ ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); - /* BAR4 - 64bit - 1M MEM*/ + /* VF-BAR4 - 64bit - MEM*/ ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE); } @@ -412,25 +439,33 @@ static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) static void ls_pcie_setup_ep(struct ls_pcie *pcie) { u32 sriov; + u32 pf, vf; + void *bar_base = NULL; sriov = readl(pcie->dbi + PCIE_SRIOV); if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) { - int pf, vf; - + pcie->sriov_flag = 1; for (pf = 0; pf < PCIE_PF_NUM; pf++) { - for (vf = 0; vf <= PCIE_VF_NUM; vf++) { - ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), - PCIE_PF_VF_CTRL); - - ls_pcie_ep_setup_bars(pcie->dbi); - ls_pcie_ep_setup_atu(pcie); + if (pcie->cfg2_flag) { + for (vf = 0; vf <= PCIE_VF_NUM; vf++) { + ctrl_writel(pcie, + PCIE_LCTRL0_VAL(pf, vf), + PCIE_PF_VF_CTRL); + } } + bar_base = pcie->dbi + + PCIE_MASK_OFFSET(pcie->cfg2_flag, pf); + ls_pcie_ep_setup_bars(bar_base); + ls_pcie_ep_setup_vf_bars(bar_base); + + ls_pcie_ep_setup_atu(pcie, pf); } - /* Disable CFG2 */ - ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); + + if (pcie->cfg2_flag) /* Disable CFG2 */ + ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); } else { ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); - ls_pcie_ep_setup_atu(pcie); + ls_pcie_ep_setup_atu(pcie, 0); } ls_pcie_ep_enable_cfg(pcie); @@ -502,6 +537,7 @@ static int ls_pcie_probe(struct udevice *dev) * for LS2088A series SoCs */ svr = get_svr(); + pcie->cfg2_flag = 1; svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE; if (svr == SVR_LS2088A || svr == SVR_LS2084A || svr == SVR_LS2048A || svr == SVR_LS2044A || @@ -511,6 +547,7 @@ static int ls_pcie_probe(struct udevice *dev) LS2088A_PCIE_PHYS_SIZE * pcie->idx; pcie->cfg_res.end = pcie->cfg_res.start + cfg_size; pcie->ctrl = pcie->lut + 0x40000; + pcie->cfg2_flag = 0; } pcie->cfg0 = map_physmem(pcie->cfg_res.start, diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index ddfbba6..eb910ba 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * Layerscape PCIe driver */ @@ -9,6 +9,7 @@ #define _PCIE_LAYERSCAPE_H_ #include <pci.h> #include <dm.h> +#include <linux/sizes.h> #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -85,11 +86,17 @@ #define PCIE_PF_NUM 2 #define PCIE_VF_NUM 64 +#define BAR_NUM 4 -#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ -#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ -#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ +#define PCIE_BAR0_SIZE SZ_4K /* 4K */ +#define PCIE_BAR1_SIZE SZ_8K /* 8K for MSIX */ +#define PCIE_BAR2_SIZE SZ_4K /* 4K */ +#define PCIE_BAR4_SIZE SZ_1M /* 1M */ + +#define PCIE_SRIOV_VFBAR0 0x19C +#define PCIE_CTRL1_FUNC_NUM(pf) (pf << 20) + +#define PCIE_MASK_OFFSET(flag, pf) ((flag) ? 0 : (0x1000 + 0x20000 * (pf))) /* LUT registers */ #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) @@ -144,6 +151,8 @@ struct ls_pcie { bool big_endian; bool enabled; int next_lut_index; + uint sriov_flag; + uint cfg2_flag; int mode; }; -- 1.7.1

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[U-Boot] [PATCH v4 1/2] disk: update to use SPL_PARTITIONS for SPL
by Kever Yang 03 Dec '19

03 Dec '19

The SPL disk driver can not depends on SPL_FRAMEWORK & PARTITIONS, which will enable the disk driver when we actually not need it. Use a separate Kconfig to control the partition driver in SPL and fix the issue caused by: Fixes: 91ff686562 ("blk: Rework guard around part_init call") Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v4: - format the commit message to ~75 columns. Changes in v3: - update code in blk-uclass.c Changes in v2: - add this patch common/spl/Kconfig | 2 +- disk/Kconfig | 20 ++++++++++++-------- disk/Makefile | 2 +- drivers/block/blk-uclass.c | 2 +- scripts/Makefile.spl | 2 +- 5 files changed, 16 insertions(+), 12 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 5978fb2934..094680e54d 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -544,7 +544,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBDISK_SUPPORT bool "Support disk partitions" - select PARTITIONS + select SPL_PARTITIONS help Enable support for disk partitions within SPL. 'Disk' is something of a misnomer as it includes non-spinning media such as flash (as diff --git a/disk/Kconfig b/disk/Kconfig index 28fb81c2ee..43e76cb49d 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -4,9 +4,7 @@ menu "Partition Types" config PARTITIONS bool "Enable Partition Labels (disklabels) support" default y - select SPL_SPRINTF if SPL select TPL_SPRINTF if TPL - select SPL_STRTO if SPL select TPL_STRTO if TPL help Partition Labels (disklabels) Supported: @@ -23,6 +21,12 @@ config PARTITIONS you must configure support for at least one non-MTD partition type as well. +config SPL_PARTITIONS + select SPL_SPRINTF + select SPL_STRTO + bool "Enable Partition Labels (disklabels) support for SPL" + depends on SPL + config MAC_PARTITION bool "Enable Apple's MacOS partition table" depends on PARTITIONS @@ -32,7 +36,7 @@ config MAC_PARTITION config SPL_MAC_PARTITION bool "Enable Apple's MacOS partition table for SPL" - depends on SPL && PARTITIONS + depends on SPL_PARTITIONS default y if MAC_PARTITION config DOS_PARTITION @@ -45,7 +49,7 @@ config DOS_PARTITION config SPL_DOS_PARTITION bool "Enable MS Dos partition table for SPL" - depends on SPL && PARTITIONS + depends on SPL_PARTITIONS default y if DOS_PARTITION config ISO_PARTITION @@ -56,7 +60,7 @@ config ISO_PARTITION config SPL_ISO_PARTITION bool "Enable ISO partition table for SPL" - depends on SPL && PARTITIONS + depends on SPL_PARTITIONS config AMIGA_PARTITION bool "Enable AMIGA partition table" @@ -67,7 +71,7 @@ config AMIGA_PARTITION config SPL_AMIGA_PARTITION bool "Enable AMIGA partition table for SPL" - depends on SPL && PARTITIONS + depends on SPL_PARTITIONS default y if AMIGA_PARTITION config EFI_PARTITION @@ -111,7 +115,7 @@ config EFI_PARTITION_ENTRIES_OFF config SPL_EFI_PARTITION bool "Enable EFI GPT partition table for SPL" - depends on SPL && PARTITIONS + depends on SPL_PARTITIONS default y if EFI_PARTITION config PARTITION_UUIDS @@ -125,7 +129,7 @@ config PARTITION_UUIDS config SPL_PARTITION_UUIDS bool "Enable support of UUID for partition in SPL" - depends on SPL && PARTITIONS + depends on SPL_PARTITIONS default y if SPL_EFI_PARTITION config PARTITION_TYPE_GUID diff --git a/disk/Makefile b/disk/Makefile index ccd0335959..92fcc2b4ac 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -5,7 +5,7 @@ #ccflags-y += -DET_DEBUG -DDEBUG -obj-$(CONFIG_PARTITIONS) += part.o +obj-$(CONFIG_$(SPL_)PARTITIONS) += part.o obj-$(CONFIG_$(SPL_)MAC_PARTITION) += part_mac.o obj-$(CONFIG_$(SPL_)DOS_PARTITION) += part_dos.o obj-$(CONFIG_$(SPL_)ISO_PARTITION) += part_iso.o diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index c23b6682a6..425ec3259f 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -649,7 +649,7 @@ int blk_unbind_all(int if_type) static int blk_post_probe(struct udevice *dev) { -#if defined(CONFIG_PARTITIONS) && defined(CONFIG_HAVE_BLOCK_DEVICE) +#if CONFIG_IS_ENABLED(PARTITIONS) && defined(CONFIG_HAVE_BLOCK_DEVICE) struct blk_desc *desc = dev_get_uclass_platdata(dev); part_init(desc); diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 7af6b120b6..3535978634 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -82,7 +82,7 @@ else libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ cmd/ env/ libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ ifdef CONFIG_SPL_FRAMEWORK -libs-$(CONFIG_PARTITIONS) += disk/ +libs-$(CONFIG_SPL_PARTITIONS) += disk/ endif endif -- 2.17.1

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