September 2019 - U-Boot

[U-Boot] [PPC] Internet connection on qemu-ppce500
by vnktux 12 May '20

12 May '20

Hello guys, I am running an image of U-boot 2018.09 in qemu 3.0, the goal would be to load an OS-9 rom file from tftp. The problem is that I can't manage to have an Internet connection in U-boot. No matter how I run the image I always have Net: "No Ethernet found". I run qemu 3.0 with the following command: > qemu-system-ppc -cpu e500v2 -M ppce500 -nographic -kernel ~/u-boot -net nic -net tap,ifname=tap0,script=no I tried to use different -net options in qemu but the problem is always the same. And from the u-boot source code I have edited the board file qemu-ppce500.c in order to have a few ENV variables (since I can't save any env variables from the running U-boot in qemu). > ethact=eTSEC1 > ethprime=eTSEC1 > ethaddr=192.168.10.40 > netmask=255.255.254.0 > serverip=192.168.10.2 > gatewayip=192.168.10.254 The image is compiled using of course: qemu-ppce500_defconfig. What am I doing wrong? Is it even possible to initialize the Ethernet port? Thanks in advance, Vincenzo Sent with [ProtonMail](https://protonmail.com) Secure Email.

3 2

[U-Boot] [PATCH v6 1/4] dm: spi: Convert Freescale ESPI driver to driver model
by Xiaowei Bao 12 May '20

12 May '20

From: Chuanhua Han <chuanhua.han(a)nxp.com> Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems: ===================== WARNING ====================== This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Chuanhua Han <chuanhua.han(a)nxp.com> Signed-off-by: Xiaowei Bao <xiaowei.bao(a)nxp.com> --- depends on: https://patchwork.ozlabs.org/cover/1146494/ Changes in v6: - Change #ifndef CONFIG_DM_SPI to #if !CONFIG_IS_ENABLED(DM_SPI). Changes in v5: - Modify the function spi_cs_activate to fsl_spi_cs_activate. - Move cs to the parameter of the fsl_spi_cs_activate function. Changes in v4: - Update copyright information. - Move the fsl_espi_platdata data structure to the include/dm/platform_data/. - Merge the contents of the fsl_espi_priv structure into the fsl_spi_slave structure. - Implement the fsl_espi_set_speed function. - Implement the fsl_espi_set_mode function. - Implement the espi_release_bus function. - Remove unwanted fsl_espi_bind functions. - Implement the fsl_espi_child_pre_probe function as needed. - Use #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA). Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - The fsl_espi driver support both OF_CONTROL and PLATDATA. drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- include/dm/platform_data/fsl_espi.h | 16 ++ 2 files changed, 337 insertions(+), 124 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7444ae1..fd5ac97 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,18 +3,25 @@ * eSPI controller driver. * * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) + * Chuanhua Han (chuanhua.han(a)nxp.com) */ #include <common.h> - #include <malloc.h> #include <spi.h> #include <asm/immap_85xx.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <dm/platform_data/fsl_espi.h> struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi; + u32 speed_hz; + unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout; @@ -28,6 +35,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL +/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000 + #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32 @@ -62,116 +72,27 @@ struct fsl_spi_slave { #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_spi_slave *fsl; - sys_info_t sysinfo; - unsigned long spibrg = 0; - unsigned long spi_freq = 0; - unsigned char pm = 0; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); - if (!fsl) - return NULL; - - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - fsl->mode = mode; - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; - - /* Set eSPI BRG clock source */ - get_sys_info(&sysinfo); - spibrg = sysinfo.freq_systembus / 2; - fsl->div16 = 0; - if ((spibrg / max_hz) > 32) { - fsl->div16 = ESPI_CSMODE_DIV16; - pm = spibrg / (max_hz * 16 * 2); - if (pm > 16) { - pm = 16; - debug("Requested speed is too low: %d Hz, %ld Hz " - "is used.\n", max_hz, spibrg / (32 * 16)); - } - } else - pm = spibrg / (max_hz * 2); - if (pm) - pm--; - fsl->pm = pm; - - if (fsl->div16) - spi_freq = spibrg / ((pm + 1) * 2 * 16); - else - spi_freq = spibrg / ((pm + 1) * 2); - - /* set tx_timeout to 10 times of one espi FIFO entry go out */ - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT - * 10), spi_freq); - - return &fsl->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - free(fsl); -} - -int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi; - unsigned char pm = fsl->pm; - unsigned int cs = slave->cs; - unsigned int mode = fsl->mode; - unsigned int div16 = fsl->div16; - int i; - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); - - /* Enable eSPI interface */ - out_be32(&espi->mode, ESPI_MODE_RXTHR(3) - | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); - - out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ - out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ - - /* Init CS mode interface */ - for (i = 0; i < ESPI_MAX_CS_NUM; i++) - out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); - - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & - ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 - | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK - | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); - - /* Set eSPI BRG clock source */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_PM(pm) | div16); - - /* Set eSPI mode */ - if (mode & SPI_CPHA) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CP_BEGIN_EDGCLK); - if (mode & SPI_CPOL) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CI_INACTIVEHIGH); - - /* Character bit order: msb first */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_REV_MSB_FIRST); - - /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_LEN(7)); + unsigned int com = 0; + size_t data_len = fsl->data_len; - return 0; + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); } -void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) { + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi; + /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); } static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -204,7 +125,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) debug("***spi_xfer:...Tx timeout! event = %08x\n", event); } -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, + unsigned int bytes) { ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -236,10 +158,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) +void espi_release_bus(struct fsl_spi_slave *fsl) { - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + /* Disable the SPI hardware */ + out_be32(&fsl->espi->mode, + in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); +} + +int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL; @@ -258,13 +187,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN: - cmd_len = fsl->cmd_len = data_len; + cmd_len = data_len; + fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) { - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); @@ -304,7 +234,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; - spi_cs_activate(slave); + fsl_spi_cs_activate(slave, cs); /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); @@ -347,37 +277,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, *(int *)buffer += tran_len; } } - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); } free(buffer); return 0; } +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned char pm = fsl->pm; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); +} + +void espi_setup_slave(struct fsl_spi_slave *fsl) +{ + unsigned int max_hz; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned long spi_freq = 0; + unsigned char pm = 0; + + max_hz = fsl->speed_hz; + + get_sys_info(&sysinfo); + spibrg = sysinfo.freq_systembus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("max_hz is too low: %d Hz, %ld Hz is used.\n", + max_hz, spibrg / (32 * 16)); + } + } else { + pm = spibrg / (max_hz * 2); + } + if (pm) + pm--; + fsl->pm = pm; + + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq);/* Set eSPI BRG clock source */ +} + +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; } -void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_spi_slave *fsl; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); + if (!fsl) + return NULL; + + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = max_hz; + + espi_setup_slave(fsl); + + return &fsl->slave; +} + +void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int com = 0; - size_t data_len = fsl->data_len; - com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); - com |= ESPI_COM_CS(slave->cs); - com |= ESPI_COM_TRANLEN(data_len - 1); - out_be32(&espi->com, com); + free(fsl); } -void spi_cs_deactivate(struct spi_slave *slave) +int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - /* clear the RXCNT and TXCNT */ - out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); - out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); + espi_claim_bus(fsl, slave->cs); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + + espi_release_bus(fsl); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave; + + return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); +} +#else +static void __espi_set_speed(struct fsl_spi_slave *fsl) +{ + espi_setup_slave(fsl); + + /* Set eSPI BRG clock source */ + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); +} + +static void __espi_set_mode(struct fsl_spi_slave *fsl) +{ + /* Set eSPI mode */ + if (fsl->mode & SPI_CPHA) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (fsl->mode & SPI_CPOL) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); +} + +static int fsl_espi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_claim_bus(fsl, fsl->cs); + + return 0; +} + +static int fsl_espi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_release_bus(fsl); + + return 0; +} + +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); +} + +static int fsl_espi_set_speed(struct udevice *bus, uint speed) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s speed %u\n", __func__, speed); + fsl->speed_hz = speed; + + __espi_set_speed(fsl); + + return 0; +} + +static int fsl_espi_set_mode(struct udevice *bus, uint mode) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + fsl->mode = mode; + + __espi_set_mode(fsl); + + return 0; } + +static int fsl_espi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s cs %u\n", __func__, slave_plat->cs); + fsl->cs = slave_plat->cs; + + return 0; +} + +static int fsl_espi_probe(struct udevice *bus) +{ + struct fsl_espi_platdata *plat = dev_get_platdata(bus); + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr); + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = plat->speed_hz; + + debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); + + return 0; +} + +static const struct dm_spi_ops fsl_espi_ops = { + .claim_bus = fsl_espi_claim_bus, + .release_bus = fsl_espi_release_bus, + .xfer = fsl_espi_xfer, + .set_speed = fsl_espi_set_speed, + .set_mode = fsl_espi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) +{ + fdt_addr_t addr; + struct fsl_espi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + addr = dev_read_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs_addr = lower_32_bits(addr); + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_ESPI_DEFAULT_SCK_FREQ); + + debug("ESPI: regs=%p, max-frequency=%d\n", + &plat->regs_addr, plat->speed_hz); + + return 0; +} + +static const struct udevice_id fsl_espi_ids[] = { + { .compatible = "fsl,mpc8536-espi" }, + { } +}; +#endif + +U_BOOT_DRIVER(fsl_espi) = { + .name = "fsl_espi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = fsl_espi_ids, + .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, +#endif + .ops = &fsl_espi_ops, + .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_spi_slave), + .probe = fsl_espi_probe, + .child_pre_probe = fsl_espi_child_pre_probe, +}; +#endif diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000..812933f --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_platdata { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */ -- 2.9.5

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[U-Boot] Enable USB host controller on Odroid-C2
by Beniamino Galvani 11 May '20

11 May '20

Hi, these two patches enable the USB host controller on Odroid-C2. The first patch adds a PHY driver; the second one enables the necessary configuration options and updates the device tree. Note that the DWC2 driver currently does not support enabling PHYs from the device tree and so the following series (still on review) is needed as runtime requirement for the second patch: [PATCH 0/5] usb: host: dwc2: use driver model for PHY and CLOCK Thanks, Beniamino Beniamino Galvani (2): phy: meson: add GXBB PHY driver odroid-c2: enable USB host controller arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 8 + configs/odroid-c2_defconfig | 7 + drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/meson-gxbb-usb2.c | 235 +++++++++++++++++++ include/configs/meson64.h | 5 + 6 files changed, 264 insertions(+) create mode 100644 drivers/phy/meson-gxbb-usb2.c -- 2.21.0

2 10

[U-Boot] [PATCH v2 00/18] autoboot: Tidy up autoboot code
by Simon Glass 06 May '20

06 May '20

5 24

[U-Boot] [PATCH] Makefile: Only build dtc if needed
by Simon Glass 28 Apr '20

28 Apr '20

At present U-Boot always builds dtc if CONFIG_OF_CONTROL is defined. This is wasteful when the system already has a suitable version available. Update the Makefile logic to build dtc only if the version available is too old. This saves about 3 seconds of CPU time on a clean build for me. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Makefile | 17 +++++++++++++++-- dts/Kconfig | 4 ---- scripts/Kbuild.include | 4 +++- scripts/Makefile | 1 - scripts/dtc-version.sh | 25 ++++++++++++++++++++----- 5 files changed, 38 insertions(+), 13 deletions(-) diff --git a/Makefile b/Makefile index 250eb6c3c39..fec2b2d8fb5 100644 --- a/Makefile +++ b/Makefile @@ -361,7 +361,12 @@ PERL = perl PYTHON ?= python PYTHON2 = python2 PYTHON3 = python3 -DTC ?= $(objtree)/scripts/dtc/dtc + +# DTC is automatically built if the version of $(DTC) is older that needed. +# Use the system dtc if it is new enough. +DTC ?= dtc +DTC_MIN_VERSION := 010406 + CHECK = sparse CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ @@ -926,7 +931,7 @@ endif PHONY += dtbs dtbs: dts/dt.dtb @: -dts/dt.dtb: u-boot +dts/dt.dtb: checkdtc u-boot $(Q)$(MAKE) $(build)=dts dtbs quiet_cmd_copy = COPY $@ @@ -1579,6 +1584,14 @@ SYSTEM_MAP = \ System.map: u-boot @$(call SYSTEM_MAP,$<) > $@ +build_dtc := $(objtree)/scripts/dtc/dtc + +checkdtc: + $(eval DTC := $(call dtc-version,010406,$(build_dtc))) + if test "$(DTC)" = "$(build_dtc)"; then \ + $(MAKE) $(build)=scripts/dtc; \ + fi + ######################################################################### # ARM relocations should all be R_ARM_RELATIVE (32-bit) or diff --git a/dts/Kconfig b/dts/Kconfig index 8917f424445..7e600e28f6c 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -5,9 +5,6 @@ config SUPPORT_OF_CONTROL bool -config DTC - bool - config PYLIBFDT bool @@ -24,7 +21,6 @@ menu "Device Tree Control" config OF_CONTROL bool "Run-time configuration via Device Tree" - select DTC help This feature provides for run-time configuration of U-Boot via a flattened device tree. diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 13ebddda65c..82be40cbe78 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -147,8 +147,10 @@ cc-fullversion = $(shell $(CONFIG_SHELL) \ cc-ifversion = $(shell [ $(cc-version) $(1) $(2) ] && echo $(3) || echo $(4)) # added for U-Boot +# $1: min_version +# #2: build_dtc binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS)) -dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC)) +dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC) $1 $2) # cc-ldoption # Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both) diff --git a/scripts/Makefile b/scripts/Makefile index e7b353f77f4..cfe9fef8044 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -10,4 +10,3 @@ always := $(hostprogs-y) # Let clean descend into subdirs subdir- += basic kconfig -subdir-$(CONFIG_DTC) += dtc diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh index 0744c39eb04..ec988e18daf 100755 --- a/scripts/dtc-version.sh +++ b/scripts/dtc-version.sh @@ -1,12 +1,22 @@ #!/bin/sh # -# dtc-version dtc-command +# dtc-version dtc_command min_version build_dtc # -# Prints the dtc version of `dtc-command' in a canonical 6-digit form -# such as `010404' for dtc 1.4.4 +# Selects which version of dtc to use +# +# If the version of dtc_command is < min_version, prints build_dtc else +# prints dtc_command. The min_version is in the format MMmmpp where: +# +# MM is the major version +# mm is the minor version +# pp is the patch level +# +# For example 010406 means 1.4.6 # -dtc="$*" +dtc="$1" +min_version="$2" +build_dtc="$3" if [ ${#dtc} -eq 0 ]; then echo "Error: No dtc command specified." @@ -18,4 +28,9 @@ MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1) MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2) PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1) -printf "%02d%02d%02d\\n" $MAJOR $MINOR $PATCH +version="$(printf "%02d%02d%02d" $MAJOR $MINOR $PATCH)" +if test $version -lt $min_version; then \ + echo $build_dtc +else + echo $dtc +fi -- 2.19.1.930.g4563a0d9d0-goog

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[U-Boot] [PATCH v2] imx: Introduce CONFIG_SPL_FORCE_MMC_BOOT to force MMC boot on falcon mode
by Lukasz Majewski 08 Apr '20

08 Apr '20

This change tries to fix the following problem: - The board boots (to be more precise - ROM loads SPL) from a slow SPI-NOR memory. As a result the spl_boot_device() will return SPI-NOR as a boot device (which is correct). - The problem is that in 'falcon boot' the eMMC is used as a boot medium to load kernel from its partition. Calling spl_boot_device() will break things as it returns SPI-NOR device. To fix this issue the new CONFIG_SPL_FORCE_MMC_BOOT Kconfig flag is introduced to handle this special use case. By default it is not defined, so there is no change in the legacy code flow. Signed-off-by: Lukasz Majewski <lukma(a)denx.de> --- Changes in v2: - Update/enhance the Kconfig description of the SPL_FORCE_MMC_BOOT. This patch is a follow up of previous discussion/fix: https://patchwork.ozlabs.org/patch/796237/ Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/580272414 --- arch/arm/mach-imx/spl.c | 11 +++++++++++ common/spl/Kconfig | 9 +++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 1f230aca3397..daa3d8f7ed94 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -178,7 +178,18 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ u32 spl_boot_mode(const u32 boot_device) { +/* + * When CONFIG_SPL_FORCE_MMC_BOOT is defined the 'boot_device' is used + * unconditionally to decide about device to use for booting. + * This is crucial for falcon boot mode, when board boots up (i.e. ROM + * loads SPL) from slow SPI-NOR memory and afterwards the SPL's 'falcon' boot + * mode is used to load Linux OS from eMMC partition. + */ +#ifdef CONFIG_SPL_FORCE_MMC_BOOT + switch (boot_device) { +#else switch (spl_boot_device()) { +#endif /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f467eca2be72..fe800840beb6 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -607,6 +607,15 @@ config SPL_MMC_SUPPORT this option to build the drivers in drivers/mmc as part of an SPL build. +config SPL_FORCE_MMC_BOOT + bool "Force SPL booting from MMC" + depends on SPL_MMC_SUPPORT + default n + help + Force SPL to use MMC device for Linux kernel booting even when the + SoC ROM recognized boot medium is not eMMC/SD. This is crucial for + factory or 'falcon mode' booting. + config SPL_MMC_TINY bool "Tiny MMC framework in SPL" depends on SPL_MMC_SUPPORT -- 2.11.0

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[U-Boot] [PATCH v1 0/2] stm32f7 gpio driver fixes
by Patrice Chotard 31 Mar '20

31 Mar '20

This series adds: - Fix gpio bank hole management for stm32 F7 and H7 - Fix SPL code size for stm32 F7 Patrice Chotard (2): gpio: stm32f7: Fix gpio bank hole management gpio: stm32f7: Fix SPL code size drivers/gpio/stm32f7_gpio.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) -- 1.9.1

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[U-Boot] [PATCH V3 00/27] i.MX8MM support
by Peng Fan 05 Mar '20

05 Mar '20

V3: Added a new patch from Frieder: imx: mkimage_fit_atf: Fix FIT image for correct boot order Tag fixes for Frieder Drop rom_pointer use in patch 27/27 and clean up included files. 4bytes-> 4 bytes in patch 2/27 V2: Fixed comments from Lukasz and Frieder The following was newly added. imx8m: imx-regs: drop unused register definitions imx8m: restrict reset_cpu imx: mmc_env: update runtime SD/MMC boot env device imx8m: soc: probe clock device in arch_cpu_init_dm V1: https://patchwork.ozlabs.org/cover/1144326/ This is a splitted and updated patch from https://patchwork.ozlabs.org/cover/1128799/ which is to support both i.MX8MM and i.MX8MN. There is a README added, following that to test if you would like to. Frieder Schrempf (1): imx: mkimage_fit_atf: Fix FIT image for correct boot order Peng Fan (25): tools: imx8m_image: align spl bin image size ddr: imx8m: fix ddr firmware location when enable SPL OF imx8m: add image cfg for i.MX8MM lpddr4 imx: add IMX8MQ kconfig entry imx: add IMX8MM kconfig entry imx: imx8mm: add clock bindings header imx: add i.MX8MM cpu type imx: spl: add spl_board_boot_device for i.MX8MM imx8m: imx-regs: drop unused register definitions imx8m: update imx-regs for i.MX8MM imx: add get_cpu_rev support for i.MX8MM imx8m: add pin header for i.MX8MM imx: add i.MX8MM PE property imx8m: Fix MMU table issue for OPTEE memory imx8m: set BYPASS ID SWAP to avoid AXI bus errors imx8m: soc: enable SCTR clock before timer init imx8m: restrict reset_cpu imx8m: rename clock to clock_imx8mq imx8m: restructure clock.h imx8m: add clk support for i.MX8MM imx: mmc_env: update runtime SD/MMC boot env device imx8m: soc: probe clock device in arch_cpu_init_dm arm: dts: import i.MX8MM dtsi arm: dts: add i.MX8MM pin func imx: Add i.MX8MM EVK board support. Ye Li (1): imx8m: Configure trustzone region 0 for non-secure access arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 92 + arch/arm/dts/imx8mm-evk.dts | 235 +++ arch/arm/dts/imx8mm-pinfunc.h | 629 +++++++ arch/arm/dts/imx8mm.dtsi | 733 ++++++++ arch/arm/include/asm/arch-imx/cpu.h | 6 + arch/arm/include/asm/arch-imx8m/clock.h | 491 +---- arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 ++++ arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +++++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 291 +-- arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 +++++++ arch/arm/include/asm/mach-imx/iomux-v3.h | 4 + arch/arm/include/asm/mach-imx/sys_proto.h | 8 + arch/arm/mach-imx/cpu.c | 12 + arch/arm/mach-imx/imx8m/Kconfig | 17 +- arch/arm/mach-imx/imx8m/Makefile | 4 +- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 306 +++ .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 5 +- arch/arm/mach-imx/imx8m/clock_slice.c | 63 + arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 16 + arch/arm/mach-imx/imx8m/soc.c | 129 +- arch/arm/mach-imx/mkimage_fit_atf.sh | 10 +- arch/arm/mach-imx/mmc_env.c | 3 + arch/arm/mach-imx/spl.c | 8 + board/freescale/imx8mm_evk/Kconfig | 12 + board/freescale/imx8mm_evk/MAINTAINERS | 6 + board/freescale/imx8mm_evk/Makefile | 12 + board/freescale/imx8mm_evk/README | 37 + board/freescale/imx8mm_evk/imx8mm_evk.c | 29 + board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 ++++++++++++++++++++ board/freescale/imx8mm_evk/spl.c | 129 ++ configs/imx8mm_evk_defconfig | 74 + drivers/ddr/imx/imx8m/helper.c | 12 +- include/configs/imx8mm_evk.h | 153 ++ include/dt-bindings/clock/imx8mm-clock.h | 253 +++ tools/imx8m_image.sh | 5 +- 36 files changed, 6562 insertions(+), 707 deletions(-) create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-evk.dts create mode 100644 arch/arm/dts/imx8mm-pinfunc.h create mode 100644 arch/arm/dts/imx8mm.dtsi create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%) create mode 100644 arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg create mode 100644 board/freescale/imx8mm_evk/Kconfig create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS create mode 100644 board/freescale/imx8mm_evk/Makefile create mode 100644 board/freescale/imx8mm_evk/README create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8mm_evk/spl.c create mode 100644 configs/imx8mm_evk_defconfig create mode 100644 include/configs/imx8mm_evk.h create mode 100644 include/dt-bindings/clock/imx8mm-clock.h -- 2.16.4

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[U-Boot] [PATCH] usb: ehci-mx5: Fix bus enumeration for DM case
by Marek Vasut 29 Feb '20

29 Feb '20

It is likely that the DM conversion of EHCI iMX5 driver was a derivative of EHCI VF, however the conversion is incomplete and is missing the bind workaround, which updates dev->seq number. Without this, all controllers have dev->seq number 0 . Add this bind workaround into EHCI iMX5 driver as well. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Abel Vesa <abel.vesa(a)nxp.com> Cc: Adam Ford <aford173(a)gmail.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Ludwig Zenz <lzenz(a)dh-electronics.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Vagrant Cascadian <vagrant(a)debian.org> --- drivers/usb/host/ehci-mx5.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 0b32728c57..4db513f4e5 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -301,6 +301,22 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev) return 0; } +static int ehci_usb_bind(struct udevice *dev) +{ + static int num_controllers; + + /* + * Without this hack, if we return ENODEV for USB Controller 0, on + * probe for the next controller, USB Controller 1 will be given a + * sequence number of 0. This conflicts with our requirement of + * sequence numbers while initialising the peripherals. + */ + dev->req_seq = num_controllers; + num_controllers++; + + return 0; +} + static int ehci_usb_probe(struct udevice *dev) { struct usb_platdata *plat = dev_get_platdata(dev); @@ -362,6 +378,7 @@ U_BOOT_DRIVER(usb_mx5) = { .id = UCLASS_USB, .of_match = mx5_usb_ids, .ofdata_to_platdata = ehci_usb_ofdata_to_platdata, + .bind = ehci_usb_bind, .probe = ehci_usb_probe, .remove = ehci_deregister, .ops = &ehci_usb_ops, -- 2.20.1

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[U-Boot] Starting u-boot in USB otg mode
by rivael_il 27 Feb '20

27 Feb '20

Hello u-booters! I want to load u-boot-sunxi-with-spl.bin and make it operate the USB in otg mode. (Where the host can still be connected to the board). How can I achieve this? (I have attempted to use: "usb0:dr_mode=otg,phy_type=utmi\0" without success). Thank you, Michael

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