September 2019 - U-Boot

[U-Boot] [PATCH] arm64: zynqmp: Enable 2 NAND chips support for zynqmp_mini_nand
by Michal Simek 08 Oct '19

08 Oct '19

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> This patch enables 2 nand chips support for zynqmp mini nand Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_mini_nand_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 4be624813ccf..2b896f79a72e 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -49,4 +49,5 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_ARASAN=y +CONFIG_SYS_NAND_MAX_CHIPS=2 # CONFIG_EFI_LOADER is not set -- 2.17.1

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[U-Boot] [PATCH v2] doc: README.xilinx: Add dt bindings
by Michal Simek 08 Oct '19

08 Oct '19

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Devicetree bindings are already specified in Linux kernel documentation. Instead of maintaining same dt bindings in U-Boot doc specify path to dt bindings in Linux kernel & documenting specific changes that are in U-Boot. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - Convert file to reST format - reported by Bin - Fix commit message doc/board/xilinx/index.rst | 1 + doc/board/xilinx/xilinx.rst | 38 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 doc/board/xilinx/xilinx.rst diff --git a/doc/board/xilinx/index.rst b/doc/board/xilinx/index.rst index 2416fbd216cd..47f09290af03 100644 --- a/doc/board/xilinx/index.rst +++ b/doc/board/xilinx/index.rst @@ -6,4 +6,5 @@ Xilinx .. toctree:: :maxdepth: 2 + xilinx zynq diff --git a/doc/board/xilinx/xilinx.rst b/doc/board/xilinx/xilinx.rst new file mode 100644 index 000000000000..f6ea5dbe2158 --- /dev/null +++ b/doc/board/xilinx/xilinx.rst @@ -0,0 +1,38 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. (C) Copyright 2019 Xilinx, Inc. + +U-Boot device tree bindings +---------------------------- + +All the device tree bindings used in U-Boot are specified in Linux +kernel. Please refer dt bindings from below specified paths in Linux +kernel. + +* ata + - Documentation/devicetree/bindings/ata/ahci-ceva.txt +* gpio + - Documentation/devicetree/bindings/gpio/gpio-xilinx.txt + - Documentation/devicetree/bindings/gpio/gpio-zynq.txt +* i2c + - Documentation/devicetree/bindings/i2c/i2c-xiic.txt + - Documentation/devicetree/bindings/i2c/i2c-cadence.txt +* mmc + - Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +* net + - Documentation/devicetree/bindings/net/macb.txt + - Documentation/devicetree/bindings/net/xilinx_axienet.txt + - Documentation/devicetree/bindings/net/xilinx_emaclite.txt +* serial + - Documentation/devicetree/bindings/serial/cdns,uart.txt + - Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt +* spi + - Documentation/devicetree/bindings/spi/spi-cadence.txt + - Documentation/devicetree/bindings/spi/spi-xilinx.txt + - Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt + - Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt +* usb + - Documentation/devicetree/bindings/usb/dwc3-xilinx.txt + - Documentation/devicetree/bindings/usb/dwc3.txt + - Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +* wdt + - Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt -- 2.17.1

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[U-Boot] [PATCH] mmc: zynq_sdhci: Remove check for DM_MMC config
by Michal Simek 08 Oct '19

08 Oct '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> The zynq_sdhci drivers depends on DM_MMC in Kconfig so no need to check for DM_MMC in the driver so this patch removes it. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/mmc/zynq_sdhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 3225a7ac9385..529eec9c45cd 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -190,7 +190,7 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host) } #endif -#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) const struct sdhci_ops arasan_ops = { .platform_execute_tuning = &arasan_sdhci_execute_tuning, .set_delay = &arasan_sdhci_set_tapdelay, @@ -266,7 +266,7 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) priv->host->name = dev->name; -#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP) +#if defined(CONFIG_ARCH_ZYNQMP) priv->host->ops = &arasan_ops; #endif -- 2.17.1

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[U-Boot] [PATCH] arm64: zynqmp: Switch spi-flash to jedec, spi-nor compatible
by Michal Simek 08 Oct '19

08 Oct '19

Change has been done across the whole tree only zynqmp-mini-qspi hasn't been fixed. Origin changed done by commit ffd4c7c2ecb7 ("dts: switch spi-flash to jedec, spi-nor compatible") Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index 1716d5179ddf..e4ba5ae9b683 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -64,7 +64,7 @@ &qspi { status = "okay"; flash0: flash@0 { - compatible = "n25q512a11", "spi-flash"; + compatible = "n25q512a11", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; -- 2.17.1

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[U-Boot] [PATCH v3] net: phy: Add gmiitorgmii converter support
by Michal Simek 08 Oct '19

08 Oct '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> This patch adds support for gmiitorgmii converter. This converter sits between the MAC and the external phy MAC <==> GMII2RGMII <==> RGMII_PHY. The ethernet driver probes this bridge and this bridge driver probes real phy driver and invokes the real phy functionalities as requested. This bridge just needs to be configured based on real phy negotiated speed and duplex. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v3: - Check that input interface type is gmii - Hardcode rgmii interface type - Add check for external phy detection - Fill node pointer for external phy - Define readext and writeext routines Changes in v2: - Include "net: phy: Fix logic around gmiitorgmii wiring" patch - Update patch on the top of "net: phy: Add clause 45 identifier to phy_device (sha1: b3eabd82f21b4d9206622fc5aee16751d2f4be8f) which adds one more parameter to phy_device_create (bool is_c45) It is quite a long time when I sent v2 on this. There were some changes we found in connection to this driver and it's wiring. DT binding is present here. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Doc… v2 https://lists.denx.de/pipermail/u-boot/2019-January/356777.html v1 https://lists.denx.de/pipermail/u-boot/2018-November/349309.html --- drivers/net/phy/Kconfig | 7 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/phy.c | 42 ++++++++ drivers/net/phy/xilinx_gmii2rgmii.c | 144 ++++++++++++++++++++++++++++ include/phy.h | 6 ++ 5 files changed, 200 insertions(+) create mode 100644 drivers/net/phy/xilinx_gmii2rgmii.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 2a3da068c90a..30bd8e765304 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -228,6 +228,13 @@ config PHY_VITESSE config PHY_XILINX bool "Xilinx Ethernet PHYs support" +config PHY_XILINX_GMII2RGMII + bool "Xilinx GMII to RGMII Ethernet PHYs support" + help + This adds support for Xilinx GMII to RGMII IP core. This IP acts + as bridge between MAC connected over GMII and external phy that + is connected over RGMII interface. + config PHY_FIXED bool "Fixed-Link PHY" depends on DM_ETH diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 555da83630f4..76b6197009bc 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o obj-$(CONFIG_PHY_TI) += ti.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o +obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o obj-$(CONFIG_PHY_MSCC) += mscc.o obj-$(CONFIG_PHY_FIXED) += fixed.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 8c4043445e86..f2d17aa91a07 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -544,6 +544,9 @@ int phy_init(void) #endif #ifdef CONFIG_PHY_FIXED phy_fixed_init(); +#endif +#ifdef CONFIG_PHY_XILINX_GMII2RGMII + phy_xilinx_gmii2rgmii_init(); #endif genphy_init(); @@ -918,6 +921,41 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) debug("%s connected to %s\n", dev->name, phydev->drv->name); } +#ifdef CONFIG_PHY_XILINX_GMII2RGMII +#ifdef CONFIG_DM_ETH +static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, + struct udevice *dev, + phy_interface_t interface) +#else +static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, + struct eth_device *dev, + phy_interface_t interface) +#endif +{ + struct phy_device *phydev = NULL; + int sn = dev_of_offset(dev); + int off; + + while (sn > 0) { + off = fdt_node_offset_by_compatible(gd->fdt_blob, sn, + "xlnx,gmii-to-rgmii-1.0"); + if (off > 0) { + phydev = phy_device_create(bus, off, + PHY_GMII2RGMII_ID, false, + interface); + break; + } + if (off == -FDT_ERR_NOTFOUND) + sn = fdt_first_subnode(gd->fdt_blob, sn); + else + printf("%s: Error finding compat string:%d\n", + __func__, off); + } + + return phydev; +} +#endif + #ifdef CONFIG_PHY_FIXED #ifdef CONFIG_DM_ETH static struct phy_device *phy_connect_fixed(struct mii_dev *bus, @@ -964,6 +1002,10 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, #ifdef CONFIG_PHY_FIXED phydev = phy_connect_fixed(bus, dev, interface); #endif +#ifdef CONFIG_PHY_XILINX_GMII2RGMII + if (!phydev) + phydev = phy_connect_gmii2rgmii(bus, dev, interface); +#endif if (!phydev) phydev = phy_find_by_mask(bus, mask, interface); diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c new file mode 100644 index 000000000000..8c20da268206 --- /dev/null +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx GMII2RGMII phy driver + * + * Copyright (C) 2018 Xilinx, Inc. + */ + +#include <dm.h> +#include <phy.h> +#include <config.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ZYNQ_GMII2RGMII_REG 0x10 +#define ZYNQ_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100) + +static int xilinxgmiitorgmii_config(struct phy_device *phydev) +{ + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + if (ext_phydev->drv->config) + ext_phydev->drv->config(ext_phydev); + + return 0; +} + +static int xilinxgmiitorgmii_extread(struct phy_device *phydev, int addr, + int devaddr, int regnum) +{ + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + if (ext_phydev->drv->readext) + ext_phydev->drv->readext(ext_phydev, addr, devaddr, regnum); + + return 0; +} + +static int xilinxgmiitorgmii_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) + +{ + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + if (ext_phydev->drv->writeext) + ext_phydev->drv->writeext(ext_phydev, addr, devaddr, regnum, + val); + + return 0; +} + +static int xilinxgmiitorgmii_startup(struct phy_device *phydev) +{ + u16 val = 0; + struct phy_device *ext_phydev = phydev->priv; + + debug("%s\n", __func__); + ext_phydev->dev = phydev->dev; + if (ext_phydev->drv->startup) + ext_phydev->drv->startup(ext_phydev); + + val = phy_read(phydev, phydev->addr, ZYNQ_GMII2RGMII_REG); + val &= ~ZYNQ_GMII2RGMII_SPEED_MASK; + + if (ext_phydev->speed == SPEED_1000) + val |= BMCR_SPEED1000; + else if (ext_phydev->speed == SPEED_100) + val |= BMCR_SPEED100; + + phy_write(phydev, phydev->addr, ZYNQ_GMII2RGMII_REG, val | + BMCR_FULLDPLX); + + phydev->duplex = ext_phydev->duplex; + phydev->speed = ext_phydev->speed; + phydev->link = ext_phydev->link; + + return 0; +} + +static int xilinxgmiitorgmii_probe(struct phy_device *phydev) +{ + int ofnode = phydev->addr; + u32 phy_of_handle; + int ext_phyaddr = -1; + struct phy_device *ext_phydev; + + debug("%s\n", __func__); + + if (phydev->interface != PHY_INTERFACE_MODE_GMII) { + printf("Incorrect interface type\n"); + return -EINVAL; + } + + /* + * Read the phy address again as the one we read in ethernet driver + * was overwritten for the purpose of storing the ofnode + */ + phydev->addr = fdtdec_get_int(gd->fdt_blob, ofnode, "reg", -1); + phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, ofnode, + "phy-handle"); + if (phy_of_handle > 0) + ext_phyaddr = fdtdec_get_int(gd->fdt_blob, + phy_of_handle, + "reg", -1); + ext_phydev = phy_find_by_mask(phydev->bus, + 1 << ext_phyaddr, + PHY_INTERFACE_MODE_RGMII); + if (!ext_phydev) { + printf("%s, No external phy device found\n", __func__); + return -EINVAL; + } + + ext_phydev->node = offset_to_ofnode(phy_of_handle); + phydev->priv = ext_phydev; + + debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr, + ext_phyaddr); + + phydev->flags |= PHY_FLAG_BROKEN_RESET; + + return 0; +} + +static struct phy_driver gmii2rgmii_driver = { + .name = "XILINX GMII2RGMII", + .uid = PHY_GMII2RGMII_ID, + .mask = 0xffffffff, + .features = PHY_GBIT_FEATURES, + .probe = xilinxgmiitorgmii_probe, + .config = xilinxgmiitorgmii_config, + .startup = xilinxgmiitorgmii_startup, + .writeext = xilinxgmiitorgmii_extwrite, + .readext = xilinxgmiitorgmii_extread, +}; + +int phy_xilinx_gmii2rgmii_init(void) +{ + phy_register(&gmii2rgmii_driver); + + return 0; +} diff --git a/include/phy.h b/include/phy.h index f4530faeb997..e50f56b6eb16 100644 --- a/include/phy.h +++ b/include/phy.h @@ -17,6 +17,11 @@ #include <phy_interface.h> #define PHY_FIXED_ID 0xa5a55a5a +/* + * There is no actual id for this. + * This is just a dummy id for gmii2rgmmi converter. + */ +#define PHY_GMII2RGMII_ID 0x5a5a5a5a #define PHY_MAX_ADDR 32 @@ -391,6 +396,7 @@ int phy_vitesse_init(void); int phy_xilinx_init(void); int phy_mscc_init(void); int phy_fixed_init(void); +int phy_xilinx_gmii2rgmii_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); -- 2.17.1

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[U-Boot] [PATCH 0/5] ARM: zynq: Boot variables cleanup
by Michal Simek 08 Oct '19

08 Oct '19

Hi, for quite a long time Xilinx was using private boot method. Pretty long time ago we have enabled distribution boot method and provided time to do transition to it. Right now it is good time to remove old methods and move to distro boot fully. It is also the part of unification between Xilinx Zynq/ZynqMP and Versal SoCs to use the same boot methods. This series convert Zynq. Variable modeboot is still setup because Topic boards and Syzygy are using it. Thanks, Michal Michal Simek (5): ARM: zynq: Specify MMC controller number for boot sequence ARM: zynq: Enable USB1 as secondary boot device ARM: zynq: Fix NOR boot mode ARM: zynq: Use {} around variables for qspi and nand boot cmds ARM: zynq: Remove all Xilinx private commands board/xilinx/zynq/board.c | 2 +- include/configs/zynq-common.h | 66 +++++------------------------------ 2 files changed, 10 insertions(+), 58 deletions(-) -- 2.17.1

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[U-Boot] [PATCH] net: phy: Define init routine and register generic phy driver
by Michal Simek 08 Oct '19

08 Oct '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> This patch define init routine for generic phy driver and registers it using phy_register as this generic phy driver also needs to be relocated incase of manual reloc. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/phy.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index ae37dd6c1e37..8c4043445e86 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -458,6 +458,11 @@ static struct phy_driver genphy_driver = { .shutdown = genphy_shutdown, }; +int genphy_init(void) +{ + return phy_register(&genphy_driver); +} + static LIST_HEAD(phy_drivers); int phy_init(void) @@ -540,6 +545,8 @@ int phy_init(void) #ifdef CONFIG_PHY_FIXED phy_fixed_init(); #endif + genphy_init(); + return 0; } -- 2.17.1

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[U-Boot] [PATCH] ARM: zynq: dts: Added alias for usb node
by Michal Simek 08 Oct '19

08 Oct '19

From: Vipul Kumar <vipul.kumar(a)xilinx.com> This patch added alias for usb node in dts file. Signed-off-by: Vipul Kumar <vipul.kumar(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Vipul left Xilinx but he is origin author of this patch that's why I am keeping him here. --- arch/arm/dts/zynq-zc702.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 54231cd5801a..d10695740fa9 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -16,6 +16,7 @@ serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; + usb0 = &usb0; }; memory@0 { -- 2.17.1

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[U-Boot] [PATCH] ARM: zynq: Align model name with DT
by Michal Simek 08 Oct '19

08 Oct '19

Use model property to distinguish different configurations. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynq-cse-qspi-single.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts index 0d680dfc0688..ac6982a74e25 100644 --- a/arch/arm/dts/zynq-cse-qspi-single.dts +++ b/arch/arm/dts/zynq-cse-qspi-single.dts @@ -7,6 +7,10 @@ #include "zynq-cse-qspi.dtsi" +/ { + model = "Zynq CSE QSPI SINGLE Board"; +}; + &flash0 { spi-rx-bus-width = <4>; }; -- 2.17.1

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[U-Boot] [PATCH] arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
by Michal Simek 08 Oct '19

08 Oct '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Add zu48dr and zu49dr to the list of zynqmp devices. The zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b and 0x7e. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f36d49fded99..6524badf299c 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -174,6 +174,14 @@ static const struct { .id = 0x66, .name = "39dr", }, + { + .id = 0x7b, + .name = "48dr", + }, + { + .id = 0x7e, + .name = "49dr", + }, }; #endif -- 2.17.1

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