September 2019 - U-Boot

[U-Boot] [PATCH v4 0/6] power: pmic: support more PMIC
by Elaine Zhang 16 Oct '19

16 Oct '19

Support more PMIC and improve compatibility between pmics. Change in V4: [PATCH v4 1/6]: No change. [PATCH v4 2/6]: No change. [PATCH v4 3/6]: No change. [PATCH v4 4/6]: No change. [PATCH v4 5/6]: Resolve code conflicts after ptach v3 5/8 and 6/8 deletion. [PATCH v4 6/6]: Resolve code conflicts after ptach v3 5/8 and 6/8 deletion. Remove [PATCH v3 5/8] and [PATCH v3 6/8], There is no application scenario. Change in V3: [PATCH v3 1/8]: Add document instructions, Correct error handling. [PATCH v3 2/8]: No change. [PATCH v3 3/8]: No change. [PATCH v3 4/8]: No change. [PATCH v3 5/8]: Update commit message. [PATCH v3 6/8]: Update commit message. [PATCH v3 7/8]: No change. [PATCH v3 8/8]: No change. Change in V2: [PATCH v2 1/8]: Add regulator suspend volatge and en/disable test. [PATCH v2 2/8]: Split the [PATCH v1 2/7], rk808 and rk818 updates. [PATCH v2 3/8]: Split the [PATCH v1 2/7], support rk816 pmic and update commit message. [PATCH v2 4/8]: Update commit message. [PATCH v2 5/8]: No change. [PATCH v2 6/8]: No change. [PATCH v2 7/8]: Remove rk809 keywords and update commit message. [PATCH v2 8/8]: Update commit message. Elaine Zhang (3): power: regulator: rk8xx: update the driver for rk808 and rk818 power: pmic: rk816: support rk816 pmic power: pmic: rk805: support rk805 pmic Joseph Chen (3): dm: regulator: support regulator more state power: pmic: rk817: support rk817 pmic power: pmic: rk809: support rk809 pmic doc/device-tree-bindings/regulator/regulator.txt | 27 + drivers/power/pmic/rk8xx.c | 89 ++- drivers/power/regulator/regulator-uclass.c | 70 ++ drivers/power/regulator/rk8xx.c | 939 +++++++++++++++++++++-- include/power/regulator.h | 64 ++ include/power/rk8xx_pmic.h | 42 + test/dm/regulator.c | 46 ++ 7 files changed, 1189 insertions(+), 88 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 0/5] Add support for MediaTek MT8518 Soc
by mingming lee 15 Oct '19

15 Oct '19

This patch series adds basic boot support on eMMC for the MediaTek MT8518 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. mingming lee (5): ARM: MediaTek: Add support for MediaTek MT8518 SoC clk: mediatek: add driver for MT8518 mmc: mtk-sd: add HS200 support pinctrl: add driver for MT8518 ARM: MediaTek: add basic support for MT8518 boards arch/arm/dts/Makefile | 3 +- arch/arm/dts/mt8518-ap1-emmc.dts | 104 ++ arch/arm/dts/mt8518.dtsi | 210 +++ arch/arm/mach-mediatek/Kconfig | 10 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8518/Makefile | 4 + arch/arm/mach-mediatek/mt8518/init.c | 116 ++ arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 + board/mediatek/mt8518/Kconfig | 14 + board/mediatek/mt8518/MAINTAINERS | 6 + board/mediatek/mt8518/Makefile | 3 + board/mediatek/mt8518/mt8518_ap1.c | 27 + configs/mt8518_ap1_emmc_defconfig | 54 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8518.c | 1558 +++++++++++++++++ drivers/mmc/mtk-sd.c | 30 +- drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 +++++ include/configs/mt8518.h | 73 + include/dt-bindings/clock/mt8518-clk.h | 249 +++ 21 files changed, 2931 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts create mode 100644 arch/arm/dts/mt8518.dtsi create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile create mode 100644 arch/arm/mach-mediatek/mt8518/init.c create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S create mode 100644 board/mediatek/mt8518/Kconfig create mode 100644 board/mediatek/mt8518/MAINTAINERS create mode 100644 board/mediatek/mt8518/Makefile create mode 100644 board/mediatek/mt8518/mt8518_ap1.c create mode 100644 configs/mt8518_ap1_emmc_defconfig create mode 100644 drivers/clk/mediatek/clk-mt8518.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c create mode 100644 include/configs/mt8518.h create mode 100644 include/dt-bindings/clock/mt8518-clk.h -- 2.18.0

4 11

[U-Boot] [PATCH v2 01/20] arch: powerpc: add eSDHC node to p1020 dts
by Yinbo Zhu 15 Oct '19

15 Oct '19

Add eSDHC node to p1020 dts Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- Change in v2: remove the string "This patch is to" from commit information arch/powerpc/dts/p1020-post.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1e5e67804b..fb3b203a24 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -24,6 +24,13 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + esdhc: esdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; }; /* PCIe controller base address 0x9000 */ -- 2.17.1

1 20

[U-Boot] [PATCH 1/4] imx: Place imx_ddr_size() into a separate file
by Fabio Estevam 14 Oct '19

14 Oct '19

Place imx_ddr_size() into a separate file. The motivation for doing this is to be able to easily reuse imx_ddr_size() on i.MX7ULP. Currently imx_ddr_size() is inside arch/arm/mach-imx/cpu.c, which is not built for i.MX7ULP. Changing the logic to allow building cpu.c for i.MX7UP would require adding several ifdef's, leading to a not a very elegant solution. To allow better reuse, just place imx_ddr_size() into a common mmdc_size.c file. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/cpu.c | 53 --------------------------------- arch/arm/mach-imx/mmdc_size.c | 55 +++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 54 deletions(-) create mode 100644 arch/arm/mach-imx/mmdc_size.c diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 898478fc4a..0c8519be94 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -20,7 +20,7 @@ obj-y += cpu.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) -obj-y += cpu.o speed.o +obj-y += cpu.o speed.o mmdc_size.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 3a8cf30c06..0b30ff40cd 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -87,59 +87,6 @@ static char *get_reset_cause(void) } #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) -#if defined(CONFIG_MX53) -#define MEMCTL_BASE ESDCTL_BASE_ADDR -#else -#define MEMCTL_BASE MMDC_P0_BASE_ADDR -#endif -static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; -static const unsigned char bank_lookup[] = {3, 2}; - -/* these MMDC registers are common to the IMX53 and IMX6 */ -struct esd_mmdc_regs { - uint32_t ctl; - uint32_t pdc; - uint32_t otc; - uint32_t cfg0; - uint32_t cfg1; - uint32_t cfg2; - uint32_t misc; -}; - -#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) -#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) -#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) -#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) -#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) - -/* - * imx_ddr_size - return size in bytes of DRAM according MMDC config - * The MMDC MDCTL register holds the number of bits for row, col, and data - * width and the MMDC MDMISC register holds the number of banks. Combine - * all these bits to determine the meme size the MMDC has been configured for - */ -unsigned imx_ddr_size(void) -{ - struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; - unsigned ctl = readl(&mem->ctl); - unsigned misc = readl(&mem->misc); - int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ - - bits += ESD_MMDC_CTL_GET_ROW(ctl); - bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; - bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; - bits += ESD_MMDC_CTL_GET_WIDTH(ctl); - bits += ESD_MMDC_CTL_GET_CS1(ctl); - - /* The MX6 can do only 3840 MiB of DRAM */ - if (bits == 32) - return 0xf0000000; - - return 1 << bits; -} -#endif - #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) const char *get_imx_type(u32 imxtype) diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c new file mode 100644 index 0000000000..8a3c6bdea6 --- /dev/null +++ b/arch/arm/mach-imx/mmdc_size.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <asm/io.h> + +#if defined(CONFIG_MX53) +#define MEMCTL_BASE ESDCTL_BASE_ADDR +#else +#define MEMCTL_BASE MMDC_P0_BASE_ADDR +#endif +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; +static const unsigned char bank_lookup[] = {3, 2}; + +/* these MMDC registers are common to the IMX53 and IMX6 */ +struct esd_mmdc_regs { + uint32_t ctl; + uint32_t pdc; + uint32_t otc; + uint32_t cfg0; + uint32_t cfg1; + uint32_t cfg2; + uint32_t misc; +}; + +#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) +#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) +#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) +#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) +#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) + +/* + * imx_ddr_size - return size in bytes of DRAM according MMDC config + * The MMDC MDCTL register holds the number of bits for row, col, and data + * width and the MMDC MDMISC register holds the number of banks. Combine + * all these bits to determine the meme size the MMDC has been configured for + */ +unsigned imx_ddr_size(void) +{ + struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; + unsigned ctl = readl(&mem->ctl); + unsigned misc = readl(&mem->misc); + int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ + + bits += ESD_MMDC_CTL_GET_ROW(ctl); + bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; + bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; + bits += ESD_MMDC_CTL_GET_WIDTH(ctl); + bits += ESD_MMDC_CTL_GET_CS1(ctl); + + /* The MX6 can do only 3840 MiB of DRAM */ + if (bits == 32) + return 0xf0000000; + + return 1 << bits; +} -- 2.17.1

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[U-Boot] [PATCH v1 0/2] android: colibri_imx7: reserve DDR memory for Cortex-M4
by Igor Opaniuk 14 Oct '19

14 Oct '19

i.MX 7's Cortex-M4 core can run from DDR and uses DDR memory for the rpmsg communication. Both use cases need a fixed location of memory reserved. For the rpmsg use case the reserved area needs to be in sync with the kernel's hardcoded vring descriptor location. Introduce support for adding linux,usable-memory property to carve out 1MB of memory in case the M4 core is running. Also make sure that the i.MX 7 specific rpmsg driver does not get loaded in case we do not carve out memory. Igor Opaniuk (2): common: fdt_support: add support for setting usable memory board: colibri_imx7: reserve DDR memory for Cortex-M4 arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++ board/toradex/colibri_imx7/colibri_imx7.c | 37 +++++++++++++++++++++++ common/fdt_support.c | 35 +++++++++++++++++++++ include/fdt_support.h | 2 ++ 4 files changed, 76 insertions(+) -- 2.17.1

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[U-Boot] [PATCH 1/2] ARM: dts: import meerkat96 board support
by Shawn Guo 14 Oct '19

14 Oct '19

It imports device tree source of meerkat96 board from Linux Kernel. Signed-off-by: Shawn Guo <shawn.guo(a)linaro.org> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx7d-meerkat96.dts | 375 +++++++++++++++++++++++++++++++ 2 files changed, 376 insertions(+) create mode 100644 arch/arm/dts/imx7d-meerkat96.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e0c54bfa767e..4a37c661c441 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -598,6 +598,7 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7-colibri-emmc.dtb \ imx7-colibri-rawnand.dtb \ imx7s-warp.dtb \ + imx7d-meerkat96.dtb \ imx7d-pico-pi.dtb \ imx7d-pico-hobbit.dtb diff --git a/arch/arm/dts/imx7d-meerkat96.dts b/arch/arm/dts/imx7d-meerkat96.dts new file mode 100644 index 000000000000..dd8003bd1fc0 --- /dev/null +++ b/arch/arm/dts/imx7d-meerkat96.dts @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Linaro Ltd. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "96Boards Meerkat96 Board"; + compatible = "novtech,imx7d-meerkat96", "fsl,imx7d"; + + chosen { + stdout-path = &uart6; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MB */ + }; + + reg_wlreg_on: regulator-wlreg-on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlreg_on>; + regulator-name = "wlreg_on"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "green:user1"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led5 { + label = "yellow:wlan"; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led6 { + label = "blue:bt"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7 &pinctrl_bt_gpios>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + device-wakeup-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbotg1 { + vbus-supply = <&reg_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <&reg_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + keep-power-in-suspend; + fsl,tuning-step = <2>; + vmmc-supply = <&reg_3p3v>; + no-1-8-v; + broken-cd; + status = "okay"; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + no-1-8-v; + no-mmc; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&reg_wlreg_on>; + vqmmc-supply =<&reg_3p3v>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_irq>; + interrupt-parent = <&gpio6>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_bt_gpios: btgpiosgrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x1f + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59 + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x79 + MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x79 + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x79 + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x79 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x79 + MX7D_PAD_SD1_WP__UART6_DCE_TX 0x79 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x79 + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x79 + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x79 + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x0D + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + >; + }; + + pinctrl_wlan_irq: wlanirqgrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x19 + >; + }; + + pinctrl_wlreg_on: wlregongrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x19 + >; + }; +}; -- 2.18.0

4 7

[U-Boot] [PATCH] imx :hab: Add hab version command
by Sjoerd Simons 14 Oct '19

14 Oct '19

THe RVT data includes a major and minor version in its header parameter. Add a new command to print this out. Signed-off-by: Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> --- Unfortunately there doesn't seem to be a way to get the minor version of the hab ROM. While there is a get_version function pointer in the vector table it's documented to only be valid during the ROM phase and a quick hack to try and call it on my board always returned 1 :/. arch/arm/include/asm/mach-imx/hab.h | 1 + arch/arm/mach-imx/hab.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index 95df88423c..5c82a148b4 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -189,6 +189,7 @@ typedef void hapi_clock_init_t(void); #define HAB_CID_ROM 0 /**< ROM Caller ID */ #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ +#define HAB_TAG_RVT 0xDD /* ROM Vector Table */ #define HAB_CMD_HDR 0xD4 /* CSF Header */ #define HAB_CMD_WRT_DAT 0xCC /* Write Data command tag */ #define HAB_CMD_CHK_DAT 0xCF /* Check Data command tag */ diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d42a15e877..e8487932c0 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -365,6 +365,21 @@ static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc, return 0; } +static int do_hab_version(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct hab_hdr *hdr = (struct hab_hdr *)HAB_RVT_BASE; + + if (hdr->tag != HAB_TAG_RVT) { + printf("Unexpected header tag: %x\n", hdr->tag); + return CMD_RET_FAILURE; + } + + printf("HAB version: %d.%d\n", hdr->par >> 4, hdr->par & 0xf); + + return 0; +} + static int do_authenticate_image_or_failover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -421,6 +436,12 @@ U_BOOT_CMD( "ivt_offset - hex offset of IVT in the image" ); +U_BOOT_CMD( + hab_version, 1, 0, do_hab_version, + "print HAB major/minor version", + "" + ); + #endif /* !defined(CONFIG_SPL_BUILD) */ /* Get CSF Header length */ -- 2.20.1

2 1

[U-Boot] [PATCH 1/2] mx6: mx6sabre common: Use more conventional spelling of fdtfile
by Sjoerd Simons 14 Oct '19

14 Oct '19

Both the distro boot configuration as well as the general pxe support standardized on fdtfile as the variable to hold the dtb filename. Adjust to follow that such that e.g. "pxe boot" will just work. Signed-off-by: Sjoerd Simons <sjoerd.simons(a)collabora.co.uk> --- include/configs/mx6sabre_common.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c137612b01..270cd2bae2 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -51,7 +51,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ - "fdt_file=undefined\0" \ + "fdtfile=undefined\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -86,7 +86,7 @@ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run finduuid; " \ "run mmcargs; " \ @@ -115,7 +115,7 @@ "fi; " \ "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ @@ -128,20 +128,20 @@ "bootz; " \ "fi;\0" \ "findfdt="\ - "if test $fdt_file = undefined; then " \ + "if test $fdtfile = undefined; then " \ "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ - "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \ + "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ - "setenv fdt_file imx6q-sabreauto.dtb; fi; " \ + "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ - "setenv fdt_file imx6dl-sabreauto.dtb; fi; " \ + "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ - "setenv fdt_file imx6qp-sabresd.dtb; fi; " \ + "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ - "setenv fdt_file imx6q-sabresd.dtb; fi; " \ + "setenv fdtfile imx6q-sabresd.dtb; fi; " \ "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ - "setenv fdt_file imx6dl-sabresd.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ + "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; " \ "fi;\0" \ -- 2.20.1

3 4

[U-Boot] [PATCH v2] rockchip: rk3399: Add Leez P710 support
by Andyshrk 14 Oct '19

14 Oct '19

From: Andy Yan <andyshrk(a)gmail.com> Specification - Rockchip RK3399 - LPDDR4 - TF sd scard slot - eMMC - M.2 B-Key for 4G LTE - AP6256 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - TYPE-C Power supply Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1: "arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC" (sha1: fc702ed49a8668a17343811ee28214d845bfc5e6) Signed-off-by: Andy Yan <anyshrk(a)gmail.com> --- Changes in v2: - Update board/rockchip/evb_rk3399/MAINTAINERS file - Add Linux dts sync commit details as Jagan's wish arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-leez-p710-u-boot.dtsi | 13 + arch/arm/dts/rk3399-leez-p710.dts | 645 ++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 + configs/leez-rk3399_defconfig | 58 ++ 5 files changed, 723 insertions(+) create mode 100644 arch/arm/dts/rk3399-leez-p710-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-leez-p710.dts create mode 100644 configs/leez-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 62da168ef86..dbb062edda6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-khadas-edge.dtb \ rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ + rk3399-leez-p710.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-neo4.dtb \ diff --git a/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi new file mode 100644 index 00000000000..f8b2a1d56e7 --- /dev/null +++ b/arch/arm/dts/rk3399-leez-p710-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Andy Yan <andy.yan(a)gmail.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; diff --git a/arch/arm/dts/rk3399-leez-p710.dts b/arch/arm/dts/rk3399-leez-p710.dts new file mode 100644 index 00000000000..32baa57b948 --- /dev/null +++ b/arch/arm/dts/rk3399-leez-p710.dts @@ -0,0 +1,645 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Andy Yan <andy.yan(a)gmail.com> + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Leez RK3399 P710"; + compatible = "leez,p710", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + dc5v_adp: dc5v-adp { + compatible = "regulator-fixed"; + regulator-name = "dc5v_adapter"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc5v_adp>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host0: vcc5v0_host1: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host3: vcc5v0-host3 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host3"; + enable-active-high; + gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host3_en>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lan: vcc3v3-lan { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vim-supply = <&vcc3v3_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc0v9_hdmi: LDO_REG7 { + regulator-name = "vcc0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + vcc5v0_host3_en: vcc5v0-host3-en { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; + + vref-supply = <&vcc_1v8>; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + status = "okay"; + + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host0>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host1>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index f8299d94601..139791795ec 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -24,6 +24,12 @@ S: Maintained F: configs/khadas-edge-v-rk3399_defconfig F: arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi +LEEZ-P710 +M: Andy Yan <andy.yan(a)rock-chips.com> +S: Maintained +F: arch/arm/dts/rk3399-leez-p710-u-boot.dtsi +F: configs/leez-rk3399_defconfig + NANOPC-T4 M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig new file mode 100644 index 00000000000..4757aaaec44 --- /dev/null +++ b/configs/leez-rk3399_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.17.1

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[U-Boot] [PATCH] configs: apalis-tk1: Do not define CONFIG_SYS_BOOT_RAMDISK_HIGH again
by Michal Simek 14 Oct '19

14 Oct '19

CONFIG_SYS_BOOT_RAMDISK_HIGH is already defined in arch/arm/include/asm/config.h:10:#define CONFIG_SYS_BOOT_RAMDISK_HIGH that's why there is no reason to define it again in board file. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/apalis-tk1.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index dacf36bf79c8..fe45917b885d 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -138,8 +138,6 @@ #define CONFIG_CMD_TIME -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -- 2.17.1

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