July 2019 - U-Boot

[U-Boot] [PATCH 0/4] davinci: omapl138-lcdk: enable CONFIG_SPL_DM
by Bartosz Golaszewski 03 Jul '19

03 Jul '19

From: Bartosz Golaszewski <bgolaszewski(a)baylibre.com> This series enables the driver model in SPL on omapl138-lcdk. First two patches enable size-reducing options in defconfig. The third patch is just a cleanup of the board file. Last patch enables the driver model and defines the serial device so that we don't have to disable CONFIG_SPL_DM_SERIAL which is enabled by default when selecting CONFIG_SPL_DM. Bartosz Golaszewski (4): davinci: omapl138-lcdk: enable SPL_SYS_MALLOC_SIMPLE davinci: omapl138-lcdk: enable CONFIG_USE_TINY_PRINTF davinci: omapl138-lcdk: remove unneeded includes davinci: omapl138-lcdk: enable driver-model in SPL board/davinci/da8xxevm/omapl138_lcdk.c | 18 ++++++++++++++++-- configs/omapl138_lcdk_defconfig | 7 +++++++ 2 files changed, 23 insertions(+), 2 deletions(-) -- 2.21.0

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[U-Boot] [PATCH] watchdog: mtk_wdt: Cosmetic cleanup of latest changes
by Stefan Roese 03 Jul '19

03 Jul '19

This patch cleans up some coding style related issues in the mtk_wtd driver to make this driver comply again with the U-Boot coding style standards. The only minimal functional change is that the timeout parameter is now passed in (u64) instead of (unsigned int) from mtk_wdt_start() to mtk_wdt_set_timeout(), preserving the original value. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Shannon Barber <sbarber(a)dataspeedinc.com> Cc: Ryder Lee <ryder.lee(a)mediatek.com> Cc: Matthias Brugger <matthias.bgg(a)gmail.com> Cc: Frank Wunderlich <frank-w(a)public-files.de> --- drivers/watchdog/mtk_wdt.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index a7d4c7a3b8..dafd2b56a8 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -70,9 +70,12 @@ static int mtk_wdt_expire_now(struct udevice *dev, ulong flags) return 0; } -static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms) +static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) { struct mtk_wdt_priv *priv = dev_get_priv(dev); + u64 timeout_us; + u32 timeout_cc; + u32 length; /* * One WDT_LENGTH count is 512 ticks of the wdt clock @@ -88,21 +91,25 @@ static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms) * The MediaTek docs lack details to know if this is the case here. * So we enforce a minimum of 1 to guarantee operation. */ - if(timeout_ms > 15984) timeout_ms = 15984; - u64 timeout_us = timeout_ms * 1000; - u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 ); - if(timeout_cc == 0) timeout_cc = 1; - u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY; + if (timeout_ms > 15984) + timeout_ms = 15984; + + timeout_us = timeout_ms * 1000; + timeout_cc = (15624 + timeout_us) / 15625; + if (timeout_cc == 0) + timeout_cc = 1; + + length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY; writel(length, priv->base + MTK_WDT_LENGTH); } -static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct mtk_wdt_priv *priv = dev_get_priv(dev); - mtk_wdt_set_timeout(dev, timeout); + mtk_wdt_set_timeout(dev, timeout_ms); - mtk_wdt_reset(dev); + mtk_wdt_reset(dev); /* Enable watchdog reset signal */ setbits_le32(priv->base + MTK_WDT_MODE, -- 2.22.0

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[U-Boot] [PATCH] ARM: imx6: DHCOM i.MX6 PDK: Switch to DM for I2C
by Ludwig Zenz 03 Jul '19

03 Jul '19

This patch enables DM I2C for DHCOM i.MX6 PDK2 boards and removes non DM I2C code. Tested with DHCOM i.MX6dl and DHCOM i.MX6q. Signed-off-by: Ludwig Zenz <lzenz(a)dh-electronics.com> --- board/dhelectronics/dh_imx6/dh_imx6.c | 105 ++-------------------------------- configs/dh_imx6_defconfig | 7 +++ include/configs/dh_imx6.h | 8 --- 3 files changed, 13 insertions(+), 107 deletions(-) diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index cca8e832ec..b2a574f0cf 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -36,92 +36,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define I2C_PAD_CTRL \ - (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define EEPROM_I2C_ADDRESS 0x50 -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -static struct i2c_pads_info dh6sdl_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -static struct i2c_pads_info dh6sdl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info dh6sdl_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -static struct i2c_pads_info dh6dq_i2c_pad_info0 = { - .scl = { - .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, - .gp = IMX_GPIO_NR(3, 21) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, - .gp = IMX_GPIO_NR(3, 28) - } -}; - -static struct i2c_pads_info dh6dq_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info dh6dq_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -214,6 +130,7 @@ int board_usb_phy_mode(int port) static int setup_dhcom_mac_from_fuse(void) { + struct udevice *dev; unsigned char enetaddr[6]; int ret; @@ -228,13 +145,14 @@ static int setup_dhcom_mac_from_fuse(void) return 0; } - ret = i2c_set_bus_num(2); +#ifdef CONFIG_SYS_I2C_MXC_I2C3 + ret = i2c_get_chip_for_busnum(2, EEPROM_I2C_ADDRESS, 1, &dev); if (ret) { - printf("Error switching I2C bus!\n"); + printf("Cannot find EEPROM!\n"); return ret; } - ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6); + ret = dm_i2c_read(dev, 0xfa, enetaddr, 0x6); if (ret) { printf("Error reading configuration EEPROM!\n"); return ret; @@ -242,6 +160,7 @@ static int setup_dhcom_mac_from_fuse(void) if (is_valid_ethaddr(enetaddr)) eth_env_set_enetaddr("ethaddr", enetaddr); +#endif return 0; } @@ -265,18 +184,6 @@ int board_init(void) /* Enable eim_slow clocks */ setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); -#ifdef CONFIG_SYS_I2C_MXC - if (is_mx6dq()) { - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2); - } else { - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2); - } -#endif - setup_dhcom_mac_from_fuse(); return 0; diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 4734ed76e5..b0749a054f 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -48,6 +48,13 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 3b1d0a99a1..7d2e573846 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -48,14 +48,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_ARP_TIMEOUT 200UL -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* MMC Configs */ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -- 2.11.0

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[U-Boot] Fix read error in fsl_qspi driver
by Thomas Schaefer 03 Jul '19

03 Jul '19

Hi all, The following patchset will fix QSPI flash read error discovered on i.MX7D Sabre eval system. Could you please check and apply to upcoming v2019.07 release? Best regards, Thomas Schaefer [PATCH 1/2] drivers/spi: fsl_qspi: fix read timeout [PATCH 2/2] drivers/spi: fsl_qspi: improve timeout calculation

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[U-Boot] Boot rootfs from FIT Image
by deepakpradhan 03 Jul '19

03 Jul '19

HI, I am using fitimage to load kernel dtb and rootfs. However the kernel and dtb files are getting loaded but the rootfs is loading from the /dev/mmcblk0p4 partition. I need to load the rootfs from FIT image and I don't know what should be the uboot command line args for this. What I have to pass to uboot so that the rootfs should be loaded from fit image? root="?" currently root=/dev/mmcblk0p4 Any help will be appreciable. Thanks in advance. -- Sent from: http://u-boot.10912.n7.nabble.com/

1 0

[U-Boot] [PATCH v3 0/6] ls1028a: networking support
by Alex Marginean 03 Jul '19

03 Jul '19

This patch set introduces ENETC ethernet and MDIO drivers, integrated in LS1028A NXP device and enables networking on the two existing boards. The SGMII interface labeled MAC0 is now functional on the reference design board (RDB). The RDB also features four switch ports, not enabled yet. On the development system (QDS) the RGMII port is now functional. Add-on cards are not yet enabled. Depends on: - DM MDIO: https://patchwork.ozlabs.org/patch/1109368/ - PCI EA and FLR: https://patchwork.ozlabs.org/patch/1111608/ Changes in v3: - Added cover letter - Added serdes (SoC internal PHYs) configuration code - Use a single config option for ethernet and MDIO drivers as they are cross dependent - Use net_rx_packets for Rx and set SYS_RX_ETH_BUFFER to 8, minimum BD ring size supported by ENETC - MDIO driver now resides in its own file, read/write functions are reused by ethernet driver to access serdes - PCI IDs for our functions are no longer defined in pci_ids.h - several cosmetic updates, static functions, comments Alex Marginean (6): include: configs: ls1028a: set SYS_RX_ETH_BUFFER to 8 drivers: net: add NXP ENETC ethernet driver drivers: net: add NXP ENETC MDIO driver drivers: net: apply serdes configuration for ENETC Ethernet interfaces arm: dts: ls1028a updates for network interfaces configs: ls1028a: enable networking options in rds, qds defconfig arch/arm/dts/fsl-ls1028a-qds.dts | 13 + arch/arm/dts/fsl-ls1028a-rdb.dts | 13 + arch/arm/dts/fsl-ls1028a.dtsi | 24 ++ configs/ls1028aqds_tfa_defconfig | 5 +- configs/ls1028ardb_tfa_defconfig | 2 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/fsl_enetc.c | 583 +++++++++++++++++++++++++++++++ drivers/net/fsl_enetc.h | 227 ++++++++++++ drivers/net/fsl_enetc_mdio.c | 149 ++++++++ include/configs/ls1028a_common.h | 4 + 11 files changed, 1027 insertions(+), 1 deletion(-) create mode 100644 drivers/net/fsl_enetc.c create mode 100644 drivers/net/fsl_enetc.h create mode 100644 drivers/net/fsl_enetc_mdio.c -- 2.17.1

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[U-Boot] [PATCH 1/2] usb: musb-new: Add DA8xx MUSB Glue and enable Host mode
by Adam Ford 03 Jul '19

03 Jul '19

The da8xx can support the MUSB OTG controller. This patch enables it in host mode. There is still work to do for device/OTG, but this has been broken for a while, so host-only is still better than nothing at all. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index 75005ccdd1..79ad14ef66 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -18,6 +18,14 @@ config USB_MUSB_GADGET help Enables the MUSB USB dual-role controller in gadget mode. +config USB_MUSB_DA8XX + bool "Enable DA8xx MUSB Controller" + depends on DM_USB + help + Say y here to enable support for the dual role high + speed USB controller based on the Mentor Graphics + silicon IP. + config USB_MUSB_TI bool "Enable TI OTG USB controller" depends on DM_USB diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile index 4eca0e5631..ec7852ce94 100644 --- a/drivers/usb/musb-new/Makefile +++ b/drivers/usb/musb-new/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_USB_MUSB_GADGET) += musb_gadget.o musb_gadget_ep0.o musb_core.o obj-$(CONFIG_USB_MUSB_GADGET) += musb_uboot.o obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o +obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o diff --git a/drivers/usb/musb-new/da8xx.c b/drivers/usb/musb-new/da8xx.c new file mode 100644 index 0000000000..3e65c14cae --- /dev/null +++ b/drivers/usb/musb-new/da8xx.c @@ -0,0 +-2,466 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments da8xx "glue layer" + * + * Copyright (c) 2010, by Texas Instruments + * + * Based on the DA8xx "glue layer" code. + * Copyright (c) 2008-2009, MontaVista Software, Inc. <source(a)mvista.com> + * + * This file is part of the Inventra Controller Driver for Linux. + * + */ + +#include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <asm/arch/hardware.h> +#include <asm/arch/da8xx-usb.h> +#include <linux/usb/otg.h> +#include <asm/omap_musb.h> +#include "linux-compat.h" +#include "musb_core.h" +#include "musb_uboot.h" + +/* + * DA8XX specific definitions + */ + +/* USB 2.0 OTG module registers */ +#define DA8XX_USB_REVISION_REG 0x00 +#define DA8XX_USB_CTRL_REG 0x04 +#define DA8XX_USB_STAT_REG 0x08 +#define DA8XX_USB_EMULATION_REG 0x0c +#define DA8XX_USB_SRP_FIX_TIME_REG 0x18 +#define DA8XX_USB_INTR_SRC_REG 0x20 +#define DA8XX_USB_INTR_SRC_SET_REG 0x24 +#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28 +#define DA8XX_USB_INTR_MASK_REG 0x2c +#define DA8XX_USB_INTR_MASK_SET_REG 0x30 +#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34 +#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38 +#define DA8XX_USB_END_OF_INTR_REG 0x3c +#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2)) + +/* Control register bits */ +#define DA8XX_SOFT_RESET_MASK 1 + +#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */ +#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */ + +/* USB interrupt register bits */ +#define DA8XX_INTR_USB_SHIFT 16 +#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */ + /* interrupts and DRVVBUS interrupt */ +#define DA8XX_INTR_DRVVBUS 0x100 +#define DA8XX_INTR_RX_SHIFT 8 +#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT) +#define DA8XX_INTR_TX_SHIFT 0 +#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT) + +#define DA8XX_MENTOR_CORE_OFFSET 0x400 + +static irqreturn_t da8xx_musb_interrupt(int irq, void *hci) +{ + struct musb *musb = hci; + void __iomem *reg_base = musb->ctrl_base; + unsigned long flags; + irqreturn_t ret = IRQ_NONE; + u32 status; + + debug("da8xx_musb_interrupt\n"); + + spin_lock_irqsave(&musb->lock, flags); + + /* + * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through + * the Mentor registers (except for setup), use the TI ones and EOI. + */ + + /* Acknowledge and handle non-CPPI interrupts */ + status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); + if (!status) + goto eoi; + + musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); + dev_dbg(musb->controller, "USB IRQ %08x\n", status); + + musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT; + musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT; + musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT; + + /* + * DRVVBUS IRQs are the only proxy we have (a very poor one!) for + * DA8xx's missing ID change IRQ. We need an ID change IRQ to + * switch appropriately between halves of the OTG state machine. + * Managing DEVCTL.Session per Mentor docs requires that we know its + * value but DEVCTL.BDevice is invalid without DEVCTL.Session set. + * Also, DRVVBUS pulses for SRP (but not at 5 V)... + */ + if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) { + int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); + void __iomem *mregs = musb->mregs; + u8 devctl = musb_readb(mregs, MUSB_DEVCTL); + int err; + + err = musb->int_usb & MUSB_INTR_VBUSERROR; + if (err) { + /* + * The Mentor core doesn't debounce VBUS as needed + * to cope with device connect current spikes. This + * means it's not uncommon for bus-powered devices + * to get VBUS errors during enumeration. + * + * This is a workaround, but newer RTL from Mentor + * seems to allow a better one: "re"-starting sessions + * without waiting for VBUS to stop registering in + * devctl. + */ + musb->int_usb &= ~MUSB_INTR_VBUSERROR; + //musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; + //mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ); + WARNING("VBUS error workaround (delay coming)\n"); + } else if (drvvbus) { + MUSB_HST_MODE(musb); + //musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; + //portstate(musb->port1_status |= USB_PORT_STAT_POWER); + //del_timer(&musb->dev_timer); + } else if (!(musb->int_usb & MUSB_INTR_BABBLE)) { + /* + * When babble condition happens, drvvbus interrupt + * is also generated. Ignore this drvvbus interrupt + * and let babble interrupt handler recovers the + * controller; otherwise, the host-mode flag is lost + * due to the MUSB_DEV_MODE() call below and babble + * recovery logic will not be called. + */ + musb->is_active = 0; + MUSB_DEV_MODE(musb); + //musb->xceiv->otg->state = OTG_STATE_B_IDLE; + //portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); + } +#if 0 + dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", + drvvbus ? "on" : "off", + usb_otg_state_string(musb->xceiv->otg->state), + err ? " ERROR" : "", + devctl); +#endif + ret = IRQ_HANDLED; + } + + if (musb->int_tx || musb->int_rx || musb->int_usb) + ret |= musb_interrupt(musb); +eoi: + /* EOI needs to be written for the IRQ to be re-asserted. */ + if (ret == IRQ_HANDLED || status) + musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); + + spin_unlock_irqrestore(&musb->lock, flags); + + return ret; +} + +static void enable_vbus(void) +{ + u32 value; + +#if 0 + gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset"); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on); + + /* configure GPIO bank4 pin 15 in output direction */ + value = readl(&davinci_gpio_bank45->dir); + writel((value & (~DA8XX_USB_VBUS_GPIO)), &davinci_gpio_bank45->dir); + + /* set GPIO bank4 pin 15 high to drive VBUS */ + value = readl(&davinci_gpio_bank45->set_data); + writel((value | DA8XX_USB_VBUS_GPIO), &davinci_gpio_bank45->set_data); +#endif +} + +/* + * Enable the usb0 phy. This initialization procedure is explained in + * the DA8xx USB user guide document. + */ +static u8 phy_on(void) +{ + u32 timeout; + u32 cfgchip2; + + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + + cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | + CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ); + cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | + CFGCHIP2_REFFREQ_24MHZ; + + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); + + /* wait until the usb phy pll locks */ + timeout = 0x3FFFFFF; //musb_cfg.timeout; + while (timeout--) + if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) + return 1; + + debug("Phy was not turned on\n"); + /* USB phy was not turned on */ + return 0; +} + +/* + * Disable the usb phy + */ +static void phy_off(void) +{ + u32 cfgchip2; + + /* + * Power down the on-chip PHY. + */ + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + cfgchip2 &= ~CFGCHIP2_PHY_PLLON; + cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN; + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); +} + +static void da8xx_musb_phy_power(struct udevice *dev, u8 on) +{ + unsigned long start = get_timer(0); + + if (on) + phy_on(); + else + phy_off(); +} + +static int da8xx_musb_init(struct musb *musb) +{ + u32 revision; + void __iomem *reg_base = musb->ctrl_base; + + /* enable psc for usb2.0 */ + lpsc_on(33); + + /* enable usb vbus */ + enable_vbus(); + + /* reset the controller */ + writel(0x1, &da8xx_usb_regs->control); + udelay(5000); + + /* start the on-chip usb phy and its pll */ + if (phy_on() == 0) { + return -1; + } + + /* Returns zero if e.g. not clocked */ + revision = readl(&da8xx_usb_regs->revision); + if (revision == 0) { + return -1; + } + + /* Disable all interrupts */ + writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | + DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set); + + musb->mregs += DA8XX_MENTOR_CORE_OFFSET; + + /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ + debug("DA8xx OTG revision %08x, control %02x\n", revision, + musb_readb(reg_base, DA8XX_USB_CTRL_REG)); + + musb->isr = da8xx_musb_interrupt; + return 0; +} + +static int da8xx_musb_exit(struct musb *musb) +{ + /* Turn of the phy */ + phy_off(); + + /* flush any interrupts */ + writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | + DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr); + writel(0, &da8xx_usb_regs->eoi); + + return 0; +} + +/** + * da8xx_musb_enable - enable interrupts + */ +static int da8xx_musb_enable(struct musb *musb) +{ + void __iomem *reg_base = musb->ctrl_base; + u32 mask; + + /* Workaround: setup IRQs through both register sets. */ + mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) | + ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) | + DA8XX_INTR_USB_MASK; + musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); + + /* Force the DRVVBUS IRQ so we can start polling for ID change. */ + musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, + DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT); + + return 0; +} + +/** + * da8xx_musb_disable - disable HDRC and flush interrupts + */ +static void da8xx_musb_disable(struct musb *musb) +{ + void __iomem *reg_base = musb->ctrl_base; + + musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, + DA8XX_INTR_USB_MASK | + DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK); + musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); +} + +void da8xx_musb_reset(struct udevice *dev) +{ + void *reg_base = dev_read_addr_ptr(dev); + /* Reset the controller */ + musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); +} + +void da8xx_musb_clear_irq(struct udevice *dev) +{ + /* flush any interrupts */ + writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | + DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr); + writel(0, &da8xx_usb_regs->eoi); +} + +const struct musb_platform_ops da8xx_ops = { + .init = da8xx_musb_init, + .exit = da8xx_musb_exit, + .enable = da8xx_musb_enable, + .disable = da8xx_musb_disable, +}; + +#if CONFIG_IS_ENABLED(DM_USB) + +struct da8xx_musb_platdata { + void *base; + void *ctrl_mod_base; + struct musb_hdrc_platform_data plat; + struct musb_hdrc_config musb_config; + struct omap_musb_board_data otg_board_data; +}; + +static int da8xx_musb_ofdata_to_platdata(struct udevice *dev) +{ + struct da8xx_musb_platdata *platdata = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); + + platdata->base = (void *)dev_read_addr_ptr(dev); + platdata->musb_config.multipoint = 1; + platdata->musb_config.dyn_fifo = 1; + platdata->musb_config.num_eps = 5; + platdata->musb_config.ram_bits = 10; + platdata->plat.power = fdtdec_get_int(fdt, node, + "power", -1); + if (platdata->plat.power < 0) { + platdata->plat.power = 50; /* If power isn't specified, assume 50mA */ + } + + platdata->otg_board_data.interface_type = MUSB_INTERFACE_UTMI; + +#if 0 /* In a perfect world, mode would be set to OTG, mode 3 from DT */ + platdata->plat.mode = fdtdec_get_int(fdt, node, + "mode", -1); + if (platdata->plat.mode < 0) { + pr_err("MUSB mode DT entry missing\n"); + return -ENOENT; + } +#else /* MUSB_OTG, it doesn't work */ +#ifdef CONFIG_USB_MUSB_HOST /* Host seems to be the only option that works */ + platdata->plat.mode = MUSB_HOST; +#else /* For that matter, MUSB_PERIPHERAL doesn't either */ + platdata->plat.mode = MUSB_PERIPHERAL; +#endif +#endif + platdata->otg_board_data.dev = dev; + platdata->plat.config = &platdata->musb_config; + platdata->plat.platform_ops = &da8xx_ops; + platdata->plat.board_data = &platdata->otg_board_data; + platdata->otg_board_data.set_phy_power = da8xx_musb_phy_power; + platdata->otg_board_data.clear_irq = da8xx_musb_clear_irq; + platdata->otg_board_data.reset = da8xx_musb_reset; + return 0; +} + +static int da8xx_musb_probe(struct udevice *dev) +{ +#ifdef CONFIG_USB_MUSB_HOST + struct musb_host_data *host = dev_get_priv(dev); +#endif + struct da8xx_musb_platdata *platdata = dev_get_platdata(dev); + struct usb_bus_priv *priv = dev_get_uclass_priv(dev); + struct omap_musb_board_data *otg_board_data; + int ret; + void *base = dev_read_addr_ptr(dev); + + priv->desc_before_addr = true; + + otg_board_data = &platdata->otg_board_data; + +#ifdef CONFIG_USB_MUSB_HOST + host->host = musb_init_controller(&platdata->plat, + (struct device *)otg_board_data, + platdata->base); + if (!host->host) { + return -EIO; + } + + ret = musb_lowlevel_init(host); +#else + ret = musb_register(&platdata->plat, + (struct device *)otg_board_data, + platdata->base); +#endif + return ret; +} + +static int da8xx_musb_remove(struct udevice *dev) +{ + struct musb_host_data *host = dev_get_priv(dev); + + musb_stop(host->host); + + return 0; +} + +static const struct udevice_id da8xx_musb_ids[] = { + { .compatible = "ti,da830-musb" }, + { } +}; + +U_BOOT_DRIVER(da8xx_musb) = { + .name = "da8xx-musb", +#ifdef CONFIG_USB_MUSB_HOST + .id = UCLASS_USB, +#else + .id = UCLASS_USB_GADGET_GENERIC, +#endif + .of_match = da8xx_musb_ids, + .ofdata_to_platdata = da8xx_musb_ofdata_to_platdata, + .probe = da8xx_musb_probe, + .remove = da8xx_musb_remove, +#ifdef CONFIG_USB_MUSB_HOST + .ops = &musb_usb_ops, +#endif + .platdata_auto_alloc_size = sizeof(struct da8xx_musb_platdata), + .priv_auto_alloc_size = sizeof(struct musb_host_data), +}; + +#endif /* CONFIG_IS_ENABLED(DM_USB) */ + -- 2.17.1

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[U-Boot] Pull request: u-boot-rockchip/tags/rockchip-for-v2019.07-rc5-2
by Kever Yang 02 Jul '19

02 Jul '19

Hi Tom, Please pull some rockchip updates: - fix for atf bl31_image_info pointer - fix for rockpro64 vdd_log init - fix for tinker-rk3288 SPL size too big https://travis-ci.org/keveryang/u-boot/builds/553096186 Thanks, - Kever The following changes since commit 8c2d42d526574a6d972d7711660b652d2aeba7e1: poplar: increase SYS_MALLOC_F_LEN for DM_FLAG_PRE_RELOC support (2019-07-01 09:35:56 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git tags/rockchip-for-v2019.07-rc5-2 for you to fetch changes up to 665ebcadd69b8d3ebce946709e23f0df0bee7b56: rockchip: rk3288: enable TPL for tinker-board (2019-07-02 11:49:49 +0800) ---------------------------------------------------------------- Frieder Schrempf (1): spl: atf: Fix uninitialized pointer to bl31_image_info Kever Yang (8): rockchip: rk3288: enable TPL configs to chip level rockchip: rk3288: add separate TPL STACK address rockchip: dts: rk3288: move reloc tag into -u-boot dts rockchip: dts: tinker: migrate the dm-pre-reloc tag into -u-boot dts rockchip: dts: rk3288-tinker: enable sdmmc pinctrl node in spl rockchip: config: update config for TPL support on tinker-rk3288 rockchip: config: tiner-rk3288: extend CONFIG_SYS_MONITOR_LEN to 600KB rockchip: rk3288: enable TPL for tinker-board Mark Kettenis (1): rockchip: dts: rk3399: rockpro64: Provide init voltage arch/arm/dts/rk3288-tinker-u-boot.dtsi | 54 +++++++++++++++++++++++++++ arch/arm/dts/rk3288-tinker.dts | 19 ---------- arch/arm/dts/rk3288-u-boot.dtsi | 36 ++++++++++++++++++ arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 2 + arch/arm/dts/rk3288-vyasa-u-boot.dtsi | 2 + arch/arm/dts/rk3288.dtsi | 8 ---- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 4 ++ arch/arm/mach-rockchip/Kconfig | 18 +++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 15 +------- common/spl/spl_atf.c | 1 + configs/tinker-rk3288_defconfig | 13 +++---- include/configs/tinker_rk3288.h | 1 + 12 files changed, 124 insertions(+), 49 deletions(-) create mode 100644 arch/arm/dts/rk3288-tinker-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-u-boot.dtsi

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[U-Boot] [BUG] Wandboard fails to boot via U-Boot bootefi, GRUB
by Heinrich Schuchardt 02 Jul '19

02 Jul '19

Hello Leif, the Wandboard Quad rev B1 cannot be booted via U-Boot, GRUB-efi-arm. GRUB loads the initial ramdisk into an area which the the mainline 4.19.55 kernel simply does not accept because it thinks the minimum address is 0x68000000 and not 0x10000000. Booting via bootz works without problem. Did you see a similar problems before? This is the memory map when it is last read from U-Boot. typ, phys, virt, pages, attrib 00000002, 8f797000, 8f797000, 869, 8 00000005, 8f796000, 8f796000, 1, 8000000000000008 00000002, 8dd8c000, 8dd8c000, 1a0a, 8 00000000, 8dd8b000, 8dd8b000, 1, 8 00000006, 8dd8a000, 8dd8a000, 1, 8000000000000008 00000000, 8dd83000, 8dd83000, 7, 8 00000006, 8dd82000, 8dd82000, 1, 8000000000000008 00000000, 8dd7e000, 8dd7e000, 4, 8 00000001, 8dd67000, 8dd67000, 17, 8 00000004, 8dd66000, 8dd66000, 1, 8 00000000, 8dd64000, 8dd64000, 2, 8 00000002, 8dd63000, 8dd63000, 1, 8 00000006, 8dd62000, 8dd62000, 1, 8000000000000008 00000002, 8dd61000, 8dd61000, 1, 8 00000001, 6e60c000, 6e60c000, 1f755, 8 00000002, 6e1f8000, 6e1f8000, 414, 8 00000001, 6dded000, 6dded000, 40b, 8 00000002, 6ddec000, 6ddec000, 1, 8 00000004, 6ddeb000, 6ddeb000, 1, 8 00000002, 6dde9000, 6dde9000, 2, 8 00000007, 2ffff000, 2ffff000, 3ddea, 8 00000002, 2e1f1000, 2e1f1000, 1e0e, 8 00000007, 17f0c000, 17f0c000, 162e5, 8 00000004, 17f00000, 17f00000, c, 8 00000002, 17d00000, 17d00000, 200, 8 00000007, 1240b000, 1240b000, 58f5, 8 00000002, 12000000, 12000000, 40b, 8 00000004, 10000000, 10000000, 2000, 8 The initial ramdisk is loaded at 2e1f1000. The problem occurs in drivers/of/fdt.c where some memory areas including the one containig the initial ramdisk are excluded. I have added some extra debug lines to early_init_dt_add_memory_arch(). [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.19.55-armmp (zfsdt@family) (gcc version 8.3.0 (Debian 8.3.0-6)) #8 SMP Sat Jun 29 17:04:52 CES9 [ 0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Wandboard i.MX6 Quad Board rev B1 [ 0.000000] OF: fdt: base 10000000 < phys_offset 68000000 [ 0.000000] OF: fdt: Ignoring memory range 0x10000000 - 0x68000000 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: EFI v2.80 by Das U-Boot [ 0.000000] efi: SMBIOS=0x8dd82000 [ 0.000000] OF: fdt: base 0000000010000000 + size 0000000002000000 < phys_offset 0000000068000000 [ 0.000000] OF: fdt: Ignoring memory block 0x10000000 - 0x12000000 [ 0.000000] OF: fdt: base 0000000012000000 + size 000000000040b000 < phys_offset 0000000068000000 [ 0.000000] OF: fdt: Ignoring memory block 0x12000000 - 0x1240b000 [ 0.000000] OF: fdt: base 000000001240b000 + size 00000000058f5000 < phys_offset 0000000068000000 [ 0.000000] OF: fdt: Ignoring memory block 0x1240b000 - 0x17d00000 [ 0.000000] OF: fdt: base 0000000017d00000 + size 0000000000200000 < phys_offset 0000000068000000 [ 0.000000] OF: fdt: Ignoring memory block 0x17d00000 - 0x17f00000 [ 0.000000] OF: fdt: phys_offset 0000000068000000 [ 0.000000] OF: fdt: base 0000000017f00000 + size 000000000000c000 < phys_offset 0000000068000000 [ 0.000000] OF: fdt: Ignoring memory block 0x17f00000 - 0x17f0c000 [ 0.000000] OF: fdt: phys_offset 0000000068000000 [ 0.000000] OF: fdt: base 0000000017f0c000 + size 00000000162e5000 < phys_offset 0000000068000000 [ 0.000000] OF: fdt: Ignoring memory block 0x17f0c000 - 0x2e1f1000 [ 0.000000] OF: fdt: phys_offset 0000000068000000 [ 0.000000] OF: fdt: base 000000002e1f1000 + size 0000000001e0e000 < phys_offset 0000000068000000 [ 0.000000] OF: fdt: Ignoring memory block 0x2e1f1000 - 0x2ffff000 [ 0.000000] INITRD: 0x2e1f1000+0x01e0e000 is not a memory region - disabling initrd [ 0.000000] cma: Reserved 16 MiB at 0x8e000000 [ 0.000000] Unable to handle kernel paging request at virtual address 6fd00000 [ 0.000000] pgd = (ptrval) [ 0.000000] [6fd00000] *pgd=00000000 [ 0.000000] Internal error: Oops: 5 [#1] SMP ARM [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.19.55-armmp #8 [ 0.000000] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 0.000000] PC is at fdt_check_header+0xc/0x80 [ 0.000000] LR is at __unflatten_device_tree+0x4c/0x274 [ 0.000000] pc : [<c0ae9d48>] lr : [<c09696dc>] psr: 200000d3 [ 0.000000] sp : c1201ec0 ip : c1201ed0 fp : c1201ecc [ 0.000000] r10: c1316340 r9 : 00000000 r8 : c135e308 [ 0.000000] r7 : 00000000 r6 : 6fd00000 r5 : c1074be8 r4 : c1074be8 [ 0.000000] r3 : c1074be8 r2 : c135e308 r1 : 00000000 r0 : 6fd00000 [ 0.000000] Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none [ 0.000000] Control: 10c5387d Table: 6820404a DAC: 00000051 [ 0.000000] Process swapper (pid: 0, stack limit = 0x(ptrval)) [ 0.000000] Stack: (0xc1201ec0 to 0xc1202000) [ 0.000000] 1ec0: c1201efc c1201ed0 c09696dc c0ae9d48 c1074be8 c1074be8 c1209900 8fffffff [ 0.000000] 1ee0: 8f980000 c1349880 e7fffc80 c1316340 c1201f1c c1201f00 c1076000 c096969c [ 0.000000] 1f00: 00000000 c1201f10 c0358230 c1083028 c1201fa4 c1201f20 c1004a38 c1075fc8 [ 0.000000] 1f20: ffffffff 10c5387d c03bcd50 c03bc83c c0d61908 c0d6349c c1205dcc c1201fbc [ 0.000000] 1f40: c0e340c8 fffff000 c1201fa4 c1201f58 c1022158 c0af8b54 c1205dcc c1205dcc [ 0.000000] 1f60: c1205dcc ffffffff c1201f94 c1201f78 c03bd0c8 00000000 c1201f9c 00000000 [ 0.000000] 1f80: c1205dcc c1205dcc ffffffff c1205dc0 412fc09a 10c5387d c1201ff4 c Best regards Heinrich

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[U-Boot] [PATCH v4 0/6] android: implement A/B boot process
by Igor Opaniuk 02 Jul '19

02 Jul '19

*** This patch series depends on [4], [5], [6] and should be applied after these paticular patches. This patch series adds support for Android A/B boot process [1]. Main steps of A/B boot process are: - A/B metadata integrity check - looking for the current slot (where the system should be booting from) - getting the name of the current boot partition (boot_a or boot_b) and loading the corresponding Android boot image - getting the name of the current system partition (system_a or system_b) and passing of its full name via kernel command line (like 'root=/dev/mmcblk1p11') - passing current slot via kernel command line (like 'androidboot.slot_suffix=_a') and via A/B metadata (e.g. via misc partition) - A/B metadata processing: setting the boot success flag for current slot, handling the retry counter, etc A/B metadata is organized according to Android reference [2] and stored on 'misc' partition. On the first A/B boot process, when 'misc' partition doesn't contain required data, default A/B metadata will be created and stored in 'misc' partition. In the end of the Android boot, 'update_verifier' and 'update_engine' services are processing the A/B metadata through the Boot Control HAL. To confirm the boot was successful using current slot, "boot success" flag must be set on Android side. To enable Android A/B support in U-Boot: 1. Set the following config options: CONFIG_ANDROID_AB=y CONFIG_CMD_AB_SELECT=y 2. Change the disk layout so that it has sloted boot partitions. E.g. instead of 'boot' and 'system' partitions there should be 'boot_a', 'boot_b', 'system_a' and 'system_b' partitions. To be able to actually test this patch series, the A/B features must be implemented and enabled in Android as well (see [1] for details). Documentation and corresponding test for A/B boot is present here. The last patch in this series integrates A/B boot support on AM57xx based boards (though it's not enabled by default). Future users of A/B boot feature can use it as a reference. This series is a part of previous submission [3] by Alex Deymo. It contains only A/B feature that was stripped out from there with some modifications for using with "bootm" command preferred in upstream. Changes in v4: * Removed android_bl_msg.h and re-used the one, which was introduced by Eugeniu Rosca in [4] and [5]. * Initially we had intention to use "bcb" command and scripting for providing proper boot sequence logic (slot selection, decrementing the counter for each slot), but found out that it's better to keep using a dedicated command ab_select to avoid huge amount of scripting in the headers in includes/config for each platform. * Removed ANDROID_ prefix in multiple macros. * Addressed comments from Simon Changes in v3: * Minor fixes in the ab metadata handling (added additional sanity checks). * As Ruslan Trofymenko left Linaro and won't address comments anymore, continue (added my S-b tag) upstreaming patches on my own. Changes in v2: * 'android_ab_select' command is renamed to 'ab_select' command and moved to separate 'Android support commands' menu * For am57xx boards slotted sections (e.g. system_a and system_b) are added to the default sections if CONFIG_CMD_AB_SELECT flag is defined * Returned function error codes are clarified (errno using) * Some types constants and files are renamed * Assertion condition is clarified in test case * 'debug' calls are changed to 'log_debug' * The Guide is clarified by the results of changes [1] https://source.android.com/devices/tech/ota/ab/ab_implement [2] bootable/recovery/bootloader_message/include/bootloader_message/bootloader_message.h [3] https://lists.denx.de/pipermail/u-boot/2017-April/285841.html [4] https://patchwork.ozlabs.org/patch/1080394/ [5] https://patchwork.ozlabs.org/patch/1104243/ [6] https://patchwork.ozlabs.org/patch/1116012/ Ruslan Trofymenko (6): disk: part: Extend API to get partition info common: Implement A/B metadata cmd: Add 'ab_select' command test/py: Add base test case for A/B updates doc: android: Add simple guide for A/B updates env: am57xx: Implement A/B boot process cmd/Kconfig | 15 ++ cmd/Makefile | 1 + cmd/ab_select.c | 52 ++++++ common/Kconfig | 10 ++ common/Makefile | 1 + common/android_ab.c | 298 ++++++++++++++++++++++++++++++++++ configs/sandbox_defconfig | 2 + disk/part.c | 68 ++++++++ doc/README.android-ab | 67 ++++++++ include/android_ab.h | 34 ++++ include/environment/ti/boot.h | 58 ++++++- include/part.h | 21 +++ test/py/tests/test_ab.py | 74 +++++++++ 13 files changed, 695 insertions(+), 6 deletions(-) create mode 100644 cmd/ab_select.c create mode 100644 common/android_ab.c create mode 100644 doc/README.android-ab create mode 100644 include/android_ab.h create mode 100644 test/py/tests/test_ab.py -- 2.17.1

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