July 2019 - U-Boot

[U-Boot] [PATCH v7 3/9] x86: Add a common HOB library
by Park, Aiden 02 Aug '19

02 Aug '19

FSP(CONFIG_HAVE_FSP) and Slim Bootloader(CONFIG_SYS_SLIMBOOTLOADER) consume HOB(CONFIG_USE_HOB) data from the each HOB list pointer. Add a common HOB library in lib/hob.c and include/asm/hob.h. Signed-off-by: Aiden Park <aiden.park(a)intel.com> --- Changes in v7: * Split HOB library into EFI_GUID pre-work and making a common library Changes in v6: * Use CONFIG_USE_HOB * Change struct efi_guid to efi_guid_t * Use EFI_GUID to define GUIDs Changes in v3: * Create a common HOB libary from fsp_hob and fsp_support arch/x86/include/asm/fsp/fsp_hob.h | 184 +------------------- arch/x86/include/asm/fsp/fsp_support.h | 37 +--- arch/x86/include/asm/hob.h | 229 +++++++++++++++++++++++++ arch/x86/lib/Makefile | 1 + arch/x86/lib/fsp/fsp_support.c | 57 +----- arch/x86/lib/hob.c | 84 +++++++++ cmd/x86/Makefile | 1 + cmd/x86/fsp.c | 65 +------ cmd/x86/hob.c | 78 +++++++++ 9 files changed, 399 insertions(+), 337 deletions(-) create mode 100644 arch/x86/include/asm/hob.h create mode 100644 arch/x86/lib/hob.c create mode 100644 cmd/x86/hob.c diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h index 843d7b513b..3bb79c4b67 100644 --- a/arch/x86/include/asm/fsp/fsp_hob.h +++ b/arch/x86/include/asm/fsp/fsp_hob.h @@ -7,125 +7,7 @@ #ifndef __FSP_HOB_H__ #define __FSP_HOB_H__ -#include <efi.h> -#include <efi_loader.h> - -/* Type of HOB Header */ -#define HOB_TYPE_MEM_ALLOC 0x0002 -#define HOB_TYPE_RES_DESC 0x0003 -#define HOB_TYPE_GUID_EXT 0x0004 -#define HOB_TYPE_UNUSED 0xFFFE -#define HOB_TYPE_EOH 0xFFFF - -/* - * Describes the format and size of the data inside the HOB. - * All HOBs must contain this generic HOB header. - */ -struct hob_header { - u16 type; /* HOB type */ - u16 len; /* HOB length */ - u32 reserved; /* always zero */ -}; - -/* - * Describes all memory ranges used during the HOB producer phase that - * exist outside the HOB list. This HOB type describes how memory is used, - * not the physical attributes of memory. - */ -struct hob_mem_alloc { - struct hob_header hdr; - /* - * A GUID that defines the memory allocation region's type and purpose, - * as well as other fields within the memory allocation HOB. This GUID - * is used to define the additional data within the HOB that may be - * present for the memory allocation HOB. Type efi_guid is defined in - * InstallProtocolInterface() in the UEFI 2.0 specification. - */ - efi_guid_t name; - /* - * The base address of memory allocated by this HOB. - * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0 - * specification. - */ - phys_addr_t mem_base; - /* The length in bytes of memory allocated by this HOB */ - phys_size_t mem_len; - /* - * Defines the type of memory allocated by this HOB. - * The memory type definition follows the EFI_MEMORY_TYPE definition. - * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0 - * specification. - */ - enum efi_mem_type mem_type; - /* padding */ - u8 reserved[4]; -}; - -/* Value of ResourceType in HOB_RES_DESC */ -#define RES_SYS_MEM 0x00000000 -#define RES_MMAP_IO 0x00000001 -#define RES_IO 0x00000002 -#define RES_FW_DEVICE 0x00000003 -#define RES_MMAP_IO_PORT 0x00000004 -#define RES_MEM_RESERVED 0x00000005 -#define RES_IO_RESERVED 0x00000006 -#define RES_MAX_MEM_TYPE 0x00000007 - -/* - * These types can be ORed together as needed. - * - * The first three enumerations describe settings - * The rest of the settings describe capabilities - */ -#define RES_ATTR_PRESENT 0x00000001 -#define RES_ATTR_INITIALIZED 0x00000002 -#define RES_ATTR_TESTED 0x00000004 -#define RES_ATTR_SINGLE_BIT_ECC 0x00000008 -#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010 -#define RES_ATTR_ECC_RESERVED_1 0x00000020 -#define RES_ATTR_ECC_RESERVED_2 0x00000040 -#define RES_ATTR_READ_PROTECTED 0x00000080 -#define RES_ATTR_WRITE_PROTECTED 0x00000100 -#define RES_ATTR_EXECUTION_PROTECTED 0x00000200 -#define RES_ATTR_UNCACHEABLE 0x00000400 -#define RES_ATTR_WRITE_COMBINEABLE 0x00000800 -#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000 -#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000 -#define RES_ATTR_16_BIT_IO 0x00004000 -#define RES_ATTR_32_BIT_IO 0x00008000 -#define RES_ATTR_64_BIT_IO 0x00010000 -#define RES_ATTR_UNCACHED_EXPORTED 0x00020000 - -/* - * Describes the resource properties of all fixed, nonrelocatable resource - * ranges found on the processor host bus during the HOB producer phase. - */ -struct hob_res_desc { - struct hob_header hdr; - /* - * A GUID representing the owner of the resource. This GUID is - * used by HOB consumer phase components to correlate device - * ownership of a resource. - */ - efi_guid_t owner; - u32 type; - u32 attr; - /* The physical start address of the resource region */ - phys_addr_t phys_start; - /* The number of bytes of the resource region */ - phys_size_t len; -}; - -/* - * Allows writers of executable content in the HOB producer phase to - * maintain and manage HOBs with specific GUID. - */ -struct hob_guid { - struct hob_header hdr; - /* A GUID that defines the contents of this HOB */ - efi_guid_t name; - /* GUID specific data goes here */ -}; +#include <asm/hob.h> enum pixel_format { pixel_rgbx_8bpc, /* RGB 8 bit per color */ @@ -147,70 +29,6 @@ struct __packed hob_graphics_info { u32 pixels_per_scanline; }; -/** - * get_next_hob() - return a pointer to the next HOB in the HOB list - * - * This macro returns a pointer to HOB that follows the HOB specified by hob - * in the HOB List. - * - * @hdr: A pointer to a HOB. - * - * @return: A pointer to the next HOB in the HOB list. - */ -static inline const struct hob_header *get_next_hob(const struct hob_header *hdr) -{ - return (const struct hob_header *)((uintptr_t)hdr + hdr->len); -} - -/** - * end_of_hob() - determine if a HOB is the last HOB in the HOB list - * - * This macro determine if the HOB specified by hob is the last HOB in the - * HOB list. If hob is last HOB in the HOB list, then true is returned. - * Otherwise, false is returned. - * - * @hdr: A pointer to a HOB. - * - * @retval true: The HOB specified by hdr is the last HOB in the HOB list. - * @retval false: The HOB specified by hdr is not the last HOB in the HOB list. - */ -static inline bool end_of_hob(const struct hob_header *hdr) -{ - return hdr->type == HOB_TYPE_EOH; -} - -/** - * get_guid_hob_data() - return a pointer to data buffer from a HOB of - * type HOB_TYPE_GUID_EXT - * - * This macro returns a pointer to the data buffer in a HOB specified by hob. - * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. - * - * @hdr: A pointer to a HOB. - * - * @return: A pointer to the data buffer in a HOB. - */ -static inline void *get_guid_hob_data(const struct hob_header *hdr) -{ - return (void *)((uintptr_t)hdr + sizeof(struct hob_guid)); -} - -/** - * get_guid_hob_data_size() - return the size of the data buffer from a HOB - * of type HOB_TYPE_GUID_EXT - * - * This macro returns the size, in bytes, of the data buffer in a HOB - * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. - * - * @hdr: A pointer to a HOB. - * - * @return: The size of the data buffer. - */ -static inline u16 get_guid_hob_data_size(const struct hob_header *hdr) -{ - return hdr->len - sizeof(struct hob_guid); -} - /* FSP specific GUID HOB definitions */ #define FSP_GUID_DATA1 0x912740be #define FSP_GUID_DATA2 0x2284 diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 0cca948184..7b92392a27 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -8,10 +8,10 @@ #define __FSP_SUPPORT_H__ #include "fsp_types.h" +#include "fsp_hob.h" #include "fsp_fv.h" #include "fsp_ffs.h" #include "fsp_api.h" -#include "fsp_hob.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" #include "fsp_azalia.h" @@ -131,41 +131,6 @@ u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); */ u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); -/** - * Returns the next instance of a HOB type from the starting HOB. - * - * @type: HOB type to search - * @hob_list: A pointer to the HOB list - * - * @retval: A HOB object with matching type; Otherwise NULL. - */ -const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list); - -/** - * Returns the next instance of the matched GUID HOB from the starting HOB. - * - * @guid: GUID to search - * @hob_list: A pointer to the HOB list - * - * @retval: A HOB object with matching GUID; Otherwise NULL. - */ -const struct hob_header *fsp_get_next_guid_hob(const efi_guid_t *guid, - const void *hob_list); - -/** - * This function retrieves a GUID HOB data buffer and size. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the GUID HOB data buffer length. - * If the GUID HOB is located, the length will be updated. - * @guid A pointer to HOB GUID. - * - * @retval NULL: Failed to find the GUID HOB. - * @retval others: GUID HOB data buffer pointer. - */ -void *fsp_get_guid_hob_data(const void *hob_list, u32 *len, - const efi_guid_t *guid); - /** * This function retrieves FSP Non-volatile Storage HOB buffer and size. * diff --git a/arch/x86/include/asm/hob.h b/arch/x86/include/asm/hob.h new file mode 100644 index 0000000000..26a2b81e08 --- /dev/null +++ b/arch/x86/include/asm/hob.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + */ + +#ifndef __HOB_H__ +#define __HOB_H__ + +#include <efi.h> +#include <efi_loader.h> + +/* Type of HOB Header */ +#define HOB_TYPE_MEM_ALLOC 0x0002 +#define HOB_TYPE_RES_DESC 0x0003 +#define HOB_TYPE_GUID_EXT 0x0004 +#define HOB_TYPE_UNUSED 0xFFFE +#define HOB_TYPE_EOH 0xFFFF + +/* Value of ResourceType in HOB_RES_DESC */ +#define RES_SYS_MEM 0x00000000 +#define RES_MMAP_IO 0x00000001 +#define RES_IO 0x00000002 +#define RES_FW_DEVICE 0x00000003 +#define RES_MMAP_IO_PORT 0x00000004 +#define RES_MEM_RESERVED 0x00000005 +#define RES_IO_RESERVED 0x00000006 +#define RES_MAX_MEM_TYPE 0x00000007 + +/* + * These types can be ORed together as needed. + * + * The first three enumerations describe settings + * The rest of the settings describe capabilities + */ +#define RES_ATTR_PRESENT 0x00000001 +#define RES_ATTR_INITIALIZED 0x00000002 +#define RES_ATTR_TESTED 0x00000004 +#define RES_ATTR_SINGLE_BIT_ECC 0x00000008 +#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010 +#define RES_ATTR_ECC_RESERVED_1 0x00000020 +#define RES_ATTR_ECC_RESERVED_2 0x00000040 +#define RES_ATTR_READ_PROTECTED 0x00000080 +#define RES_ATTR_WRITE_PROTECTED 0x00000100 +#define RES_ATTR_EXECUTION_PROTECTED 0x00000200 +#define RES_ATTR_UNCACHEABLE 0x00000400 +#define RES_ATTR_WRITE_COMBINEABLE 0x00000800 +#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000 +#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000 +#define RES_ATTR_16_BIT_IO 0x00004000 +#define RES_ATTR_32_BIT_IO 0x00008000 +#define RES_ATTR_64_BIT_IO 0x00010000 +#define RES_ATTR_UNCACHED_EXPORTED 0x00020000 + +/* + * Describes the format and size of the data inside the HOB. + * All HOBs must contain this generic HOB header. + */ +struct hob_header { + u16 type; /* HOB type */ + u16 len; /* HOB length */ + u32 reserved; /* always zero */ +}; + +/* + * Describes all memory ranges used during the HOB producer phase that + * exist outside the HOB list. This HOB type describes how memory is used, + * not the physical attributes of memory. + */ +struct hob_mem_alloc { + struct hob_header hdr; + /* + * A GUID that defines the memory allocation region's type and purpose, + * as well as other fields within the memory allocation HOB. This GUID + * is used to define the additional data within the HOB that may be + * present for the memory allocation HOB. Type efi_guid_t is defined in + * InstallProtocolInterface() in the UEFI 2.0 specification. + */ + efi_guid_t name; + /* + * The base address of memory allocated by this HOB. + * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0 + * specification. + */ + phys_addr_t mem_base; + /* The length in bytes of memory allocated by this HOB */ + phys_size_t mem_len; + /* + * Defines the type of memory allocated by this HOB. + * The memory type definition follows the EFI_MEMORY_TYPE definition. + * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0 + * specification. + */ + enum efi_mem_type mem_type; + /* padding */ + u8 reserved[4]; +}; + +/* + * Describes the resource properties of all fixed, nonrelocatable resource + * ranges found on the processor host bus during the HOB producer phase. + */ +struct hob_res_desc { + struct hob_header hdr; + /* + * A GUID representing the owner of the resource. This GUID is + * used by HOB consumer phase components to correlate device + * ownership of a resource. + */ + efi_guid_t owner; + u32 type; + u32 attr; + /* The physical start address of the resource region */ + phys_addr_t phys_start; + /* The number of bytes of the resource region */ + phys_size_t len; +}; + +/* + * Allows writers of executable content in the HOB producer phase to + * maintain and manage HOBs with specific GUID. + */ +struct hob_guid { + struct hob_header hdr; + /* A GUID that defines the contents of this HOB */ + efi_guid_t name; + /* GUID specific data goes here */ +}; + +/** + * get_next_hob() - return a pointer to the next HOB in the HOB list + * + * This macro returns a pointer to HOB that follows the HOB specified by hob + * in the HOB List. + * + * @hdr: A pointer to a HOB. + * + * @return: A pointer to the next HOB in the HOB list. + */ +static inline const struct hob_header *get_next_hob(const struct hob_header *hdr) +{ + return (const struct hob_header *)((uintptr_t)hdr + hdr->len); +} + +/** + * end_of_hob() - determine if a HOB is the last HOB in the HOB list + * + * This macro determine if the HOB specified by hob is the last HOB in the + * HOB list. If hob is last HOB in the HOB list, then true is returned. + * Otherwise, false is returned. + * + * @hdr: A pointer to a HOB. + * + * @retval true: The HOB specified by hdr is the last HOB in the HOB list. + * @retval false: The HOB specified by hdr is not the last HOB in the HOB list. + */ +static inline bool end_of_hob(const struct hob_header *hdr) +{ + return hdr->type == HOB_TYPE_EOH; +} + +/** + * get_guid_hob_data() - return a pointer to data buffer from a HOB of + * type HOB_TYPE_GUID_EXT + * + * This macro returns a pointer to the data buffer in a HOB specified by hob. + * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. + * + * @hdr: A pointer to a HOB. + * + * @return: A pointer to the data buffer in a HOB. + */ +static inline void *get_guid_hob_data(const struct hob_header *hdr) +{ + return (void *)((uintptr_t)hdr + sizeof(struct hob_guid)); +} + +/** + * get_guid_hob_data_size() - return the size of the data buffer from a HOB + * of type HOB_TYPE_GUID_EXT + * + * This macro returns the size, in bytes, of the data buffer in a HOB + * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT. + * + * @hdr: A pointer to a HOB. + * + * @return: The size of the data buffer. + */ +static inline u16 get_guid_hob_data_size(const struct hob_header *hdr) +{ + return hdr->len - sizeof(struct hob_guid); +} + +/** + * Returns the next instance of a HOB type from the starting HOB. + * + * @type: HOB type to search + * @hob_list: A pointer to the HOB list + * + * @retval: A HOB object with matching type; Otherwise NULL. + */ +const struct hob_header *hob_get_next_hob(uint type, const void *hob_list); + +/** + * Returns the next instance of the matched GUID HOB from the starting HOB. + * + * @guid: GUID to search + * @hob_list: A pointer to the HOB list + * + * @retval: A HOB object with matching GUID; Otherwise NULL. + */ +const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid, + const void *hob_list); + +/** + * This function retrieves a GUID HOB data buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the GUID HOB data buffer length. + * If the GUID HOB is located, the length will be updated. + * @guid A pointer to HOB GUID. + * + * @retval NULL: Failed to find the GUID HOB. + * @retval others: GUID HOB data buffer pointer. + */ +void *hob_get_guid_hob_data(const void *hob_list, u32 *len, + const efi_guid_t *guid); + +#endif /* __HOB_H__ */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 436252dd83..906be5eab9 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -42,6 +42,7 @@ obj-y += tables.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_ZBOOT) += zimage.o endif +obj-$(CONFIG_USE_HOB) += hob.o obj-$(CONFIG_HAVE_FSP) += fsp/ ifdef CONFIG_SPL_BUILD diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 0d1bb35186..0eaa9b232b 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -344,74 +344,23 @@ u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len) return base; } -const struct hob_header *fsp_get_next_hob(uint type, const void *hob_list) -{ - const struct hob_header *hdr; - - hdr = hob_list; - - /* Parse the HOB list until end of list or matching type is found */ - while (!end_of_hob(hdr)) { - if (hdr->type == type) - return hdr; - - hdr = get_next_hob(hdr); - } - - return NULL; -} - -const struct hob_header *fsp_get_next_guid_hob(const efi_guid_t *guid, - const void *hob_list) -{ - const struct hob_header *hdr; - struct hob_guid *guid_hob; - - hdr = hob_list; - while ((hdr = fsp_get_next_hob(HOB_TYPE_GUID_EXT, - hdr)) != NULL) { - guid_hob = (struct hob_guid *)hdr; - if (!guidcmp(guid, &(guid_hob->name))) - break; - hdr = get_next_hob(hdr); - } - - return hdr; -} - -void *fsp_get_guid_hob_data(const void *hob_list, u32 *len, - const efi_guid_t *guid) -{ - const struct hob_header *guid_hob; - - guid_hob = fsp_get_next_guid_hob(guid, hob_list); - if (guid_hob == NULL) { - return NULL; - } else { - if (len) - *len = get_guid_hob_data_size(guid_hob); - - return get_guid_hob_data(guid_hob); - } -} - void *fsp_get_nvs_data(const void *hob_list, u32 *len) { const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - return fsp_get_guid_hob_data(hob_list, len, &guid); + return hob_get_guid_hob_data(hob_list, len, &guid); } void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) { const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; - return fsp_get_guid_hob_data(hob_list, len, &guid); + return hob_get_guid_hob_data(hob_list, len, &guid); } void *fsp_get_graphics_info(const void *hob_list, u32 *len) { const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID; - return fsp_get_guid_hob_data(hob_list, len, &guid); + return hob_get_guid_hob_data(hob_list, len, &guid); } diff --git a/arch/x86/lib/hob.c b/arch/x86/lib/hob.c new file mode 100644 index 0000000000..dcee29b04c --- /dev/null +++ b/arch/x86/lib/hob.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: Intel +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + */ + +#include <common.h> +#include <asm/hob.h> + +/** + * Returns the next instance of a HOB type from the starting HOB. + * + * @type: HOB type to search + * @hob_list: A pointer to the HOB list + * + * @retval: A HOB object with matching type; Otherwise NULL. + */ +const struct hob_header *hob_get_next_hob(uint type, const void *hob_list) +{ + const struct hob_header *hdr; + + hdr = hob_list; + + /* Parse the HOB list until end of list or matching type is found */ + while (!end_of_hob(hdr)) { + if (hdr->type == type) + return hdr; + + hdr = get_next_hob(hdr); + } + + return NULL; +} + +/** + * Returns the next instance of the matched GUID HOB from the starting HOB. + * + * @guid: GUID to search + * @hob_list: A pointer to the HOB list + * + * @retval: A HOB object with matching GUID; Otherwise NULL. + */ +const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid, + const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_guid *guid_hob; + + hdr = hob_list; + while ((hdr = hob_get_next_hob(HOB_TYPE_GUID_EXT, hdr))) { + guid_hob = (struct hob_guid *)hdr; + if (!guidcmp(guid, &guid_hob->name)) + break; + hdr = get_next_hob(hdr); + } + + return hdr; +} + +/** + * This function retrieves a GUID HOB data buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the GUID HOB data buffer length. + * If the GUID HOB is located, the length will be updated. + * @guid A pointer to HOB GUID. + * + * @retval NULL: Failed to find the GUID HOB. + * @retval others: GUID HOB data buffer pointer. + */ +void *hob_get_guid_hob_data(const void *hob_list, u32 *len, + const efi_guid_t *guid) +{ + const struct hob_header *guid_hob; + + guid_hob = hob_get_next_guid_hob(guid, hob_list); + if (!guid_hob) + return NULL; + + if (len) + *len = get_guid_hob_data_size(guid_hob); + + return get_guid_hob_data(guid_hob); +} diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile index 707161440d..144b1cf5ab 100644 --- a/cmd/x86/Makefile +++ b/cmd/x86/Makefile @@ -2,4 +2,5 @@ obj-y += mtrr.o obj-$(CONFIG_CMD_EXCEPTION) += exception.o +obj-$(CONFIG_USE_HOB) += hob.o obj-$(CONFIG_HAVE_FSP) += fsp.o diff --git a/cmd/x86/fsp.c b/cmd/x86/fsp.c index 1b4c0207ce..efa183854b 100644 --- a/cmd/x86/fsp.c +++ b/cmd/x86/fsp.c @@ -9,21 +9,6 @@ DECLARE_GLOBAL_DATA_PTR; -static char *hob_type[] = { - "reserved", - "Hand-off", - "Mem Alloc", - "Res Desc", - "GUID Ext", - "FV", - "CPU", - "Mem Pool", - "reserved", - "FV2", - "Load PEIM", - "Capsule", -}; - static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct fsp_header *hdr = find_fsp_header(); @@ -72,55 +57,8 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - const struct hob_header *hdr; - uint type; - char *desc; - int i = 0; - char uuid[UUID_STR_LEN + 1]; - - hdr = gd->arch.hob_list; - - printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr); - - printf("# | Address | Type | Len | "); - printf("%42s\n", "GUID"); - printf("---|----------|-----------|------|-"); - printf("------------------------------------------\n"); - while (!end_of_hob(hdr)) { - printf("%02x | %08x | ", i, (unsigned int)hdr); - type = hdr->type; - if (type == HOB_TYPE_UNUSED) - desc = "*Unused*"; - else if (type == HOB_TYPE_EOH) - desc = "*EOH*"; - else if (type >= 0 && type <= ARRAY_SIZE(hob_type)) - desc = hob_type[type]; - else - desc = "*Invalid*"; - printf("%-9s | %04x | ", desc, hdr->len); - - if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || - type == HOB_TYPE_GUID_EXT) { - efi_guid_t *guid = (efi_guid_t *)(hdr + 1); - - uuid_bin_to_str(guid->b, uuid, UUID_STR_FORMAT_GUID); - printf("%s", uuid); - } else { - printf("%42s", "Not Available"); - } - printf("\n"); - hdr = get_next_hob(hdr); - i++; - } - - return 0; -} - static cmd_tbl_t fsp_commands[] = { U_BOOT_CMD_MKENT(hdr, 0, 1, do_hdr, "", ""), - U_BOOT_CMD_MKENT(hob, 0, 1, do_hob, "", ""), }; static int do_fsp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -144,6 +82,5 @@ static int do_fsp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( fsp, 2, 1, do_fsp, "Show Intel Firmware Support Package (FSP) related information", - "hdr - Print FSP header information\n" - "fsp hob - Print FSP Hand-Off Block (HOB) information" + "hdr - Print FSP header information" ); diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c new file mode 100644 index 0000000000..5bc6deb8bd --- /dev/null +++ b/cmd/x86/hob.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014-2015, Bin Meng <bmeng.cn(a)gmail.com> + */ + +#include <common.h> +#include <command.h> +#include <efi.h> +#include <asm/hob.h> + +DECLARE_GLOBAL_DATA_PTR; + +static char *hob_type[] = { + "reserved", + "Hand-off", + "Mem Alloc", + "Res Desc", + "GUID Ext", + "FV", + "CPU", + "Mem Pool", + "reserved", + "FV2", + "Load PEIM", + "Capsule", +}; + +static int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const struct hob_header *hdr; + uint type; + char *desc; + int i = 0; + efi_guid_t *guid; + char uuid[UUID_STR_LEN + 1]; + + hdr = gd->arch.hob_list; + + printf("HOB list address: 0x%08x\n\n", (unsigned int)hdr); + + printf("# | Address | Type | Len | "); + printf("%36s\n", "GUID"); + printf("---|----------|-----------|------|-"); + printf("------------------------------------\n"); + while (!end_of_hob(hdr)) { + printf("%02x | %08x | ", i, (unsigned int)hdr); + type = hdr->type; + if (type == HOB_TYPE_UNUSED) + desc = "*Unused*"; + else if (type == HOB_TYPE_EOH) + desc = "*EOH*"; + else if (type >= 0 && type <= ARRAY_SIZE(hob_type)) + desc = hob_type[type]; + else + desc = "*Invalid*"; + printf("%-9s | %04x | ", desc, hdr->len); + + if (type == HOB_TYPE_MEM_ALLOC || type == HOB_TYPE_RES_DESC || + type == HOB_TYPE_GUID_EXT) { + guid = (efi_guid_t *)(hdr + 1); + uuid_bin_to_str(guid->b, uuid, UUID_STR_FORMAT_GUID); + printf("%s", uuid); + } else { + printf("%36s", "Not Available"); + } + printf("\n"); + hdr = get_next_hob(hdr); + i++; + } + + return 0; +} + +U_BOOT_CMD( + hob, 1, 1, do_hob, + "Print Hand-Off Block (HOB) information", + "" +); -- 2.20.1

3 4

[U-Boot] [PATCH v7 0/9] x86: Add basic Slim Bootloader payload support
by Park, Aiden 02 Aug '19

02 Aug '19

This patch is to enable U-Boot as a payload which runs on top of Slim Bootloader(https://github.com/slimbootloader/slimbootloader) boot firmware for x86 platforms. The Slim Bootloader is designed with multi-stage architecture for the execution from reset vector to OS hand-off, and supports QEMU, Apollolake, Whiskeylake and Coffeelake platforms consuming Intel FSP(https://github.com/IntelFsp/FSP) for silicon initialization including CAR and memory initialization. As multi-stage architecture, the Slim Bootloader adopts payload concept which is responsible for OS load from media devices and boot OS and it supports 32-bit PE32, EFI FV, ELF and RAW format payloads. The Slim Bootloader generate HOB(Hand Off Block) list pointer, which has debug serial port info, memory map info, performance data info and etc., and passes it to a payload. U-Boot configures serial port, dram, pci, tsc and others with the information from the HOB. The compiled U-Boot supports USB, SATA and SD/MMC boot which have been verified on QEMU and other supported platforms. Changes in v7: * Split HOB library into EFI_GUID pre-work and making a common library * Use for_each macro for memory entry search Changes in v6: * Add CONFIG_USE_HOB * Move USB_STORAGE and USB_KEYBOARD from CPU Kconfig to board Kconfig * Remove RTL8169 until required * Use EFI_GUID and efi_guid_t instead of struct efi_guid * Use less generic struct name in Slim Bootloader specific files * Convert README to reST doc/board/intel/slimbootloader.rst Changes in v5: * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig Changes in v4: * Use arch/x86/cpu/start.S with CONFIG_SYS_SLIMBOOTLOADER condition * Update U-boot or u-boot to U-Boot in commit message * Add static keyword in static function Changes in v3: * Add a brief description about Slim Bootloader in 1st patch * Add a common HOB library to be used by both FSP and Slim Bootloader * Move board/slimbootloader/slimbootloader to board/intel/slimbootloader * Add more description board/intel/slimbootloader/README * Fix comments from the code review Changes in v2: * Split a single patch to 8 patches * Add more comment for each structure and functions Aiden Park (9): x86: Add new slimbootloader CPU type x86: lib: fsp: Use EFI_GUID and efi_guid_t x86: Add a common HOB library x86: slimbootloader: Add memory configuration x86: slimbootloader: Add serial driver x86: slimbootloader: Set TSC information for tsc_timer x86: slimbootloader: Add a slimbootloader device tree board: intel: Add new slimbootloader board x86: Skip setting up MTRRs in slimbootloader arch/x86/Kconfig | 9 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/slimbootloader/Kconfig | 19 ++ arch/x86/cpu/slimbootloader/Makefile | 5 + arch/x86/cpu/slimbootloader/car.S | 14 + arch/x86/cpu/slimbootloader/sdram.c | 149 +++++++++++ arch/x86/cpu/slimbootloader/serial.c | 67 +++++ arch/x86/cpu/slimbootloader/slimbootloader.c | 58 ++++ arch/x86/cpu/start.S | 6 +- arch/x86/dts/Makefile | 1 + arch/x86/dts/slimbootloader.dts | 27 ++ .../asm/arch-slimbootloader/slimbootloader.h | 115 ++++++++ arch/x86/include/asm/fsp/fsp_ffs.h | 4 +- arch/x86/include/asm/fsp/fsp_fv.h | 4 +- arch/x86/include/asm/fsp/fsp_hob.h | 252 +++--------------- arch/x86/include/asm/fsp/fsp_support.h | 39 +-- arch/x86/include/asm/fsp/fsp_types.h | 8 - arch/x86/include/asm/global_data.h | 2 +- arch/x86/include/asm/hob.h | 229 ++++++++++++++++ arch/x86/lib/Makefile | 1 + arch/x86/lib/asm-offsets.c | 2 +- arch/x86/lib/fsp/fsp_support.c | 123 ++------- arch/x86/lib/hob.c | 84 ++++++ arch/x86/lib/init_helpers.c | 3 +- board/intel/Kconfig | 14 + board/intel/slimbootloader/Kconfig | 28 ++ board/intel/slimbootloader/Makefile | 5 + board/intel/slimbootloader/slimbootloader.c | 21 ++ board/intel/slimbootloader/start.S | 9 + cmd/x86/Makefile | 1 + cmd/x86/fsp.c | 67 +---- cmd/x86/hob.c | 78 ++++++ configs/slimbootloader_defconfig | 22 ++ doc/board/intel/index.rst | 1 + doc/board/intel/slimbootloader.rst | 174 ++++++++++++ include/configs/slimbootloader.h | 62 +++++ 36 files changed, 1273 insertions(+), 431 deletions(-) create mode 100644 arch/x86/cpu/slimbootloader/Kconfig create mode 100644 arch/x86/cpu/slimbootloader/Makefile create mode 100644 arch/x86/cpu/slimbootloader/car.S create mode 100644 arch/x86/cpu/slimbootloader/sdram.c create mode 100644 arch/x86/cpu/slimbootloader/serial.c create mode 100644 arch/x86/cpu/slimbootloader/slimbootloader.c create mode 100644 arch/x86/dts/slimbootloader.dts create mode 100644 arch/x86/include/asm/arch-slimbootloader/slimbootloader.h create mode 100644 arch/x86/include/asm/hob.h create mode 100644 arch/x86/lib/hob.c create mode 100644 board/intel/slimbootloader/Kconfig create mode 100644 board/intel/slimbootloader/Makefile create mode 100644 board/intel/slimbootloader/slimbootloader.c create mode 100644 board/intel/slimbootloader/start.S create mode 100644 cmd/x86/hob.c create mode 100644 configs/slimbootloader_defconfig create mode 100644 doc/board/intel/slimbootloader.rst create mode 100644 include/configs/slimbootloader.h -- 2.20.1

3 3

[U-Boot] [PATCH v7 8/9] board: intel: Add new slimbootloader board
by Park, Aiden 02 Aug '19

02 Aug '19

Add slimbootloader board to run U-boot as a Slim Bootloader payload - Add new board/intel/slimbootloader directory with minimum codes - Add slimbootloader configuration files - Add doc/board/intel/slimbootloader.rst Signed-off-by: Aiden Park <aiden.park(a)intel.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko(a)gmail.com> --- Changes in v7: * Adding slimbootloader.rst in index.rst Changes in v6: * Select CONFIG_SYS_SLIMBOOTLOADER in board Kconfig * Move USB_STORAGE and USB_KEYBOARD to board Kconfig * Convert README to reST doc/board/intel/slimbootloader.rst Changes in v5: * Remove X86_LOAD_FROM_32_BIT from slimbootloader_defconfig Changes in v3: * Remove VENDOR_SLIMBOOTLOADER * Use VENDOR_INTEL * Move slimbootloader under board/intel/ * Enable generic CONFIGs in slimbootloader_defconfig * Add more description in board/intel/slimbootloader/README board/intel/Kconfig | 14 ++ board/intel/slimbootloader/Kconfig | 28 ++++ board/intel/slimbootloader/Makefile | 5 + board/intel/slimbootloader/slimbootloader.c | 21 +++ board/intel/slimbootloader/start.S | 9 + configs/slimbootloader_defconfig | 22 +++ doc/board/intel/index.rst | 1 + doc/board/intel/slimbootloader.rst | 174 ++++++++++++++++++++ include/configs/slimbootloader.h | 62 +++++++ 9 files changed, 336 insertions(+) create mode 100644 board/intel/slimbootloader/Kconfig create mode 100644 board/intel/slimbootloader/Makefile create mode 100644 board/intel/slimbootloader/slimbootloader.c create mode 100644 board/intel/slimbootloader/start.S create mode 100644 configs/slimbootloader_defconfig create mode 100644 doc/board/intel/slimbootloader.rst create mode 100644 include/configs/slimbootloader.h diff --git a/board/intel/Kconfig b/board/intel/Kconfig index 5131836cb0..10859b5f08 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -73,6 +73,19 @@ config TARGET_MINNOWMAX Note that PCIE_ECAM_BASE is set up by the FSP so the value used by U-Boot matches that value. +config TARGET_SLIMBOOTLOADER + bool "slimbootloader" + help + This target is used for running U-Boot on top of Slim Bootloader + boot firmware as a payload. Slim Bootloader does memory initialization + and silicon initialization, and it passes necessary information in + HOB(Hand Off Block) to a payload. The payload consumes HOB data + which is generated by Slim Bootloader for its driver initialization. + Slim Bootloader consumes FSP and its HOB, but FSP HOB is cleared + Before launching a payload. Instead, Slim Bootloader generates its + HOB data such as memory info, serial port info and so on. + Refer to doc/board/intel/slimbootloader.rst for the details. + endchoice source "board/intel/bayleybay/Kconfig" @@ -82,5 +95,6 @@ source "board/intel/crownbay/Kconfig" source "board/intel/edison/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig" +source "board/intel/slimbootloader/Kconfig" endif diff --git a/board/intel/slimbootloader/Kconfig b/board/intel/slimbootloader/Kconfig new file mode 100644 index 0000000000..8c7e22cc33 --- /dev/null +++ b/board/intel/slimbootloader/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> + +if TARGET_SLIMBOOTLOADER + +config SYS_BOARD + default "slimbootloader" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "slimbootloader" + +config SYS_CONFIG_NAME + default "slimbootloader" + +config SYS_TEXT_BASE + default 0x00100000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYS_SLIMBOOTLOADER + select USB_STORAGE + select USB_KEYBOARD + +endif diff --git a/board/intel/slimbootloader/Makefile b/board/intel/slimbootloader/Makefile new file mode 100644 index 0000000000..fd8fa98a8d --- /dev/null +++ b/board/intel/slimbootloader/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> + +obj-y += start.o slimbootloader.o diff --git a/board/intel/slimbootloader/slimbootloader.c b/board/intel/slimbootloader/slimbootloader.c new file mode 100644 index 0000000000..f50eeb823f --- /dev/null +++ b/board/intel/slimbootloader/slimbootloader.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <common.h> + +int board_early_init_r(void) +{ + /* + * Make sure PCI bus is enumerated so that peripherals on the PCI bus + * can be discovered by their drivers. + * + * Slim Bootloader has already done PCI bus enumeration before loading + * U-Boot, so U-Boot needs to preserve PCI configuration. + * Therefore, '# CONFIG_PCI_PNP is not set' is included in defconfig. + */ + pci_init(); + + return 0; +} diff --git a/board/intel/slimbootloader/start.S b/board/intel/slimbootloader/start.S new file mode 100644 index 0000000000..5c3f3df09e --- /dev/null +++ b/board/intel/slimbootloader/start.S @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +/* board early initialization */ +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig new file mode 100644 index 0000000000..b16ed71469 --- /dev/null +++ b/configs/slimbootloader_defconfig @@ -0,0 +1,22 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_TARGET_SLIMBOOTLOADER=y +CONFIG_DEFAULT_DEVICE_TREE="slimbootloader" +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_MMC=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_CMD_USB=y +CONFIG_DOS_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_BOOTDELAY=10 +CONFIG_CONSOLE_SCROLL_LINES=5 +# CONFIG_PCI_PNP is not set diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index f416801910..f545dee87a 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -13,3 +13,4 @@ Intel edison galileo minnowmax + slimbootloader diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst new file mode 100644 index 0000000000..4b9c293c2d --- /dev/null +++ b/doc/board/intel/slimbootloader.rst @@ -0,0 +1,174 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Aiden Park <aiden.park(a)intel.com> + +Slim Bootloader +=============== + +Introduction +------------ + +This target is to enable U-Boot_ as a payload of `Slim Bootloader`_ (a.k.a SBL) +boot firmware which currently supports QEMU, Apollolake, Whiskeylake, +Coffeelake-R platforms. + +The `Slim Bootloader`_ is designed with multi-stages(Stage1A/B, Stage2, Payload) +architecture to cover from reset vector to OS booting and it consumes +`Intel FSP`_ for silicon initialization. + +* Stage1A: Reset vector, CAR init with FSP-T +* Stage1B: Memory init with FSP-M, CAR teardown, Continue execution in memory +* Stage2 : Rest of Silicon init with FSP-S, Create HOB, Hand-off to Payload +* Payload: Payload init with HOB, Load OS from media, Booting OS + +The Slim Bootloader stages(Stage1A/B, Stage2) focus on chipset, hardware and +platform specific initialization, and it provides useful information to a +payload in a HOB(Hand-Off Block) which has serial port, memory map, performance +data info and so on. This is Slim Bootloader architectural design to make a +payload light-weight, platform independent and more generic across different +boot solutions or payloads, and to minimize hardware re-initialization in a +payload. + +Build Instruction for U-Boot as a Slim Bootloader payload +--------------------------------------------------------- + +Build U-Boot and obtain u-boot-dtb.bin:: + + $ make distclean + $ make slimbootloader_defconfig + $ make all + +Prepare Slim Bootloader +----------------------- + +1. Setup Build Environment for Slim Bootloader. + + Refer to `Getting Started`_ page in `Slim Bootloader`_ document site. + +2. Get source code. Let's simply clone the repo:: + + $ git clone https://github.com/slimbootloader/slimbootloader.git + +3. Copy u-boot-dtb.bin to Slim Bootloader. + Slim Bootloader looks for a payload from the specific location. + Copy the build u-boot-dtb.bin to the expected location:: + + $ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/ + $ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin + +Build Instruction for Slim Bootloader for QEMU target +----------------------------------------------------- + +Slim Bootloader supports multiple payloads, and a board of Slim Bootloader +detects its target payload by PayloadId in board configuration. +The PayloadId can be any 4 Bytes value. + +1. Update PayloadId. Let's use 'U-BT' as an example:: + + $ vi Platform/QemuBoardPkg/CfgData/CfgDataExt_Brd1.dlt + -GEN_CFG_DATA.PayloadId | 'AUTO' + +GEN_CFG_DATA.PayloadId | 'U-BT' + +2. Update payload text base. PAYLOAD_EXE_BASE must be the same as U-Boot + CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig. + PAYLOAD_LOAD_HIGH must be 0:: + + $ vi Platform/QemuBoardPkg/BoardConfig.py + + self.PAYLOAD_LOAD_HIGH = 0 + + self.PAYLOAD_EXE_BASE = 0x00100000 + +3. Build QEMU target. Make sure u-boot-dtb.bin and U-BT PayloadId + in build command. The output is Outputs/qemu/SlimBootloader.bin:: + + $ python BuildLoader.py build qemu -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma" + +4. Launch Slim Bootloader on QEMU. + You should reach at U-Boot serial console:: + + $ qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio -pflash Outputs/qemu/SlimBootloader.bin + +Build Instruction for Slim Bootloader for LeafHill(APL) target +-------------------------------------------------------------- + +LeafHill is using PCI UART2 device as a serial port. +For MEM32 serial port, CONFIG_SYS_NS16550_MEM32 needs to be enabled in U-Boot. + +1. Enable CONFIG_SYS_NS16550_MEM32 in U-Boot:: + + $ vi include/configs/slimbootloader.h + +#define CONFIG_SYS_NS16550_MEM32 + #ifdef CONFIG_SYS_NS16550_MEM3 + +2. Build U-Boot:: + + $ make disclean + $ make slimbootloader_defconfig + $ make all + +3. Copy u-boot-dtb.bin to Slim Bootloader. + Slim Bootloader looks for a payload from the specific location. + Copy the build u-boot-dtb.bin to the expected location:: + + $ mkdir -p <Slim Bootloader Dir>/PayloadPkg/PayloadBins/ + $ cp <U-Boot Dir>/u-boot-dtb.bin <Slim Bootloader Dir>/PayloadPkg/PayloadBins/u-boot-dtb.bin + +4. Update PayloadId. Let's use 'U-BT' as an example:: + + $ vi Platform/ApollolakeBoardPkg/CfgData/CfgData_Int_LeafHill.dlt + -GEN_CFG_DATA.PayloadId | 'AUTO + +GEN_CFG_DATA.PayloadId | 'U-BT' + +5. Update payload text base. + +* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE + in board/intel/slimbootloader/Kconfig. +* PAYLOAD_LOAD_HIGH must be 0:: + + $ vi Platform/ApollolakeBoardPkg/BoardConfig.py + + self.PAYLOAD_LOAD_HIGH = 0 + + self.PAYLOAD_EXE_BASE = 0x00100000 + +6. Build APL target. Make sure u-boot-dtb.bin and U-BT PayloadId + in build command. The output is Outputs/apl/Stitch_Components.zip:: + + $ python BuildLoader.py build apl -p "OsLoader.efi:LLDR:Lz4;u-boot-dtb.bin:U-BT:Lzma" + +7. Stitch IFWI. + + Refer to Apollolake_ page in Slim Bootloader document site:: + + $ python Platform/ApollolakeBoardPkg/Script/StitchLoader.py -i <Existing IFWI> -s Outputs/apl/Stitch_Components.zip -o <Output IFWI> + +8. Flash IFWI. + + Use DediProg to flash IFWI. You should reach at U-Boot serial console. + + +Build Instruction to use ELF U-Boot +----------------------------------- + +1. Enable CONFIG_OF_EMBED:: + + $ vi configs/slimbootloader_defconfig + +CONFIG_OF_EMBED=y + +2. Build U-Boot:: + + $ make disclean + $ make slimbootloader_defconfig + $ make all + $ strip u-boot (removing symbol for reduced size) + +3. Do same steps as above + +* Copy u-boot(ELF) to PayloadBins directory +* Update PayloadId 'U-BT' as above. +* No need to set PAYLOAD_LOAD_HIGH and PAYLOAD_EXE_BASE. +* Build Slim Bootloader. Use u-boot instead of u-boot-dtb.bin:: + + $ python BuildLoader.py build <qemu or apl> -p "OsLoader.efi:LLDR:Lz4;u-boot:U-BT:Lzma" + +.. _U-Boot: https://gitlab.denx.de/ +.. _`Slim Bootloader`: https://github.com/slimbootloader/ +.. _`Intel FSP`: https://github.com/IntelFsp/ +.. _`Getting Started`: https://slimbootloader.github.io/getting-started/ +.. _Apollolake: https://slimbootloader.github.io/supported-hardware/apollo-lake-crb.html#st… diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h new file mode 100644 index 0000000000..e0011ed446 --- /dev/null +++ b/include/configs/slimbootloader.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef __SLIMBOOTLOADER_CONFIG_H__ +#define __SLIMBOOTLOADER_CONFIG_H__ + +#include <configs/x86-common.h> + +/* + * By default, CONFIG_SYS_NS16550_PORT_MAPPED is enabled for port io serial. + * To use mmio base serial, enable CONFIG_SYS_NS16550_MEM32 and disable + * CONFIG_SYS_NS16550_PORT_MAPPED until ns16550 driver supports serial port + * configuration in run-time. + * + * #define CONFIG_SYS_NS16550_MEM32 + * #undef CONFIG_SYS_NS16550_PORT_MAPPED + */ +#ifdef CONFIG_SYS_NS16550_MEM32 +#undef CONFIG_SYS_NS16550_PORT_MAPPED +#endif + +#define CONFIG_STD_DEVICES_SETTINGS \ + "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* + * Override CONFIG_EXTRA_ENV_SETTINGS in x86-common.h + */ +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_STD_DEVICES_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=0x4000000\0" \ + "ramdiskfile=initrd\0" \ + "bootdev=usb\0" \ + "bootdevnum=0\0" \ + "bootdevpart=0\0" \ + "bootfsload=fatload\0" \ + "bootusb=setenv bootdev usb; boot\0" \ + "bootscsi=setenv bootdev scsi; boot\0" \ + "bootmmc=setenv bootdev mmc; boot\0" \ + "bootargs=console=ttyS0,115200 console=tty0\0" + +/* + * Override CONFIG_BOOTCOMMAND in x86-common.h + */ +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "if test ${bootdev} = \"usb\"; then ${bootdev} start; fi; " \ + "if test ${bootdev} = \"scsi\"; then ${bootdev} scan; fi; " \ + "${bootdev} info; " \ + "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \ + "${loadaddr} ${bootfile}; " \ + "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \ + "${ramdiskaddr} ${ramdiskfile}; " \ + "zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}" + +#endif /* __SLIMBOOTLOADER_CONFIG_H__ */ -- 2.20.1

2 2

[U-Boot] [PATCH] sifive: riscv: streamline HiFive Unleashed configuration infrastructure
by Sagar Shrikant Kadam 01 Aug '19

01 Aug '19

This patch is intended to update the current configuration implementation of HiFive Unleashed board so that it is as per the guidelines provided in U-boot's doc/README.kconfig. The board has a FU540-C000 SoC built around U54-MC Core complex. This patch is based on the commit 75551c8bfc95 ("Merge branch '2019-07-26-ti-imports'") in master branch of repo[1] and is tested with OpenSBI to use the dtb passed as argument in FW_PAYLOAD_FDT_PATH from the mainline kernel and boot's linux image over tftp. The patch is available for testing at dev/sagark/sifive_u540defconfig branch here [2]. [1] http://git.denx.de/u-boot-riscv.git [2] https://github.com/sagsifive/u-boot Summary: -Update TARGET in board select menu. -Update SYS_CPU from generic to u54-mc. -Added SYS_SOC. -Update SYS_BOARD from fu540 to hifive_unleashed. -Update SYS_CONFIG_NAME from sifive-u540 to hifive_unleashed . -Update MAINTAINERS file with relevant entries corresponding to the above changes. This patch will conflict with few patches which are already submitted for review, it would be good if U-boot folks would suggest something accordingly. Sagar Shrikant Kadam (1): sifive: riscv: update Hifive Unleashed configuration infrastructure arch/riscv/Kconfig | 6 +- arch/riscv/cpu/generic/Kconfig | 12 --- arch/riscv/cpu/generic/Makefile | 6 -- arch/riscv/cpu/generic/cpu.c | 35 ------- arch/riscv/cpu/generic/dram.c | 37 ------- arch/riscv/cpu/u54-mc/Kconfig | 12 +++ arch/riscv/cpu/u54-mc/Makefile | 6 ++ arch/riscv/cpu/u54-mc/cpu.c | 35 +++++++ arch/riscv/cpu/u54-mc/dram.c | 37 +++++++ arch/riscv/include/asm/arch-fu540-c000/clk.h | 14 +++ arch/riscv/include/asm/arch-generic/clk.h | 14 --- board/sifive/fu540/Kconfig | 49 ---------- board/sifive/fu540/MAINTAINERS | 9 -- board/sifive/fu540/Makefile | 5 - board/sifive/fu540/fu540.c | 139 --------------------------- board/sifive/hifive_unleashed/Kconfig | 52 ++++++++++ board/sifive/hifive_unleashed/MAINTAINERS | 9 ++ board/sifive/hifive_unleashed/Makefile | 5 + board/sifive/hifive_unleashed/fu540.c | 139 +++++++++++++++++++++++++++ configs/hifive_unleashed_defconfig | 11 +++ configs/sifive_fu540_defconfig | 11 --- include/configs/hifive_unleashed.h | 47 +++++++++ include/configs/sifive-fu540.h | 47 --------- 23 files changed, 370 insertions(+), 367 deletions(-) delete mode 100644 arch/riscv/cpu/generic/Kconfig delete mode 100644 arch/riscv/cpu/generic/Makefile delete mode 100644 arch/riscv/cpu/generic/cpu.c delete mode 100644 arch/riscv/cpu/generic/dram.c create mode 100644 arch/riscv/cpu/u54-mc/Kconfig create mode 100644 arch/riscv/cpu/u54-mc/Makefile create mode 100644 arch/riscv/cpu/u54-mc/cpu.c create mode 100644 arch/riscv/cpu/u54-mc/dram.c create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h delete mode 100644 board/sifive/fu540/Kconfig delete mode 100644 board/sifive/fu540/MAINTAINERS delete mode 100644 board/sifive/fu540/Makefile delete mode 100644 board/sifive/fu540/fu540.c create mode 100644 board/sifive/hifive_unleashed/Kconfig create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS create mode 100644 board/sifive/hifive_unleashed/Makefile create mode 100644 board/sifive/hifive_unleashed/fu540.c create mode 100644 configs/hifive_unleashed_defconfig delete mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/hifive_unleashed.h delete mode 100644 include/configs/sifive-fu540.h -- 2.7.4

5 11

[U-Boot] [PATCH 0/10] x86: Add generic VESA video driver
by Simon Glass 01 Aug '19

01 Aug '19

This series introduces a generic VESA video driver and adjusts the generic PCI ROM support to support it. It also fixes up some problems which prevent this from working on PowerPC at present. It is now possible to use VESA graphics: - On PowerPC, using the x86 emulator - On x86, using either the x86 emulator or native code execution As it turns out, on the only platform I have tested (link), the x86 emulator is only slightly slower that native code execution (200ms difference). Still, we may as well leave this feature in there. VGA ROMs are a very old technology but they are still used by modern platforms, including at least link and some Atom designs. Simon Glass (10): bios_emulator: Fix an #ifdef typo in the header file x86: Correct endianness isues in pci_rom x86: Support ROMs on other archs bios_emulator: Don't display error when emulator terminates bios_emulator: Add some VESA interface debugging x86: pci: Don't stop when we get a vendor/device mismatch x86: Add a VESA video driver x86: Drop the x86_fb driver x86: Access the VGA ROM when needed RFC: Test code for glacier PCI video support arch/x86/include/asm/u-boot-x86.h | 2 + drivers/bios_emulator/atibios.c | 161 +++++++++++++++++++++++---- drivers/bios_emulator/include/x86emu/debug.h | 2 +- drivers/bios_emulator/x86emu/ops.c | 2 +- drivers/pci/pci_auto.c | 28 ++++- drivers/pci/pci_rom.c | 40 ++++--- drivers/video/Makefile | 2 +- drivers/video/vesa_fb.c | 64 +++++++++++ drivers/video/x86_fb.c | 38 ------- include/configs/canyonlands.h | 31 ++++++ include/configs/chromebook_link.h | 2 +- include/pci.h | 9 ++ include/pci_rom.h | 1 - include/vbe.h | 9 +- 14 files changed, 312 insertions(+), 79 deletions(-) create mode 100644 drivers/video/vesa_fb.c delete mode 100644 drivers/video/x86_fb.c -- 2.2.0.rc0.207.ga3a616c

3 42

[U-Boot] [PATCH] board_r: re-order the board_early_init_r()
by Kever Yang 01 Aug '19

01 Aug '19

The board_early_init_r() suppose to be called before board_init(), then the board callback functions in board_r will be: - board_early_init_r() - board_init() - board_late_init() Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- common/board_r.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index abc31b17b8..c5e33c4654 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -681,6 +681,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_DM initr_dm, #endif +#if defined(CONFIG_BOARD_EARLY_INIT_R) + board_early_init_r, +#endif #if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \ defined(CONFIG_SANDBOX) board_init, /* Setup chipselects */ @@ -712,9 +715,6 @@ static init_fnc_t init_sequence_r[] = { #endif #ifdef CONFIG_ADDR_MAP initr_addr_map, -#endif -#if defined(CONFIG_BOARD_EARLY_INIT_R) - board_early_init_r, #endif INIT_FUNC_WATCHDOG_RESET #ifdef CONFIG_POST -- 2.17.1

4 7

[U-Boot] [PATCH v2 0/7] Add PCIe root complex support for AM654x SoC
by Sekhar Nori 01 Aug '19

01 Aug '19

Hi, This patch series adds PCIe root complex support for AM654x SoC. The device-tree files are based on bindings accepted in linux. See files Documentation/devicetree/bindings/phy/ti,phy-am654-serdes.txt and Documentation/devicetree/bindings/pci/pci-keystone.txt in latest mainline master. I have not posted the actual board-specific device-tree bits yet. The reason is that PCIe slot is on a daughter card on the AM65x EVM. I want to see how we can support that as an overlay in U-Boot. That needs some more attention. Meanwhile I have tested this using a patch that simply enables PCIe in the baseboard device-tree file itself. v2: - add unit tests for new clock and dm APIs introduced - add Lokesh's Reviewed-by: for patches #1 and #2 Sekhar Nori (7): clk: add support for clk_is_match() dm: core: add support for getting register address and size pcie: ti: add driver for AM65x PCIe RC phy: add support for AM654x SERDES configs: am65x_evm_a53: enable PCIe support arm: dts: k3-am65: add support for PCIe and SERDES configs: am65x_evm_a53: enable support for PCIe ethernet cards arch/arm/dts/k3-am65-main.dtsi | 108 +++++ arch/arm/dts/k3-am65.dtsi | 1 + configs/am65x_evm_a53_defconfig | 9 + drivers/clk/clk-uclass.c | 13 + drivers/core/fdtaddr.c | 17 + drivers/core/read.c | 20 + drivers/pci/Kconfig | 6 + drivers/pci/Makefile | 1 + drivers/pci/pcie_dw_ti.c | 725 +++++++++++++++++++++++++++++ drivers/phy/Kconfig | 9 + drivers/phy/Makefile | 1 + drivers/phy/phy-ti-am654.c | 411 ++++++++++++++++ include/clk.h | 13 + include/dm/fdtaddr.h | 18 + include/dm/read.h | 41 ++ include/dt-bindings/phy/phy-am654-serdes.h | 13 + test/dm/clk.c | 1 + test/dm/test-fdt.c | 16 +- 18 files changed, 1419 insertions(+), 4 deletions(-) create mode 100644 drivers/pci/pcie_dw_ti.c create mode 100644 drivers/phy/phy-ti-am654.c create mode 100644 include/dt-bindings/phy/phy-am654-serdes.h -- 2.16.2

3 13

[U-Boot] [PATCH v1] colibri_imx7: boot kernel in secure mode
by Igor Opaniuk 01 Aug '19

01 Aug '19

From: Igor Opaniuk <igor.opaniuk(a)toradex.com> NXP downstream kernel uses legacy method to enable other cores, which requires kernel to run in a security mode (althought upstream kernel uses PSCI for this). As we're using NXP kernel in our BSPs, lets enable this by default. Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> --- include/configs/colibri_imx7.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 40173b18fa..5408577661 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -164,7 +164,8 @@ "${board}/flash_blk.img && source ${loadaddr}\0" \ "setup=setenv setupargs " \ "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} consoleblank=0\0" \ + ",${baudrate}n8 ${memargs} consoleblank=0; " \ + "setenv bootm_boot_mode sec\0" \ "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ "setusbupdate=usb start && setenv interface usb && " \ "fatload ${interface} 0:1 ${loadaddr} " \ -- 2.17.1

6 12

[U-Boot] [PATCH v1 0/9] apalis-tk1: fixes/updates for v2019.10
by Igor Opaniuk 01 Aug '19

01 Aug '19

Misc. fixes related to pinmux configuration (fan), default bootargs, reset reason output and power rail configuration. Dominik Sliwa (2): apalis-tk1/t30: colibri_t30: display reset reason apalis-tk1: remove non-esential power rails on boot Igor Opaniuk (5): apalis-tk1: set apalis gpio 8 aka fan_en apalis-tk1: provide proper USB vendor id apalis-tk1: enable user debug by default apalis-tk1: add pcie_aspm=off to defargs apalis-tk1: switch to zImage Marcel Ziswiler (2): apalis-tk1: do not explicitly release reset_moci# apalis-tk1: remove default vesa vga mode from vidargs arch/arm/mach-tegra/sys_info.c | 32 ++++++++----- arch/arm/mach-tegra/tegra124/cpu.c | 45 +++++++++++++++++++ board/toradex/apalis-tk1/apalis-tk1.c | 10 +++++ board/toradex/apalis-tk1/as3722_init.c | 23 ++++++++++ .../apalis-tk1/pinmux-config-apalis-tk1.h | 2 +- configs/apalis-tk1_defconfig | 2 +- include/configs/apalis-tk1.h | 17 +++---- 7 files changed, 111 insertions(+), 20 deletions(-) -- 2.17.1

4 18

[U-Boot] [PATCH v3] x86: ich-spi: Convert driver to spi-mem ops
by Bernhard Messerklinger 01 Aug '19

01 Aug '19

With the introduction of the new spi-mem model operations changed slightly. The new spi-mem operations make things a bit easier to handle for ich-spi flash interface. This patch converts the ich-spi driver by using spi-mem operations. --- Changes in v2: - make 2 routines static; update commit message a little bit Changes in v3: - update erase op code handling to work with latest master spi-nor driver Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger(a)br-automation.com> --- drivers/spi/ich.c | 267 +++++++++++++++++----------------------------- drivers/spi/ich.h | 9 +- 2 files changed, 100 insertions(+), 176 deletions(-) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 03531a8c0c..179f801d42 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -14,6 +14,8 @@ #include <pci_ids.h> #include <spi.h> #include <asm/io.h> +#include <spi-mem.h> +#include <div64.h> #include "ich.h" @@ -171,18 +173,6 @@ static int ich_init_controller(struct udevice *dev, return 0; } -static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase) { if (plat->ich_version == ICHV_7) { @@ -213,47 +203,12 @@ static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase) return lock != 0; } -static void spi_setup_type(struct spi_trans *trans, int data_bytes) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes */ - if (trans->bytesin == 0) { - if (trans->bytesout + data_bytes > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, bool lock) { uint16_t optypes; uint8_t opmenu[ctlr->menubytes]; - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); if (!lock) { /* The lock is off, so just use index 0. */ ich_writeb(ctlr, trans->opcode, ctlr->opmenu); @@ -285,12 +240,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, optypes = ich_readw(ctlr, ctlr->optype); optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } + if (optype != trans->type) { printf("ICH SPI: Transaction doesn't fit type %d\n", optype); @@ -300,26 +250,6 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, } } -static int spi_setup_offset(struct spi_trans *trans) -{ - /* Separate the SPI address and data */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printf("Unrecognized SPI transaction type %#x\n", trans->type); - return -EPROTO; - } -} - /* * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set * below is true) or 0. In case the wait was for the bit(s) to set - write @@ -350,7 +280,7 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, return -ETIMEDOUT; } -void ich_spi_config_opcode(struct udevice *dev) +static void ich_spi_config_opcode(struct udevice *dev) { struct ich_spi_priv *ctlr = dev_get_priv(dev); @@ -365,72 +295,48 @@ void ich_spi_config_opcode(struct udevice *dev) ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); } -static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { - struct udevice *bus = dev_get_parent(dev); + struct udevice *bus = dev_get_parent(slave->dev); struct ich_spi_platdata *plat = dev_get_platdata(bus); struct ich_spi_priv *ctlr = dev_get_priv(bus); - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - int bytes = bitlen / 8; struct spi_trans *trans = &ctlr->trans; - unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); - int using_cmd = 0; + u16 control; + u16 opcode_index; + int ret = 0; + int status; bool lock = spi_lock_status(plat, ctlr->base); - int ret; - - /* We don't support writing partial bytes */ - if (bitlen % 8) { - debug("ICH SPI: Accessing partial bytes not supported\n"); - return -EPROTONOSUPPORT; - } - - /* An empty end transaction can be ignored */ - if (type == SPI_XFER_END && !dout && !din) - return 0; + bool with_address = 0; - if (type & SPI_XFER_BEGIN) - memset(trans, '\0', sizeof(*trans)); + trans->in = NULL; + trans->out = NULL; + trans->type = 0xFF; - /* Dp we need to come back later to finish it? */ - if (dout && type == SPI_XFER_BEGIN) { - if (bytes > ICH_MAX_CMD_LEN) { - debug("ICH SPI: Command length limit exceeded\n"); - return -ENOSPC; + if (op->data.nbytes) { + if (op->data.dir == SPI_MEM_DATA_IN) { + trans->in = op->data.buf.in; + trans->bytesin = op->data.nbytes; + } else { + trans->out = op->data.buf.out; + trans->bytesout = op->data.nbytes; } - memcpy(trans->cmd, dout, bytes); - trans->cmd_len = bytes; - debug_trace("ICH SPI: Saved %d bytes\n", bytes); - return 0; } - /* - * We process a 'middle' spi_xfer() call, which has no - * SPI_XFER_BEGIN/END, as an independent transaction as if it had - * an end. We therefore repeat the command. This is because ICH - * seems to have no support for this, or because interest (in digging - * out the details and creating a special case in the code) is low. - */ - if (trans->cmd_len) { - trans->out = trans->cmd; - trans->bytesout = trans->cmd_len; - using_cmd = 1; - debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); - } else { - trans->out = dout; - trans->bytesout = dout ? bytes : 0; - } + if (trans->opcode != op->cmd.opcode) + trans->opcode = op->cmd.opcode; - trans->in = din; - trans->bytesin = din ? bytes : 0; + if (lock && trans->opcode == SPI_OPCODE_WRDIS) + return 0; - /* There has to always at least be an opcode */ - if (!trans->bytesout) { - debug("ICH SPI: No opcode for transfer\n"); - return -EPROTO; + if (trans->opcode == SPI_OPCODE_WREN) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + if (!lock) + ich_writew(ctlr, trans->opcode, ctlr->preop); + return 0; } ret = ich_status_poll(ctlr, SPIS_SCIP, 0); @@ -442,23 +348,30 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, else ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); - spi_setup_type(trans, using_cmd ? bytes : 0); + /* Try to guess spi transaction type */ + if (op->data.dir == SPI_MEM_DATA_OUT) { + if (op->addr.nbytes) + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + } else { + if (op->addr.nbytes) + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + } + /* Special erase case handling */ + if (op->addr.nbytes && !op->data.buswidth) + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + opcode_index = spi_setup_opcode(ctlr, trans, lock); if (opcode_index < 0) return -EINVAL; - with_address = spi_setup_offset(trans); - if (with_address < 0) - return -EINVAL; - if (trans->opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!lock) - ich_writew(ctlr, trans->opcode, ctlr->preop); - return 0; + /* Handle special case for erase where address is stored in data */ + if (op->addr.nbytes) { + trans->offset = op->addr.val; + with_address = 1; } if (ctlr->speed && ctlr->max_speed >= 33000000) { @@ -472,13 +385,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, ich_writeb(ctlr, byte, ctlr->speed); } - /* See if we have used up the command data */ - if (using_cmd && dout && bytes) { - trans->out = dout; - trans->bytesout = bytes; - debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); - } - /* Preset control fields */ control = SPIC_SCGO | ((opcode_index & 0x07) << 4); @@ -513,22 +419,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, return 0; } - /* - * Check if this is a write command atempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans->bytesout > ctlr->databytes) { - debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); - return -EPROTO; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ while (trans->bytesout || trans->bytesin) { uint32_t data_length; @@ -543,9 +433,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, /* Program data into FDATA0 to N */ if (trans->bytesout) { write_reg(ctlr, trans->out, ctlr->data, data_length); - spi_use_out(trans, data_length); - if (with_address) - trans->offset += data_length; + trans->bytesout -= data_length; } /* Add proper control fields' values */ @@ -568,9 +456,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, if (trans->bytesin) { read_reg(ctlr, ctlr->data, trans->in, data_length); - spi_use_in(trans, data_length); - if (with_address) - trans->offset += data_length; + trans->bytesin -= data_length; } } @@ -581,6 +467,40 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, return 0; } +static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op) +{ + size_t page_offset; + int addr = op->addr.val; + unsigned int byte_count = op->data.nbytes; + + if (hweight32(ICH_BOUNDARY) == 1) { + page_offset = addr & (ICH_BOUNDARY - 1); + } else { + u64 aux = addr; + + page_offset = do_div(aux, ICH_BOUNDARY); + } + + if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) { + op->data.nbytes = min(ICH_BOUNDARY - page_offset, + slave->max_read_size); + } else if (slave->max_write_size) { + op->data.nbytes = min(ICH_BOUNDARY - page_offset, + slave->max_write_size); + } + + op->data.nbytes = min(op->data.nbytes, byte_count); + + return 0; +} + +static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + printf("ICH SPI: Only supports memory operations\n"); + return -1; +} + static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); @@ -686,10 +606,17 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) return ret; } +static const struct spi_controller_mem_ops ich_controller_mem_ops = { + .adjust_op_size = ich_spi_adjust_size, + .supports_op = NULL, + .exec_op = ich_spi_exec_op, +}; + static const struct dm_spi_ops ich_spi_ops = { .xfer = ich_spi_xfer, .set_speed = ich_spi_set_speed, .set_mode = ich_spi_set_mode, + .mem_ops = &ich_controller_mem_ops, /* * cs_info is not needed, since we require all chip selects to be * in the device tree explicitly diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index a974241f98..3dfb2aaff1 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -100,13 +100,8 @@ enum { HSFC_FSMIE = 0x8000 }; -enum { - ICH_MAX_CMD_LEN = 5, -}; - struct spi_trans { - uint8_t cmd[ICH_MAX_CMD_LEN]; - int cmd_len; + uint8_t cmd; const uint8_t *out; uint32_t bytesout; uint8_t *in; @@ -166,6 +161,8 @@ struct spi_trans { #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define ICH_BOUNDARY 0x1000 + enum ich_version { ICHV_7, ICHV_9, -- 2.22.0

2 1