June 2019 - U-Boot

[U-Boot] [PATCH 1/1] board/freescale/common: secure_boot: Set bootdelay to -2.
by Udit Agarwal 19 Jun '19

19 Jun '19

Uboot prompt must not be available while running secure boot. TO ensure this bootdelay must be set to -2. Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> --- board/freescale/common/fsl_chain_of_trust.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 97376c4165..dddfd26a13 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -79,7 +79,7 @@ int fsl_setenv_chain_of_trust(void) * bootdelay = 0 (To disable Boot Prompt) * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) */ - env_set("bootdelay", "0"); + env_set("bootdelay", "-2"); #ifdef CONFIG_ARM env_set("secureboot", "y"); -- 2.17.1

2 1

[U-Boot] [PATCH v5 1/2] armv8: fsl-lsch3: add clock support for the second eSDHC
by Yinbo Zhu 19 Jun '19

19 Jun '19

From: Yangbo Lu <yangbo.lu(a)nxp.com> Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- Change in v2: Change in v3: Remove non-TFA patch Change in v4: update the Copyright information Change in v5: Add NXP Copyright information arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 4 +++- arch/arm/include/asm/arch-fsl-layerscape/clock.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index bc268e207c..2d92d267a2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2014-2015, Freescale Semiconductor, Inc. + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP Semiconductors * * Derived from arch/power/cpu/mpc85xx/speed.c */ @@ -214,6 +215,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index cf058d22a9..2f51155f21 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP Semiconductors * */ @@ -14,6 +15,7 @@ enum mxc_clock { MXC_BUS_CLK, MXC_UART_CLK, MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; -- 2.17.1

2 3

[U-Boot] [PATCH v3] armv8: fsl-lsch2: add clock support for the second eSDHC
by Yinbo Zhu 19 Jun '19

19 Jun '19

Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- Change in v2: Update the Copyright information Change in v3: Add "* Copyright 2019 NXP." arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 723d7eac5d..9ece4b90e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP. */ #include <common.h> @@ -250,6 +251,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: -- 2.17.1

2 1

[U-Boot] [PATCH] armv8: ls1028a: Add secure boot defconfig
by Yuantian Tang 19 Jun '19

19 Jun '19

Add secure boot defconfig for ls1028aqds and ls1028ardb boards. Signed-off-by: Yuantian Tang <andy.tang(a)nxp.com> --- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 62 ++++++++++++++++++++ configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 62 ++++++++++++++++++++ include/configs/ls1028a_common.h | 4 ++ 3 files changed, 128 insertions(+) create mode 100644 configs/ls1028aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/ls1028ardb_tfa_SECURE_BOOT_defconfig diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..7cd2f59d7b --- /dev/null +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028AQDS=y +CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y +CONFIG_RSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..3432f90087 --- /dev/null +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028ARDB=y +CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y +CONFIG_RSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 9531548184..aeb2c7251a 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -215,4 +215,8 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + #endif /* __L1028A_COMMON_H */ -- 2.17.1

2 1

[U-Boot] [PATCH] fsl-layerscape/ls1046a_serdes.c: fix 0x3363 serdes1 setting
by Maciej Pijanowski 19 Jun '19

19 Jun '19

According to the table 31-1 in the QorIQ LS1046A Reference Manual, Rev. 2, 11/2018, the D lane of SerDes1 uses following settings: - SGMII.9, not SGMII.5 for D lane, - SGMII.10, not SGMII.6 for C lane. Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Cc: prabhakar.kushwaha(a)nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index f8310f210556..91de5ff0d3da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -29,7 +29,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, - {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, + {0x3363, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, -- 2.7.4

2 1

[U-Boot] [PATCH] fsl-layerscape/ls1046a_serdes.c: add 0x3040 serdes1 setting
by Maciej Pijanowski 19 Jun '19

19 Jun '19

According to the table 31-1 in the QorIQ LS1046A Reference Manual, Rev. 2, 11/2018, the 0x3040 is also a valid setting for the SerDes1. With the current codebase, following message appears when 0x3040 is used: SERDES1[PRTCL] = 0x3040 is not valid Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Cc: prabhakar.kushwaha(a)nxp.com Cc: piotr.krol(a)3mdeb.com --- arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index 91de5ff0d3da..12775c65433b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -33,6 +33,7 @@ static struct serdes_config serdes1_cfg_tbl[] = { SGMII_FM1_DTSEC6} }, {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x3040, {SGMII_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} }, {} }; -- 2.7.4

2 1

[U-Boot] [PATCH v4 0/6] DM: Convert i.MX28 gpio, pinmux, spi and eth drivers to DM/DTS
by Lukasz Majewski 19 Jun '19

19 Jun '19

This patch series converts some i.MX28 drivers to use DM/DTS. Converted drivers: - mxs_gpio.c - gpio driver - pinctrl-mxs.c - pinmux driver - Adjust fec_eth.c to support also i.MX28 SoC. - mxs_spi.c - SPI driver After applying this series it is possible to use ETH on i.MX28 board with following DTS description: &mac0 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; phy-supply = <&reg_fec_3v3>; phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; phy-reset-post-delay = <1>; status = "okay"; fixed-link { speed = <100>; full-duplex; }; }; And store the received binaries on SPI-NOR memory. Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/547299325 Applied on top of u-boot/master branch SHA1: c2ea87883ef309570c8903e6de4b8b78685d73d0 Changes in v4: - Add 12 digit SHA1 ID for tag v5.1.9 - Sort the entries for compatibles and Kconfig - New file - imx28-u-boot.dtsi - Use BIT() macro instead of 1 << offset - Use devfdt_get_addr to get gpio number - Use gpio-ranges property to setup gpios - Use Linux kernel code to setup pins instead of Barebox - Add soc specific data and compatible for i.MX23 and i.MX28 - Use devm_kfree() to release temporary memory - Adjust the driver to support i.MX23 (add compatible, adjust clk code) - Use BIT() macro where applicable Changes in v3: - Update tag to 5.1.9 - Set more apropriate tags - Set more apropriate tags - Set more apropriate tags - Set more apropriate tags - Set more appropriate tags Changes in v2: - Use #if !CONFIG_IS_ENABLED(DM_GPIO) instead of plain #ifdef CONFIG_DM_GPIO - New patch (conversion of mxs_spi.c to DM_SPI) Lukasz Majewski (6): ARM: dts: imx: Copy imx28 device tree related files from Linux kernel (v5.1.9) ARM: imx: net: Enable support for i.MX28 DM_ETH in the fec_mxc.c driver DTS: dm: mxs: gpio: Provide 'gpio-ranges' for mxs_gpio driver ARM: dm: mxs: gpio: Add support for DM/DTS in the mxs_gpio.c driver (DM_GPIO) ARM: imx: pinctrl: Add support for i.MX2[38] mxs pinctrl driver ARM: dm: spi: Add support DM/DTS for i.MX28 mxs SPI driver (DM_SPI conversion) arch/arm/dts/imx28-pinfunc.h | 506 ++++++++++++++ arch/arm/dts/imx28-u-boot.dtsi | 28 + arch/arm/dts/imx28.dtsi | 1330 +++++++++++++++++++++++++++++++++++++ arch/arm/dts/mxs-pinfunc.h | 31 + drivers/gpio/mxs_gpio.c | 148 +++++ drivers/net/Kconfig | 2 +- drivers/net/fec_mxc.c | 1 + drivers/pinctrl/nxp/Kconfig | 10 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-mxs.c | 200 ++++++ drivers/pinctrl/nxp/pinctrl-mxs.h | 55 ++ drivers/spi/mxs_spi.c | 400 ++++++++--- 12 files changed, 2628 insertions(+), 84 deletions(-) create mode 100644 arch/arm/dts/imx28-pinfunc.h create mode 100644 arch/arm/dts/imx28-u-boot.dtsi create mode 100644 arch/arm/dts/imx28.dtsi create mode 100644 arch/arm/dts/mxs-pinfunc.h create mode 100644 drivers/pinctrl/nxp/pinctrl-mxs.c create mode 100644 drivers/pinctrl/nxp/pinctrl-mxs.h -- 2.11.0

2 14

[U-Boot] [PATCH v3 0/5] Update SiFive Unleashed Drivers
by Anup Patel 19 Jun '19

19 Jun '19

This series update SiFive Unleashed clock driver so that: 1. It is in sync with upstream Linux driver 2. It uses latest DT bindings as-per upstream Linux driver With this series, we can now use latest DT bindings with U-Boot. I have tested SiFive Serial driver and Cadence MACB ethernet driver with this changes and both work fine. The legacy FSBL will still pass DTB to U-Boot with older DT bindings which will break the updated SiFive Unleashed clock driver. To tackle this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive Unleashed so that OpenSBI will override and pass updated DTB to U-Boot. In fact, the updated DTB passed by OpenSBI can be used by latest Linux (i.e. V5.2-rc1 or higher) as well. The OpenSBI changes to embed SiFive Unleashed DTB can be found in sifive_unleashed_dtb_fix_v3 branch of: https://github.com/avpatel/opensbi.git This series can be found in riscv_unleashed_clk_sync_v3 branch of: https://github.com/avpatel/u-boot.git Changes since v2: - Dropped PATCH6 which adds new compatible string to MACB driver because more changes are required in MACB driver for different ethernet speeds Changes since v1: - Dropped GEMGXL clock driver - Added new compatible string for SiFive MACB ethernet Anup Patel (5): clk: sifive: Factor-out PLL library as separate module clk: sifive: Sync-up WRPLL library with upstream Linux clk: sifive: Sync-up DT bindings header with upstream Linux clk: sifive: Sync-up main driver with upstream Linux clk: sifive: Drop GEMGXL clock driver board/sifive/fu540/Kconfig | 1 - drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/analogbits/Kconfig | 4 + drivers/clk/analogbits/Makefile | 3 + .../{sifive => analogbits}/wrpll-cln28hpc.c | 168 ++++++++---------- drivers/clk/sifive/Kconfig | 10 -- drivers/clk/sifive/Makefile | 4 - drivers/clk/sifive/fu540-prci.c | 123 +++++++------ drivers/clk/sifive/gemgxl-mgmt.c | 60 ------- include/dt-bindings/clk/sifive-fu540-prci.h | 29 --- include/dt-bindings/clock/sifive-fu540-prci.h | 18 ++ .../linux/clk}/analogbits-wrpll-cln28hpc.h | 70 +++----- 13 files changed, 195 insertions(+), 297 deletions(-) create mode 100644 drivers/clk/analogbits/Kconfig create mode 100644 drivers/clk/analogbits/Makefile rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (69%) delete mode 100644 drivers/clk/sifive/gemgxl-mgmt.c delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (52%) -- 2.17.1

3 7

[U-Boot] Possible bug in imx6ul nand
by Shyam Saini 19 Jun '19

19 Jun '19

Hello Everyone, I tried to run "nand erase.part" and "nand erase.chip" on imx6ul isiot board and it hangs up and after some time it starts to give this error message: MXS NAND: DMA read error MXS NAND: Error sending command I printed error number which was -110, did anybody else face this problem? I did try to erase nand with "flash_erase" from linux and it worked with throwing any error. In and all it seems like a uboot issue. Thanks a lot, Shyam

2 1

[U-Boot] [PATCH v2 0/6] Update SiFive Unleashed Drivers
by Anup Patel 19 Jun '19

19 Jun '19

This series update SiFive Unleashed clock and ethernet drivers so that: 1. It is in sync with upstream Linux driver 2. It uses latest DT bindings as-per upstream Linux driver With this series, we can now use latest DT bindings with U-Boot. I have tested SiFive Serial driver and Cadence MACB ethernet driver with this changes and both work fine. The legacy FSBL will still pass DTB to U-Boot with older DT bindings which will break the updated SiFive Unleashed clock driver. To tackle this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive Unleashed so that OpenSBI will override and pass updated DTB to U-Boot. In fact, the updated DTB passed by OpenSBI can be used by latest Linux (i.e. V5.2-rc1 or higher) as well. The OpenSBI changes to embed SiFive Unleashed DTB can be found in sifive_unleashed_dtb_fix_v2 branch of: https://github.com/avpatel/opensbi.git This series can be found in riscv_unleashed_clk_sync_v2 branch of: https://github.com/avpatel/u-boot.git Changes since v1: - Dropped GEMGXL clock driver - Added new compatible string for SiFive MACB ethernet Anup Patel (6): clk: sifive: Factor-out PLL library as separate module clk: sifive: Sync-up WRPLL library with upstream Linux clk: sifive: Sync-up DT bindings header with upstream Linux clk: sifive: Sync-up main driver with upstream Linux clk: sifive: Drop GEMGXL clock driver net: macb: Add compatible string for MACB on SiFive Unleashed board/sifive/fu540/Kconfig | 1 - drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/analogbits/Kconfig | 4 + drivers/clk/analogbits/Makefile | 3 + .../{sifive => analogbits}/wrpll-cln28hpc.c | 168 ++++++++---------- drivers/clk/sifive/Kconfig | 10 -- drivers/clk/sifive/Makefile | 4 - drivers/clk/sifive/fu540-prci.c | 123 +++++++------ drivers/clk/sifive/gemgxl-mgmt.c | 60 ------- drivers/net/macb.c | 1 + include/dt-bindings/clk/sifive-fu540-prci.h | 29 --- include/dt-bindings/clock/sifive-fu540-prci.h | 18 ++ .../linux/clk}/analogbits-wrpll-cln28hpc.h | 70 +++----- 14 files changed, 196 insertions(+), 297 deletions(-) create mode 100644 drivers/clk/analogbits/Kconfig create mode 100644 drivers/clk/analogbits/Makefile rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (69%) delete mode 100644 drivers/clk/sifive/gemgxl-mgmt.c delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (52%) -- 2.17.1

3 9