June 2019 - U-Boot

Re: [U-Boot] [PATCH v5 6/8] net: macb: Extend MACB driver for SiFive Unleashed board
by Ramon Fried 24 Jun '19

24 Jun '19

On Thu, Jun 20, 2019 at 9:49 AM Anup Patel <Anup.Patel(a)wdc.com> wrote: > The SiFive MACB ethernet has a custom TX_CLK_SEL register to select > different TX clock for 1000mbps vs 10/100mbps. > > This patch adds SiFive MACB compatible string and extends the MACB > ethernet driver to change TX clock using TX_CLK_SEL register for > SiFive MACB. > > Signed-off-by: Anup Patel <anup.patel(a)wdc.com> > --- > drivers/net/macb.c | 53 +++++++++++++++++++++++++++++++++++++++------- > 1 file changed, 45 insertions(+), 8 deletions(-) > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c > index c072f99d8f..6a29ee3064 100644 > --- a/drivers/net/macb.c > +++ b/drivers/net/macb.c > @@ -83,6 +83,9 @@ struct macb_dma_desc { > > struct macb_device { > void *regs; > + void *regs_sifive_gemgxl; This needs needs to be part of the specific config structure. > + > + bool skip_dma_config; Why do you ever need to skip_dma_config ? > unsigned int dma_burst_length; > > unsigned int rx_tail; > @@ -122,7 +125,9 @@ struct macb_device { > }; > > struct macb_config { > + bool skip_dma_config; > unsigned int dma_burst_length; > + bool has_sifive_gemgxl; > }; > > #ifndef CONFIG_DM_ETH > @@ -486,18 +491,11 @@ static int macb_phy_find(struct macb_device *macb, const char *name) > int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed) > { > #ifdef CONFIG_CLK > + struct macb_device *macb = dev_get_priv(dev); > struct clk tx_clk; > ulong rate; > int ret; > > - /* > - * "tx_clk" is an optional clock source for MACB. > - * Ignore if it does not exist in DT. > - */ > - ret = clk_get_by_name(dev, "tx_clk", &tx_clk); > - if (ret) > - return 0; > - > switch (speed) { > case _10BASET: > rate = 2500000; /* 2.5 MHz */ > @@ -513,6 +511,26 @@ int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed) > return 0; > } > > + if (macb->regs_sifive_gemgxl) { > + /* > + * SiFive GEMGXL TX clock operation mode: > + * > + * 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic > + * and output clock on GMII output signal GTX_CLK > + * 1 = MII mode. Use MII input signal TX_CLK in TX logic > + */ > + writel(rate != 125000000, macb->regs_sifive_gemgxl); > + return 0; > + } move to dedicated clock init. > + > + /* > + * "tx_clk" is an optional clock source for MACB. > + * Ignore if it does not exist in DT. > + */ > + ret = clk_get_by_name(dev, "tx_clk", &tx_clk); > + if (ret) > + return 0; > + > if (tx_clk.dev) { > ret = clk_set_rate(&tx_clk, rate); > if (ret) > @@ -701,6 +719,9 @@ static void gmac_configure_dma(struct macb_device *macb) > u32 buffer_size; > u32 dmacfg; > > + if (macb->skip_dma_config) > + return; > + Same as before, why do you skip it ? > buffer_size = 128 / RX_BUFFER_MULTIPLE; > dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L); > dmacfg |= GEM_BF(RXBS, buffer_size); > @@ -1178,6 +1199,7 @@ static int macb_eth_probe(struct udevice *dev) > struct macb_device *macb = dev_get_priv(dev); > const char *phy_mode; > __maybe_unused int ret; > + fdt_addr_t addr; > > phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", > NULL); > @@ -1194,6 +1216,7 @@ static int macb_eth_probe(struct udevice *dev) > if (!macb_config) > macb_config = &default_gem_config; > > + macb->skip_dma_config = macb_config->skip_dma_config; > macb->dma_burst_length = macb_config->dma_burst_length; > #ifdef CONFIG_CLK > ret = macb_enable_clk(dev); > @@ -1201,6 +1224,13 @@ static int macb_eth_probe(struct udevice *dev) > return ret; > #endif > > + if (macb_config->has_sifive_gemgxl) { > + addr = dev_read_addr_index(dev, 1); > + if (addr == FDT_ADDR_T_NONE) > + return -ENODEV; > + macb->regs_sifive_gemgxl = (void __iomem *)addr; > + } This should be all done in a a specific sifive init function. You can define init function and clock init function CB functions in config (Like in Linux): " int (*clk_init)(struct platform_device *pdev, struct clk **pclk, struct clk **hclk, struct clk **tx_clk, struct clk **rx_clk); int (*init)(struct platform_device *pdev); " and add your specific SOC initialization there. This function should be generic as possible. > + > _macb_eth_initialize(macb); > > #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) > @@ -1259,6 +1289,12 @@ static const struct macb_config sama5d4_config = { > .dma_burst_length = 4, > }; > > +static const struct macb_config sifive_config = { > + .skip_dma_config = true, > + .dma_burst_length = 0, Don't mention it if it's zero, and by the way, I assume it should be not zero. You're wasting memory cycles, try to find the correct value. (I think 4 is the default in macb) > + .has_sifive_gemgxl = true, can be dropped if callback functions are declared. > +}; > + > static const struct udevice_id macb_eth_ids[] = { > { .compatible = "cdns,macb" }, > { .compatible = "cdns,at91sam9260-macb" }, > @@ -1266,6 +1302,7 @@ static const struct udevice_id macb_eth_ids[] = { > { .compatible = "atmel,sama5d3-gem" }, > { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config }, > { .compatible = "cdns,zynq-gem" }, > + { .compatible = "sifive,fu540-macb", .data = (ulong)&sifive_config }, > { } > }; > > -- > 2.17.1 > Thanks, Ramon.

3 3

[U-Boot] [PATCH v6 0/8] Update SiFive Unleashed Drivers
by Anup Patel 24 Jun '19

24 Jun '19

This series update SiFive Unleashed clock driver and Cadence MACB driver so that: 1. It is in sync with upstream Linux driver 2. It uses latest DT bindings as-per upstream Linux driver With this series, we can now use latest DT bindings with U-Boot. I have tested SiFive Serial driver and Cadence MACB ethernet driver with this changes and both work fine. The legacy FSBL will still pass DTB with older DT bindings which will break the updated SiFive Unleashed clock driver. To tackle this, we have embedded DTB in OpenSBI FW_PAYLOAD firmware for SiFive Unleashed so that OpenSBI will override and pass updated DTB to U-Boot. The updated DTB passed by OpenSBI is in fact the DTB build by upstream Linux so we can straight away pass this DTB to Linux as well. This series can be found in riscv_unleashed_clk_sync_v6 branch at: https://github.com/avpatel/u-boot.git To try this series use latest OpenSBI at: https://github.com/riscv/opensbi.git And Linux-5.2-rc1 from v5.2-rc1_unleashed branch at: https://github.com/avpatel/linux.git Changes since v5: - Addressed Ramon's comments in PATCH6 - Addressed Bin's comments in PATCH7 Changes since v4: - Rebased patches upon Ramon's MACB changes (Refer, https://patchwork.ozlabs.org/patch/1114025/) - Added PATCH7 to setup ethaddr based on board serial number read from OTP - Added PATCH8 to update documentation Changes since v3: - Extend MACB ethernet driver for SiFive Unleashed board (just like Linux) Changes since v2: - Dropped PATCH6 which adds new compatible string to MACB driver because more changes are required in MACB driver for different ethernet speeds Changes since v1: - Dropped GEMGXL clock driver - Added new compatible string for SiFive MACB ethernet Anup Patel (8): clk: sifive: Factor-out PLL library as separate module clk: sifive: Sync-up WRPLL library with upstream Linux clk: sifive: Sync-up DT bindings header with upstream Linux clk: sifive: Sync-up main driver with upstream Linux clk: sifive: Drop GEMGXL clock driver net: macb: Extend MACB driver for SiFive Unleashed board riscv: sifive: fu540: Setup ethaddr env variable using OTP doc: sifive-fu540: Update README for steps to create FW_PAYLOAD board/sifive/fu540/Kconfig | 1 - board/sifive/fu540/fu540.c | 122 ++++++ configs/sifive_fu540_defconfig | 1 + doc/README.sifive-fu540 | 356 ++++++++---------- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/analogbits/Kconfig | 4 + drivers/clk/analogbits/Makefile | 3 + .../{sifive => analogbits}/wrpll-cln28hpc.c | 168 ++++----- drivers/clk/sifive/Kconfig | 10 - drivers/clk/sifive/Makefile | 4 - drivers/clk/sifive/fu540-prci.c | 123 +++--- drivers/clk/sifive/gemgxl-mgmt.c | 60 --- drivers/net/macb.c | 86 ++++- include/dt-bindings/clk/sifive-fu540-prci.h | 29 -- include/dt-bindings/clock/sifive-fu540-prci.h | 18 + .../linux/clk}/analogbits-wrpll-cln28hpc.h | 70 ++-- 17 files changed, 551 insertions(+), 506 deletions(-) create mode 100644 drivers/clk/analogbits/Kconfig create mode 100644 drivers/clk/analogbits/Makefile rename drivers/clk/{sifive => analogbits}/wrpll-cln28hpc.c (69%) delete mode 100644 drivers/clk/sifive/gemgxl-mgmt.c delete mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h create mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h rename {drivers/clk/sifive => include/linux/clk}/analogbits-wrpll-cln28hpc.h (52%) -- 2.17.1

1 8

[U-Boot] [PATCH 2/2] board: stmark2: changes for mmc boot
by Angelo Dureghello 23 Jun '19

23 Jun '19

Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- board/sysam/stmark2/stmark2.c | 15 +++++++++++++++ configs/stmark2_defconfig | 9 +++++++++ include/configs/stmark2.h | 27 +++++++++++++++------------ 3 files changed, 39 insertions(+), 12 deletions(-) diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c index 790199a640..f5f62e09a9 100644 --- a/board/sysam/stmark2/stmark2.c +++ b/board/sysam/stmark2/stmark2.c @@ -9,8 +9,10 @@ #include <spi.h> #include <asm/io.h> #include <asm/immap.h> +#ifdef CONFIG_FSL_ESDHC #include <mmc.h> #include <fsl_esdhc.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -44,3 +46,16 @@ int testdram(void) { return 0; } + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg = { + .esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR, +}; + +int board_mmc_init(bd_t *bd) +{ + esdhc_cfg.sdhc_clk = gd->arch.sdhc_clk; + + return fsl_esdhc_initialize(bd, &esdhc_cfg); +} +#endif diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index b039ebb9ea..e36b597b01 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -12,11 +12,16 @@ CONFIG_SYS_PROMPT="stmark2 $ " # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +CONFIG_DOS_PARTITION=y CONFIG_MTDIDS_DEFAULT="nor0=spi-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)" CONFIG_DEFAULT_DEVICE_TREE="stmark2" @@ -25,6 +30,8 @@ CONFIG_USE_ENV_SPI_CS=y CONFIG_ENV_SPI_CS=1 # CONFIG_NET is not set CONFIG_MTD_DEVICE=y +CONFIG_MMC=y +CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=50000000 @@ -34,3 +41,5 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CF_SPI=y CONFIG_REGEX=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 rw rootfstype=ramfs rdinit=/sbin/init devtmpfs.mount=1" diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 35966580a9..f02c10c59c 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -19,31 +19,26 @@ #define CONFIG_TIMESTAMP -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 root=/dev/ram0 rw " \ - "rootfstype=ramfs " \ - "rdinit=/bin/init " \ - "devtmpfs.mount=1" - #define CONFIG_BOOTCOMMAND \ - "sf probe 0:1 50000000; " \ - "sf read ${loadaddr} 0x100000 ${kern_size}; " \ - "bootm ${loadaddr}" + "run boot_sd; bootm ${loadaddr} ${loadaddr_ramfs}" #define CONFIG_EXTRA_ENV_SETTINGS \ + "boot_sd=load mmc 0:1 ${loadaddr} uImage; " \ + "load mmc 0:1 ${loadaddr_ramfs} uRamfs\0" \ "kern_size=0x700000\0" \ "loadaddr=0x40001000\0" \ + "loadaddr_ramfs=0x41001000\0" \ "-(rootfs)\0" \ - "update_uboot=loady ${loadaddr}; " \ + "update_sf_uboot=loady ${loadaddr}; " \ "sf probe 0:1 50000000; " \ "sf erase 0 0x80000; " \ "sf write ${loadaddr} 0 ${filesize}\0" \ - "update_kernel=loady ${loadaddr}; " \ + "update_sf_kernel=loady ${loadaddr}; " \ "setenv kern_size ${filesize}; saveenv; " \ "sf probe 0:1 50000000; " \ "sf erase 0x100000 0x700000; " \ "sf write ${loadaddr} 0x100000 ${filesize}\0" \ - "update_rootfs=loady ${loadaddr}; " \ + "update_sf_rootfs=loady ${loadaddr}; " \ "sf probe 0:1 50000000; " \ "sf erase 0x00800000 0x100000; " \ "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ @@ -62,6 +57,13 @@ #define CONFIG_MCFTMR #undef CONFIG_MCFPIT +/* MMC Config*/ +#ifdef CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0xfc0cc000 +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + /* DSPI and Serial Flash */ #define CONFIG_CF_DSPI #define CONFIG_SERIAL_FLASH @@ -72,6 +74,7 @@ #define CONFIG_EXTRA_CLOCK #define CONFIG_PRAM 2048 /* 2048 KB */ +#define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -- 2.20.1

1 0

[U-Boot] [PATCH 1/2] board: amcore: fix u-boot mtd partition
by Angelo Dureghello 23 Jun '19

23 Jun '19

Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- include/configs/amcore.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 4daa0bafe8..6349cf90bc 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -15,15 +15,15 @@ #define CONFIG_SYS_UART_PORT 0 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTCOMMAND "bootm ffc20000" +#define CONFIG_BOOTCOMMAND "bootm ffc30000" #define CONFIG_EXTRA_ENV_SETTINGS \ "upgrade_uboot=loady; " \ - "protect off 0xffc00000 0xffc1ffff; " \ - "erase 0xffc00000 0xffc1ffff; " \ + "protect off 0xffc00000 0xffc2ffff; " \ + "erase 0xffc00000 0xffc2ffff; " \ "cp.b 0x20000 0xffc00000 ${filesize}\0" \ "upgrade_kernel=loady; " \ - "erase 0xffc20000 0xffefffff; " \ - "cp.b 0x20000 0xffc20000 ${filesize}\0" \ + "erase 0xffc30000 0xffefffff; " \ + "cp.b 0x20000 0xffc30000 ${filesize}\0" \ "upgrade_jffs2=loady; " \ "erase 0xfff00000 0xffffffff; " \ "cp.b 0x20000 0xfff00000 ${filesize}\0" @@ -62,7 +62,7 @@ #define CONFIG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) +#define CONFIG_SYS_MONITOR_LEN ((192 - 4) * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) -- 2.20.1

1 0

[U-Boot] ping on http://patchwork.ozlabs.org/patch/1094192/
by Hannes Schmelzer 23 Jun '19

23 Jun '19

Hi Tom, how about merging this? cheers, Hannes -- mfG Schmelzer Hannes

2 1

[U-Boot] [BUG] incorrect crash dump output for thumbs mode
by Heinrich Schuchardt 23 Jun '19

23 Jun '19

>> Hello Marek, >> >> please, have a look at arch/arm/lib/interrupts.c. >> >> If the processor is in thumbs mode when crashing the output is formatted >> in a different way than when not in thumbs mode, cf. dump_instr(). Is >> there something wrong with the thumbs mode detection? > > Well, try maybe objdump ? > > What is more plausible, that the above completely nonsensical > disassembly actually works and the CPU triggers undefined instruction -- > or that the CPU is actually in thumb mode (hint: imx6 u-boot builds are > built in thumb2) and there's a bug in efi_device_path.c ? I think the later. > > I think maybe you should slow down and consider this option. > On a Wandboard which is also imx I had a look at the output of exceptions: => exception unaligned data abort pc : [<8f7a2b1a>] lr : [<8f7ab1b7>] reloc pc : [<1780cb1a>] lr : [<178151b7>] sp : 8ed8c3f8 ip : 8f7a2b15 fp : 00000002 r10: 8f7f81f0 r9 : 8ed95ea8 r8 : 8ed99488 r7 : 8f7ab109 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6358 r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6358 Flags: nzCv IRQs off FIQs off Mode SVC_32 Code: 8f7e1907 8f7e191f 8f7e193d f105466d (e9d50501) Resetting CPU ... cat u-boot.map .text.do_unaligned 0x1780cb14 0xe cmd/built-in.o objdump -S -D cmd/arm/exception.o 00000000 <do_unaligned>: /* * The LDRD instruction requires the data source to be four byte aligned * even if strict alignment fault checking is disabled in the system * control register. */ asm volatile ( 0: 466d mov r5, sp 2: f105 0501 add.w r5, r5, #1 6: e9d5 6700 ldrd r6, r7, [r5] "MOV r5, sp\n" "ADD r5, #1\n" "LDRD r6, r7, [r5]\n"); return CMD_RET_FAILURE; } a: 2001 movs r0, #1 c: 4770 bx lr So there is a bug in arch/arm/lib/interrupts.c such that it does not detect thumb mode and outputs the code arround PC incorrectly. Macro thumb_mode(regs) returns 0 though the thumbs flag is set: CPSR: 200001f3 THUMBS_FLAG: 00000020 The reason is that in arch/arm/include/asm/proc-armv/ptrace.h we are checking non-existent CONFIG_ARM_THUMB. We should check CONFIG_IS_ENABLED(SYS_THUMB_BUILD). I will send a patch to correct this. With the patch applied the output is correct: => exception unaligned data abort pc : [<8f7a2b52>] lr : [<8f7ab1ef>] reloc pc : [<1780cb52>] lr : [<178151ef>] sp : 8ed8c3f8 ip : 8f7a2b4d fp : 00000002 r10: 8f7f8228 r9 : 8ed95ea8 r8 : 8ed99488 r7 : 8f7ab141 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6390 r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6390 Flags: nzCv IRQs off FIQs off Mode SVC_32 (T) Code: 8f7e 466d f105 0501 (e9d5) 6700 Resetting CPU ... Thanks for rubbing my nose into it. Regards Heinrich

2 1

[U-Boot] [PATCH 1/1] ARM: correct detection of thumbs mode
by Heinrich Schuchardt 23 Jun '19

23 Jun '19

When a crash occurs in thumbs mode the crash dump is incorrect. This is due to the usage of a non-existing configuration variable CONFIG_ARM_THUMB in the definition of macro thumb_mode(regs). Use CONFIG_IS_ENABLED(SYS_THUMB_BUILD) to detect that the code has been compiled for thumbs mode. With the patch crash dumps indicate thumbs mode correctly. On a system with thumbs mode: => exception unaligned data abort pc : [<8f7a2b52>] lr : [<8f7ab1ef>] reloc pc : [<1780cb52>] lr : [<178151ef>] sp : 8ed8c3f8 ip : 8f7a2b4d fp : 00000002 r10: 8f7f8228 r9 : 8ed95ea8 r8 : 8ed99488 r7 : 8f7ab141 r6 : 00000000 r5 : 8ed8c3f9 r4 : 8f7f6390 r3 : 8ed9948c r2 : 00000001 r1 : 00000000 r0 : 8f7f6390 Flags: nzCv IRQs off FIQs off Mode SVC_32 (T) Code: 8f7e 466d f105 0501 (e9d5) 6700 The Flags line has '(T)' and in the Code line the output is in u16 groups. On a system without thumbs mode: => exception breakpoint prefetch abort pc : [<7ff5a5c8>] lr : [<7ff675ec>] reloc pc : [<0000e5c8>] lr : [<0001b5ec>] sp : 7ee0ad80 ip : 7ff5a5cc fp : 7ff674cc r10: 00000002 r9 : 7ef0bed8 r8 : 7ffd6214 r7 : 7ef0e080 r6 : 00000000 r5 : 7ffd4090 r4 : 00000000 r3 : 7ef0e084 r2 : 00000001 r1 : 00000000 r0 : 7ffd4090 Flags: nzCv IRQs off FIQs off Mode SVC_32 Code: e1a0500d e2855001 e1c560d0 e3a00001 (e12fff1e) The Flags line does not show '(T)' and in the Code line the output is in u32 groups. Reported-by: Marek Vasut <marex(a)denx.de> Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- arch/arm/include/asm/proc-armv/ptrace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 183b00a087..e37ad8fd1f 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -86,7 +86,7 @@ struct pt_regs { #define user_mode(regs) \ (((regs)->ARM_cpsr & 0xf) == 0) -#ifdef CONFIG_ARM_THUMB +#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) #define thumb_mode(regs) \ (((regs)->ARM_cpsr & T_BIT)) #else -- 2.20.1

2 1

[U-Boot] [PATCH 0/7] sunxi: Add H6 DDR3 DRAM support
by Andre Przywara 23 Jun '19

23 Jun '19

So far the SPL DRAM driver for the Allwinner H6 SoC only supports LPDDR3 DRAM chips, which are used on most single board computers with this SoC. There are some TV boxes with the H6 out now, but most of them are using DDR3 DRAM instead of LPDDR3. This series extends the existing H6 DRAM driver to cover DDR3 DRAMs as well. The information used in these patches is from: - register dumps after Allwinner's boot0 (libdram) has initialised the DRAM - some disassembly of the libdram library - timing parameters as found in the boot0 binary - comparison with Xilinx ZynqMP DRAM controller documentation The box I played with (Eachlink H6 Mini) has 3GB of DDR3-1600 chips and runs at 840 MHz, however I couldn't get it to work with these parameters. Instead Jernej suggested to use a lower clock and adjust some timing parameters, which made it work for me as well. Many thanks to Jernej Skrabec for his help, also to others who helped with testing and experiments. The first two patches contain some fixes for the existing driver. Patch 3 moves the existing LPDDR3 timing parameters into a separate file, patch 5 introduces the respective DDR3 timings, patch 6 adds some generic delay lines values. Patch 4 enhances the DRAM controller driver to program DDR3 specific registers as well and use different settings on other registers. The final patch introduces support for the Eachlink H6 Mini TV box, with the usual device tree and defconfig file. Please have a look and comment! Cheers, Andre. Andre Przywara (6): sunxi: H6: DRAM: avoid memcpy() on MMIO registers sunxi: H6: DRAM: follow recommended PHY init algorithm sunxi: H6: move LPDDR3 timing definition into separate file sunxi: H6: Add DDR3 support to DRAM controller driver sunxi: H6: Add DDR3-1333 timings sunxi: H6: Add basic Eachlink H6 Mini support Jernej Skrabec (1): sunxi: H6: Add DDR3 DRAM delay values arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts | 116 +++++++++++ arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h | 35 ++++ arch/arm/mach-sunxi/Kconfig | 18 +- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 240 +++++++--------------- arch/arm/mach-sunxi/dram_timings/Makefile | 2 + arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c | 144 +++++++++++++ arch/arm/mach-sunxi/dram_timings/h6_lpddr3_1333.c | 132 ++++++++++++ configs/eachlink_h6_mini_defconfig | 17 ++ configs/orangepi_one_plus_defconfig | 1 + configs/pine_h64_defconfig | 1 + 12 files changed, 537 insertions(+), 171 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6-eachlink-h6-mini.dts create mode 100644 arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c create mode 100644 arch/arm/mach-sunxi/dram_timings/h6_lpddr3_1333.c create mode 100644 configs/eachlink_h6_mini_defconfig -- 2.14.5

4 12

[U-Boot] [PATCH v2 0/3] Add SDHCI card detection support
by Michal Simek 22 Jun '19

22 Jun '19

Hi, This patch series adds card detection support in sdhci framework & added functionality to read card detect dt properties. Thanks, Michal Changes in v2: - Moved reading CD devicetree properties functionality from sdhci.c to mmc-uclass.c & moved mmc capability macros to mmc.h from sdhci.h. - Created a new patch for reading "cd-gpio" property from DT. - Used CARD_PRESENT instead of SDHCI_CARD_DETECT_PIN_LEVEL for reading sd card presence detection. T Karthik Reddy (3): mmc: Read sd card detect properties from DT mmc: sdhci: Read cd-gpio from devicetree mmc: sdhci: Implement SDHCI card detect drivers/mmc/mmc-uclass.c | 9 +++++++++ drivers/mmc/sdhci.c | 38 ++++++++++++++++++++++++++++++++++++++ include/mmc.h | 4 ++++ 3 files changed, 51 insertions(+) -- 2.17.1

4 9

[U-Boot] [PATCH 1/1] disk: part: avoid undefined reference to `__udivmoddi4'
by Heinrich Schuchardt 22 Jun '19

22 Jun '19

When compiling with FTRACE=1 an error ld.bfd: disk/built-in.o: in function `lba512_muldiv': disk/part.c:114: undefined reference to `__udivmoddi4 occurred. Use '>> 11' instead of '/ 2048' to avoid the division. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- disk/part.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/disk/part.c b/disk/part.c index 98cc54db20..862078f3e7 100644 --- a/disk/part.c +++ b/disk/part.c @@ -103,17 +103,17 @@ typedef lbaint_t lba512_t; #endif /* - * Overflowless variant of (block_count * mul_by / div_by) + * Overflowless variant of (block_count * mul_by / 2**div_by) * when div_by > mul_by */ -static lba512_t lba512_muldiv(lba512_t block_count, lba512_t mul_by, lba512_t div_by) +static lba512_t lba512_muldiv(lba512_t block_count, lba512_t mul_by, int div_by) { lba512_t bc_quot, bc_rem; /* x * m / d == x / d * m + (x % d) * m / d */ - bc_quot = block_count / div_by; - bc_rem = block_count - div_by * bc_quot; - return bc_quot * mul_by + (bc_rem * mul_by) / div_by; + bc_quot = block_count >> div_by; + bc_rem = block_count - (bc_quot << div_by); + return bc_quot * mul_by + ((bc_rem * mul_by) >> div_by); } void dev_print (struct blk_desc *dev_desc) @@ -193,7 +193,7 @@ void dev_print (struct blk_desc *dev_desc) lba512 = (lba * (dev_desc->blksz/512)); /* round to 1 digit */ /* 2048 = (1024 * 1024) / 512 MB */ - mb = lba512_muldiv(lba512, 10, 2048); + mb = lba512_muldiv(lba512, 10, 11); mb_quot = mb / 10; mb_rem = mb - (10 * mb_quot); -- 2.20.1

2 2