May 2019 - U-Boot

[U-Boot] [PATCH 1/3] spl: imx6: Let spl_boot_device return USDHC1 or USDHC2
by Adam Ford 09 Aug '19

09 Aug '19

Currently, when the spl_boot_device checks the boot device, it will only return MMC1 when it's either sd or eMMC regardless of whether or not it's MMC1 or MMC2. This is a problem when booting from MMC2 if MMC isn't being manually configured like in the DM_SPL case with SPL_OF_CONTROL. This patch will check the register and return either MMC1 or MMC2. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 9f1e0f6a72..1f230aca33 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -24,6 +24,7 @@ u32 spl_boot_device(void) { unsigned int bmode = readl(&src_base->sbmr2); u32 reg = imx6_src_get_boot_mode(); + u32 mmc_index = ((reg >> 11) & 0x03); /* * Check for BMODE if serial downloader is enabled @@ -84,11 +85,12 @@ u32 spl_boot_device(void) /* SD/eSD: 8.5.3, Table 8-15 */ case IMX6_BMODE_SD: case IMX6_BMODE_ESD: - return BOOT_DEVICE_MMC1; - /* MMC/eMMC: 8.5.3 */ case IMX6_BMODE_MMC: case IMX6_BMODE_EMMC: - return BOOT_DEVICE_MMC1; + if (mmc_index == 1) + return BOOT_DEVICE_MMC2; + else + return BOOT_DEVICE_MMC1; /* NAND Flash: 8.5.2, Table 8-10 */ case IMX6_BMODE_NAND_MIN ... IMX6_BMODE_NAND_MAX: return BOOT_DEVICE_NAND; -- 2.17.1

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[U-Boot] [PATCH v3 0/5] dm: spi: Convert Freescale ESPI driver to driver
by Chuanhua Han 08 Aug '19

08 Aug '19

In order to convert the Freescale ESPI driver to the driver model, there are 5 related patches in the current patch set: 0001-spl-dm-disable-SPI-DM-flash-for-non-DM-SPL.patch 0002-dm-spi-Convert-Freescale-ESPI-driver-to-driver-model.patch 0003-powerpc-dts-t2080-add-espi-controller-node-support.patch 0004-powerpc-dts-t2080qds-add-espi-slave-nodes-support.patch 0005-configs-enable-espi-device-module-in-T2080QDS.patch The first patch is to solve the problem that spl can't work when spiboot, and this is required for SPI boot. The other four patches are supported by the driver model. This patchset already supports the full dm mode, and fsl_espi driver support both OF_CONTROL and PLATDATA. Chuanhua Han (5): spl: dm: disable SPI DM flash for non-DM SPL dm: spi: Convert Freescale ESPI driver to driver model powerpc: dts: t2080: add espi controller node support powerpc: dts: t2080qds: add espi slave nodes support configs: enable espi device module in T2080QDS arch/powerpc/dts/t2080.dtsi | 10 + arch/powerpc/dts/t2080qds.dts | 33 ++ configs/T2080QDS_NAND_defconfig | 2 + configs/T2080QDS_SDCARD_defconfig | 2 + configs/T2080QDS_SECURE_BOOT_defconfig | 2 + configs/T2080QDS_SPIFLASH_defconfig | 2 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 + configs/T2080QDS_defconfig | 2 + drivers/spi/fsl_espi.c | 454 +++++++++++++++------- include/config_uncmd_spl.h | 1 + 10 files changed, 376 insertions(+), 134 deletions(-) -- 2.17.1

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[U-Boot] [PATCH 0/3] Ethernet support for QEMU sifive_u machine
by Anup Patel 07 Aug '19

07 Aug '19

This patchset enables Cadance MACB ethernet driver for QEMU sifive_u machine. The Cadance MACB ethernet driver works fine for QEMU sifive_u machince in both M-mode and S-mode with some minor fixes. The patches are based upon latest RISC-V U-Boot tree (git://git.denx.de/u-boot-riscv.git) at commit id 9deb8d2fcd13d4a40a4e63c396fe4376af46efac To try on QEMU, please ensure following patches are applied to QEMU sources: https://patchwork.kernel.org/patch/10729579/ https://patchwork.kernel.org/patch/10729581/ Anup Patel (3): riscv: Add asm/dma-mapping.h for DMA mappings net: macb: Fix clk API usage for RISC-V systems riscv: qemu: Imply MACB ethernet for emulation arch/riscv/include/asm/dma-mapping.h | 37 ++++++++++++++++++++++++++++ board/emulation/qemu-riscv/Kconfig | 4 +++ drivers/net/macb.c | 4 ++- 3 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/dma-mapping.h -- 2.17.1

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[U-Boot] [PATCH 2/2] efi_loader: set the dhcp ack received flag
by Patrick Wildt 06 Aug '19

06 Aug '19

The PXE object contains a flag that specifies whether or not a DHCP ACK has been received. This can be used by EFI Applications to find out whether or not it is worth to read the DHCP information from our object. Signed-off-by: Patrick Wildt <patrick(a)blueri.se> --- lib/efi_loader/efi_net.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 8c5d5b492c..0b9c7b9345 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -332,8 +332,10 @@ int efi_net_register(void) netobj->net_mode.max_packet_size = PKTSIZE; netobj->pxe.mode = &netobj->pxe_mode; - if (dhcp_ack) + if (dhcp_ack) { netobj->pxe_mode.dhcp_ack = *dhcp_ack; + netobj->pxe_mode.dhcp_ack_received = 1; + } /* * Create WaitForPacket event. -- 2.14.3 (Apple Git-98)

5 19

[U-Boot] [PATCH 0/10] x86: Add generic VESA video driver
by Simon Glass 01 Aug '19

01 Aug '19

This series introduces a generic VESA video driver and adjusts the generic PCI ROM support to support it. It also fixes up some problems which prevent this from working on PowerPC at present. It is now possible to use VESA graphics: - On PowerPC, using the x86 emulator - On x86, using either the x86 emulator or native code execution As it turns out, on the only platform I have tested (link), the x86 emulator is only slightly slower that native code execution (200ms difference). Still, we may as well leave this feature in there. VGA ROMs are a very old technology but they are still used by modern platforms, including at least link and some Atom designs. Simon Glass (10): bios_emulator: Fix an #ifdef typo in the header file x86: Correct endianness isues in pci_rom x86: Support ROMs on other archs bios_emulator: Don't display error when emulator terminates bios_emulator: Add some VESA interface debugging x86: pci: Don't stop when we get a vendor/device mismatch x86: Add a VESA video driver x86: Drop the x86_fb driver x86: Access the VGA ROM when needed RFC: Test code for glacier PCI video support arch/x86/include/asm/u-boot-x86.h | 2 + drivers/bios_emulator/atibios.c | 161 +++++++++++++++++++++++---- drivers/bios_emulator/include/x86emu/debug.h | 2 +- drivers/bios_emulator/x86emu/ops.c | 2 +- drivers/pci/pci_auto.c | 28 ++++- drivers/pci/pci_rom.c | 40 ++++--- drivers/video/Makefile | 2 +- drivers/video/vesa_fb.c | 64 +++++++++++ drivers/video/x86_fb.c | 38 ------- include/configs/canyonlands.h | 31 ++++++ include/configs/chromebook_link.h | 2 +- include/pci.h | 9 ++ include/pci_rom.h | 1 - include/vbe.h | 9 +- 14 files changed, 312 insertions(+), 79 deletions(-) create mode 100644 drivers/video/vesa_fb.c delete mode 100644 drivers/video/x86_fb.c -- 2.2.0.rc0.207.ga3a616c

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[U-Boot] [PATCH] video, simple_panel: add lg,lb070wv8 display
by Heiko Schocher 30 Jul '19

30 Jul '19

add "lg,lb070wv8" display to compatible node. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- clean travis build, see: https://travis-ci.org/hsdenx/u-boot-test/builds/537359553 drivers/video/simple_panel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index 7a968e740c..c3c0e84732 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -105,6 +105,7 @@ static const struct udevice_id simple_panel_ids[] = { { .compatible = "auo,b133xtn01" }, { .compatible = "auo,b116xw03" }, { .compatible = "auo,b133htn01" }, + { .compatible = "lg,lb070wv8" }, { } }; -- 2.21.0

2 1

[U-Boot] [PATCH PATCH v3 00/12] Add support for applications of overlays in SPL
by Jean-Jacques Hiblot 30 Jul '19

30 Jul '19

The purpose of this series is to provide the SPL with ability to apply overlays for u-boot. this is only a RFC so far, to get a feedback on the approach. Our use-case is the support of the daughter boards of the AM65x EVM. In Linux, each board is supported by a unique overlay. The presence of the boards is detected at runtime, and some useful features (like USB) are implemented on those daughter boards. Instead of providing multiple dtbs and fall in a combinatorial pit, we propose to use DT overlays. Patch #1 "spl: fit: Add support for applying DT overlay" has been posted a few weeks ago by Michal Simek. Patch #2 to #5 amend Michal's patch. Patch #6 to #8 are simple fixes for the Makefile Patch #9 is not required but relates to this series and will be required later by the AM6x platform Patch #10 is used to reduce the complexity of the Makefile by having FIT generator scripts provide their dependencies Patch #12 adds a way to dynamically select the DT overlays. That is were we would use HW detection to select the required overlays. In that case, the board-level code tells what overlay it needs (it gives the name of the node). On arm, if overlay are supported, this series increases the size of the SPL by 3.2 kB. Travis build : https://travis-ci.org/jjhiblot/u-boot/builds/535686392 For a strange reason, buildman on travis show errors for sun8i ans sun50i, but pass when I run it locally. Changes in v3: - Add a new config option: SPL_LOAD_FIT_APPLY_OVERLAY. By default, it is not selected. - removed the RFC prefix. This work will be needed soon by TI's AM65x platform. and can probably benefit other modular platforms - removed the last patch that provided an example of how to use this with on a DRA76. - removed the patch that made u-boot.img a symlink to u-boot.itb because it breaks the build of many platforms (because files required to build the ITB are missing) - removed the patch to reduce the footprint of the am335x SPL. (already merged) - Made the boot flow more permissive (don't fail immediately if an overlay is not present) and more verbose when an error occures - handle the dependencies of the FIT generation in a more generic way - use a dedicated kconfig option to enable the application of the overlays by the SPL. Changes in v2: - reworked board_fit_get_additionnal_images() and how it used in spl_fit.c - removed dtbo generation from dtso files and use .dts extension for the overlays - add dynamic allocation usage in a separate patch - defconfig change for the am335x_evm Jean-Jacques Hiblot (11): spl: fit: Make room in the FDT before applying overlays spl: fit: allocate a temporary buffer to load the overlays spl: fit: Do not fail immediately if an overlay is not available spl: fit: be more verbose when an error occurs when applying the overlays Makefile.lib: include /__symbols__ in dtb if SPL_LOAD_FIT_APPLY_OVERLAY is enabled Makefile: Fix tests for CONFIG_SPL_LOAD_FIT and CONFIG_SPL_FIT_GENERATOR Makefile: Fix u-boot.itb generation when building outside the source tree Makefile: Pass the board name to the FIT generator scripts Makefile: Query the SPL Fit Generator for its dependencies spl: fit: constify the output parameter of spl_fit_get_image_name() spl: fit: Allow the board to tell if more images must be loaded from FIT Michal Simek (1): spl: fit: Add support for applying DT overlay Kconfig | 10 +++ Makefile | 23 +++-- arch/arm/mach-imx/mkimage_fit_atf.sh | 10 ++- arch/arm/mach-rockchip/make_fit_atf.py | 13 ++- board/sunxi/mksunxi_fit_atf.sh | 7 ++ .../lion_rk3368/fit_spl_atf.its | 6 +- .../puma_rk3399/fit_spl_atf.its | 8 +- common/spl/spl_fit.c | 90 +++++++++++++++++-- include/spl.h | 16 ++++ scripts/Makefile.lib | 4 + 10 files changed, 156 insertions(+), 31 deletions(-) -- 2.17.1

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[U-Boot] [PATCH 0/4] Veyron Speedy / ASUS C201 fixes
by Urja Rannikko 30 Jul '19

30 Jul '19

Hi, Just saying: I'm not familiar with this stuff so i might've misunderstood something in my commit messages, but anyways i managed to make it boot. There's more stuff than just these, but i decided I'd keep it short... If you want to know my full setup, you can check out my gh repo for now: https://github.com/urjaman/u-boot/commits/c201-stuff Notably I did include http://patchwork.ozlabs.org/patch/1040541/ in my tree when testing (rk3288 pinctrl patch that was linked to on the previous thread i found about the veyron speedy being broken). The one thing that I havent yet fixed is that the USB host port on the otg-capable controller (near screen) doesn't work - one guess i have is that the dwc2 host driver doesn't force it into host mode... (It doesn't even read dr_mode ...) Urja Rannikko (4): pinctrl: exit pinconfig_post_bind if there are no subnodes rk3288-board: remove pinctrl call for debug uart rk3288-board: cosmetic: document selecting RK PWM dw_mmc: turn on the IO supply arch/arm/mach-rockchip/rk3288-board.c | 13 +------------ drivers/mmc/dw_mmc.c | 15 +++++++++++++++ drivers/pinctrl/pinctrl-uclass.c | 3 +++ 3 files changed, 19 insertions(+), 12 deletions(-) -- 2.21.0

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[U-Boot] [PATCH] rockchip: rk3399: Add Khadas Edge board support
by xieqinick＠gmail.com 27 Jul '19

27 Jul '19

From: Nick <nick(a)khadas.com> Khadas Edge is a board from Khadas, you can find the detail about it here: https://www.khadas.com/edge This patch add basic node for the board and make it able to bring up. Specification - Rockchip RK3399 - Dual-Channel 2GB/4GB LPDDR4 - SD card slot - Onboard 16GB/32GB/128GB eMMC - RTL8211FD 1Gbps - AP6356S/AP6398S WiFI/BT - HDMI Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - Full 4 Lane M.2 Socket - 16MB SPI Flash - IR - Programmable MCU Signed-off-by: Nick <nick(a)khadas.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-kedge-u-boot.dtsi | 10 + arch/arm/dts/rk3399-kedge.dts | 611 ++++++++++++++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 7 + configs/khadas-edge-rk3399_defconfig | 63 ++++ 5 files changed, 692 insertions(+) create mode 100644 arch/arm/dts/rk3399-kedge-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-kedge.dts create mode 100644 configs/khadas-edge-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 31ef2b6..d9adecf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -113,6 +113,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ rk3399-rock960.dtb \ + rk3399-kedge.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3399-kedge-u-boot.dtsi b/arch/arm/dts/rk3399-kedge-u-boot.dtsi new file mode 100644 index 0000000..bf0d54c --- /dev/null +++ b/arch/arm/dts/rk3399-kedge-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Nick <nick(a)khadas.com> + */ + +#include "rk3399-u-boot.dtsi" + +&sdmmc { + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; +}; diff --git a/arch/arm/dts/rk3399-kedge.dts b/arch/arm/dts/rk3399-kedge.dts new file mode 100644 index 0000000..e07e699 --- /dev/null +++ b/arch/arm/dts/rk3399-kedge.dts @@ -0,0 +1,611 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RK3399-based Khadas boards device tree source + * + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com/edge) + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Khadas Edge"; + compatible = "khadas,edge", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; +// vin-supply = <&vdd_5v>; + }; + + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_s3"; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_gpio>; + + status { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu_b"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "rtc_clko_wifi"; + #clock-cells = <1>; + interrupt-parent = <&gpio1>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_center"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_cpu_l"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_apio2: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_apio2"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_vldo2: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_vldo2"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmupll"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_vldo5: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_vldo5"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_apio2>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index f55c92f..bcb058c 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -24,3 +24,10 @@ S: Maintained F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-u-boot.dtsi F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi + +KHADAS-EDGE +M: Nick <nick(a)khadas.com> +S: Maintained +F: configs/khadas-edge-rk3399_defconfig +F: arch/arm/dts/rk3399-kedge.dts +F: arch/arm/dts/rk3399-kedge-u-boot.dtsi diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig new file mode 100644 index 0000000..a9def59 --- /dev/null +++ b/configs/khadas-edge-rk3399_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kedge.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SYS_PROMPT="kedge# " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FS_UUID=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-kedge" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y -- 2.7.4

9 26

[U-Boot] [PATCH] Fix RK3328-evb Floating GPIO0_D6 - pull up - 4ma
by Mister Fix-IT 26 Jul '19

26 Jul '19

Pin GPIO0_30 (D6) is left floating. In the case of the new revision of Pine64 Rock64 Rev3, this pin needs to be pulled up 4ma. Otherwise uboot fails to boot from sd stating "Card did not respond to voltage select". --- arch/arm/dts/rk3328-evb.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index ec594a8452e..c242a8364c5 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -25,6 +25,8 @@ compatible = "regulator-fixed"; regulator-name = "vcc3v3"; gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pwren>; regulator-always-on; regulator-boot-on; };

2 2