May 2019 - U-Boot

[U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6
by Icenowy Zheng 25 Oct '19

25 Oct '19

The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/board.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 40a3f845d0..a646ea6a3c 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -73,6 +73,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; }; +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c6dd7b8e54..bd3b5d8303 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map; static int gpio_init(void) { + __maybe__unused uint val; #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN7I) || \ @@ -139,6 +140,14 @@ static int gpio_init(void) #error Unsupported console port number. Please fix pin mux settings in board.c #endif +#ifdef CONFIG_MACH_SUN50I_H6 + /* Update PIO power bias configuration by copy hardware detected value */ + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); +#endif + return 0; } -- 2.18.1

2 2

[U-Boot] [PATCH] reset: socfpga: release more A10 peripherals out of reset
by tien.fong.chee＠intel.com 09 Oct '19

09 Oct '19

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Current implementation almost release all peripherals out of reset for gen5, but A10 has more peripherals than gen5, hence this patch is required to release the rest of peripherals to support old kernels. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/reset/reset-socfpga.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index cb8312619f..d8b8b25fc3 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -127,6 +127,9 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + writel(0, data->modrst_base + 8); +#endif } return 0; -- 2.13.0

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[U-Boot] [PATCH] cmd: reset: add parameters to specify reboot_mode
by Simon Goldschmidt 09 Oct '19

09 Oct '19

This patch adds parameter support for the 'reset' command to specify the reboot mode (cold vs. warm). Checking these parameters is implemented in the DM implementation. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- cmd/boot.c | 4 ++-- drivers/sysreset/sysreset-uclass.c | 17 ++++++++++++++++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/cmd/boot.c b/cmd/boot.c index 9150fce80b..c3f33a9ca3 100644 --- a/cmd/boot.c +++ b/cmd/boot.c @@ -56,9 +56,9 @@ U_BOOT_CMD( #endif U_BOOT_CMD( - reset, 1, 0, do_reset, + reset, 2, 0, do_reset, "Perform RESET of the CPU", - "" + "[<cold|warm>] - type of reboot" ); #ifdef CONFIG_CMD_POWEROFF diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index ad831c703a..fbda3f44f2 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -111,9 +111,24 @@ void reset_cpu(ulong addr) int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + enum sysreset_t reboot_mode = SYSRESET_COLD; + + if (argc > 1 && argv[1]) { + switch (*argv[1]) { + case 'w': + reboot_mode = SYSRESET_WARM; + printf("warm "); + break; + case 'c': + reboot_mode = SYSRESET_COLD; + printf("cold "); + break; + } + } + printf("resetting ...\n"); - sysreset_walk_halt(SYSRESET_COLD); + sysreset_walk_halt(reboot_mode); return 0; } -- 2.20.1

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[U-Boot] [PATCH 0/1] board: arm: Add support for Broadcom BCM7445D0
by Thomas Fitzsimmons 28 Sep '19

28 Sep '19

Hi, This patch adds support for loading U-Boot on the Broadcom 7445D0 SoC, as a third stage bootloader loaded by Broadcom's BOLT bootloader. While this is only a partial port, it does enable some of U-Boot's flexibility on this SoC, functionality beyond what BOLT provides. Specifically, it brings: - ext4 file system traversal - support for loading FIT images - advanced scripting - support for FIT-provided DTBs instead of relying on the BOLT-provided DTB My team at Cisco is using a customized version of this port in production. The same approach may work on other BCM7xxx boards, with some configuration adjustments and memory layout experimentation. Stefan Roese reviewed (off-list) some early revisions of these changes. This patch is my attempt to rebase on the current U-Boot master branch. I'm submitting it in case there is interest in including this port in upstream U-Boot. Thomas Thomas Fitzsimmons (1): board: arm: Add support for Broadcom BCM7445D0 arch/arm/Kconfig | 12 + arch/arm/cpu/armv7/Makefile | 1 + arch/arm/cpu/armv7/bcm7445d0/Makefile | 11 + arch/arm/cpu/armv7/bcm7445d0/lowlevel_init.S | 24 ++ arch/arm/lib/crt0.S | 2 + arch/arm/mach-bcm7445d0/include/mach/gpio.h | 12 + arch/arm/mach-bcm7445d0/include/mach/hardware.h | 12 + arch/arm/mach-bcm7445d0/include/mach/sdhci.h | 15 + board/broadcom/bcm7445d0/Kconfig | 132 ++++++++ board/broadcom/bcm7445d0/Makefile | 11 + board/broadcom/bcm7445d0/bcm7445d0.c | 147 ++++++++ common/fdt_support.c | 9 +- common/image-fit.c | 2 + configs/bcm7445d0_defconfig | 21 ++ drivers/mmc/Makefile | 1 + drivers/mmc/bcmstb_sdhci.c | 59 ++++ drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/bcmstb_spi.c | 428 ++++++++++++++++++++++++ dts/Kconfig | 6 + include/configs/bcm7445d0.h | 227 +++++++++++++ include/configs/bcmstb.h | 57 ++++ lib/fdtdec.c | 8 + 23 files changed, 1204 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/bcm7445d0/Makefile create mode 100644 arch/arm/cpu/armv7/bcm7445d0/lowlevel_init.S create mode 100644 arch/arm/mach-bcm7445d0/include/mach/gpio.h create mode 100644 arch/arm/mach-bcm7445d0/include/mach/hardware.h create mode 100644 arch/arm/mach-bcm7445d0/include/mach/sdhci.h create mode 100644 board/broadcom/bcm7445d0/Kconfig create mode 100644 board/broadcom/bcm7445d0/Makefile create mode 100644 board/broadcom/bcm7445d0/bcm7445d0.c create mode 100644 configs/bcm7445d0_defconfig create mode 100644 drivers/mmc/bcmstb_sdhci.c create mode 100644 drivers/spi/bcmstb_spi.c create mode 100644 include/configs/bcm7445d0.h create mode 100644 include/configs/bcmstb.h -- 1.8.3.1

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[U-Boot] [PATCH 00/17] Convert some imx6 boards to DM_VIDEO
by Anatolij Gustschin 17 Sep '19

17 Sep '19

This series starts conversion of ipuv3 driver to DM_VIDEO. It has been tested on apalis_imx6 module with LVDS display attached and on wandboard with HDMI display. With applied "[PATCH 17/17] imx6: wandboard: convert to DM_MMC" building wandboard target doesn't work. To fix this please apply patches [1], [2] and enable CONFIG_AHCI and CONFIG_DM_SCSI in wandboard_defconfig. [1] http://patchwork.ozlabs.org/patch/1050141 [2] http://patchwork.ozlabs.org/patch/1050143 Anatolij Gustschin (17): video: ipuv3: add DM_VIDEO support video: move ipuv3 files to subdirectory imx: move CONFIG_VIDEO_IPUV3 to defconfigs imx6: dts: add 'u-boot,dm-pre-reloc' to soc and ipu nodes apalis_imx6: convert to DM_VIDEO imx6: icore: convert to DM_VIDEO imx6: ge_bx50v3: convert to DM_VIDEO colibri_imx6: convert to DM_VIDEO mx6sabresd: convert to DM_VIDEO mx6sabreauto: convert to DM_VIDEO imx6: wandboard: add device tree imx6: wandboard: convert to DM_GPIO and enable pinctrl driver imx6: wandboard: convert to DM_USB imx6: wandboard: convert to DM_VIDEO imx6: wandboard: convert to DM_PMIC imx6: wandboard: convert to DM_I2C imx6: wandboard: convert to DM_MMC arch/arm/dts/imx6dl-wandboard-revb1.dts | 18 + arch/arm/dts/imx6qdl-wandboard-revb1.dtsi | 41 +++ arch/arm/dts/imx6qdl-wandboard.dtsi | 380 ++++++++++++++++++++++ arch/arm/dts/imx6qdl.dtsi | 2 + arch/arm/include/asm/mach-imx/video.h | 1 + arch/arm/mach-imx/video.c | 25 +- board/wandboard/MAINTAINERS | 3 + board/wandboard/spl.c | 92 ++++++ board/wandboard/wandboard.c | 160 +++------ configs/apalis_imx6_defconfig | 4 +- configs/aristainetos2_defconfig | 1 + configs/aristainetos2b_defconfig | 1 + configs/aristainetos_defconfig | 1 + configs/cgtqmx6eval_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/colibri_imx6_defconfig | 3 +- configs/dms-ba16-1g_defconfig | 1 + configs/dms-ba16_defconfig | 1 + configs/ge_bx50v3_defconfig | 2 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/imx6dl_icore_nand_defconfig | 2 +- configs/imx6q_icore_nand_defconfig | 2 +- configs/imx6qdl_icore_mmc_defconfig | 2 +- configs/imx6qdl_icore_nand_defconfig | 2 +- configs/m53menlo_defconfig | 1 + configs/marsboard_defconfig | 1 + configs/mx51evk_defconfig | 1 + configs/mx53cx9020_defconfig | 1 + configs/mx53loco_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6qsabrelite_defconfig | 1 + configs/mx6sabreauto_defconfig | 3 +- configs/mx6sabresd_defconfig | 3 +- configs/nitrogen6dl2g_defconfig | 1 + configs/nitrogen6dl_defconfig | 1 + configs/nitrogen6q2g_defconfig | 1 + configs/nitrogen6q_defconfig | 1 + configs/nitrogen6s1g_defconfig | 1 + configs/nitrogen6s_defconfig | 1 + configs/novena_defconfig | 1 + configs/riotboard_defconfig | 1 + configs/riotboard_spl_defconfig | 1 + configs/tbs2910_defconfig | 1 + configs/wandboard_defconfig | 18 +- drivers/video/Kconfig | 9 +- drivers/video/Makefile | 2 +- drivers/video/imx/Kconfig | 8 + drivers/video/imx/Makefile | 6 + drivers/video/{ => imx}/ipu.h | 0 drivers/video/{ => imx}/ipu_common.c | 0 drivers/video/{ => imx}/ipu_disp.c | 0 drivers/video/{ => imx}/ipu_regs.h | 0 drivers/video/{ => imx}/mxc_ipuv3_fb.c | 89 ++++- drivers/video/{ => imx}/mxcfb.h | 0 include/configs/advantech_dms-ba16.h | 1 - include/configs/apalis_imx6.h | 1 - include/configs/aristainetos-common.h | 1 - include/configs/cgtqmx6eval.h | 1 - include/configs/cm_fx6.h | 1 - include/configs/colibri_imx6.h | 1 - include/configs/embestmx6boards.h | 1 - include/configs/ge_bx50v3.h | 8 - include/configs/gw_ventana.h | 1 - include/configs/m53menlo.h | 1 - include/configs/mx51evk.h | 1 - include/configs/mx53cx9020.h | 1 - include/configs/mx53loco.h | 1 - include/configs/mx53ppd.h | 5 - include/configs/mx6cuboxi.h | 1 - include/configs/mx6sabre_common.h | 1 - include/configs/nitrogen6x.h | 1 - include/configs/novena.h | 1 - include/configs/tbs2910.h | 1 - include/configs/wandboard.h | 18 - 77 files changed, 766 insertions(+), 187 deletions(-) create mode 100644 arch/arm/dts/imx6dl-wandboard-revb1.dts create mode 100644 arch/arm/dts/imx6qdl-wandboard-revb1.dtsi create mode 100644 arch/arm/dts/imx6qdl-wandboard.dtsi create mode 100644 drivers/video/imx/Kconfig create mode 100644 drivers/video/imx/Makefile rename drivers/video/{ => imx}/ipu.h (100%) rename drivers/video/{ => imx}/ipu_common.c (100%) rename drivers/video/{ => imx}/ipu_disp.c (100%) rename drivers/video/{ => imx}/ipu_regs.h (100%) rename drivers/video/{ => imx}/mxc_ipuv3_fb.c (88%) rename drivers/video/{ => imx}/mxcfb.h (100%) -- 2.17.1

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[U-Boot] [usb dwc3] xHCI driver -- a hint needed.
by Yuri Frolov 11 Sep '19

11 Sep '19

Hi, I've been trying to bring up a dwc3 usb controller included in 32-bit MIPS chip. Usb is the one port usb2.0 host module, compliant with xHCI Revision 1.0, UTMI+ Low Pin interface (ULPI) Revision 1.1 and AMBA AXI Protocol specification. g_snpsid register reports 0x5533290a revision. It's verified, that linux kernel support is ok, usb is fully functional. axi { <...> usb@1F04D050 { compatible = "be,baikal-dwc3"; reg = <0x1f04d050 0x4>; interrupts = <0x0 0x45 0x4>; #address-cells = <0x1>; #size-cells = <0x1>; clocks = <0xf 0x0>; clock-names = "usb"; ranges; status = "okay"; dwc3@1F100000 { compatible = "snps,dwc3", "synopsys,dwc3", "generic-xhci"; reg = <0x1f100000 0x10000>; interrupts = <0x0 0x44 0x4>; dr_mode = "host"; tx-fifo-resize; maximum-speed = "high-speed"; }; }; }; whereas in u-boot 'usb start' fails on hub initialization (as I can see): Any ideas why this could happen?.. Any direction where to look at? Any suggestions will be greatly appreciated. # usb start (Re)start USB... USB0: dwc3_reg->g_snpsid: 0x5533290a Register 1000140 NbrPorts 1 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... New Device 0 set address 1 usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x12 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x9 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x1F get_conf_no 0 Result 25, wLength 31 if 0, ep 0 ##EP epmaxpacketin[1] = 8 set configuration 1 usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0 new device strings: Mfr=1, Product=2, SerialNumber=0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 0xFF USB device number 1 default language ID 0x409 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 length 0xFF usb_control_msg: request: 0x6, requesttype: 0x80, value 0x302 index 0x409 length 0xFF Manufacturer U-Boot Product XHCI Host Controller SerialNumber USB hub found usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2A00 index 0x0 length 0x4 usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2A00 index 0x0 length 0xC 1 ports detected ganged power switching standalone hub individual port over-current protection TT requires at most 8 FS bit times (666 ns) power on to power good time: 20ms hub controller current requirement: 0mA port 1 is removable usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 0x4 get_hub_status returned status 1, change 801 local power source is lost (inactive) no over-current condition exists enabling power on all ports usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 0x0 port 1 returns 0 devnum=1 poweron: query_delay=100 connect_timeout=1100 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 Port 1 Status 101 Change 1 devnum=1 port=1: USB dev found usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 portstatus 101, change 1, 12 Mb/s usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x1 length 0x0 usb_hub_port_reset: resetting port 1... usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 portstatus 111, change 0, 12 Mb/s STAT_C_CONNECTION = 0 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 0 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 portstatus 503, change 10, 480 Mb/s STAT_C_CONNECTION = 0 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 1 usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 0x0 New Device 1 XHCI timeout on event type 33... cannot recover. BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()! BUG! Reset CPU by CPC Here is the drivers/usb/host/xhci-baikal.c: #include <common.h> #include <usb.h> #include <linux/errno.h> #include <linux/compat.h> #include <linux/usb/dwc3.h> #include <linux/usb/xhci-omap.h> #include "xhci.h" /* Declare global data pointer */ DECLARE_GLOBAL_DATA_PTR; struct baikal_xhci { struct xhci_hccr *hcd; struct dwc3 *dwc3_reg; }; static struct baikal_xhci baikal; int __attribute__((weak)) board_usb_init(int index, enum usb_init_type init); static int baikal_xhci_core_init(struct baikal_xhci *baikal) { int ret = 0; ret = dwc3_core_init(baikal->dwc3_reg); if (ret) { debug("%s:failed to initialize core\n", __func__); return ret; } /* We are hard-coding DWC3 core to Host Mode */ dwc3_set_mode(baikal->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); return ret; } static void baikal_xhci_core_exit(struct baikal_xhci *baikal) { } int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) { struct baikal_xhci *ctx = &baikal; int ret = 0; ctx->hcd = (struct xhci_hccr *)CONFIG_USB_XHCI_BAIKAL_BASE; ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); ret = board_usb_init(index, USB_INIT_HOST); if (ret != 0) { puts("Failed to initialize board for USB\n"); return ret; } ret = baikal_xhci_core_init(ctx); if (ret < 0) { puts("Failed to initialize xhci\n"); return ret; } *hccr = (struct xhci_hccr *)(CONFIG_USB_XHCI_BAIKAL_BASE); *hcor = (struct xhci_hcor *)((uint32_t) *hccr + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); debug("baikal-xhci: init hccr %x and hcor %x hc_length %d\n", (uint32_t)*hccr, (uint32_t)*hcor, (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); return ret; } void xhci_hcd_stop(int index) { } TIA, Yuri

4 6

[U-Boot] [PATCH] sunxi: Add H6 SPI SPL support
by Marek Kraus 06 Sep '19

06 Sep '19

Add H6 SPI addresses and masks (since H6 memory map is totally different). Tested on Pine H64 rev B with Winbond W25Q128FW, Signed-off-by: Marek Kraus <gamelaster(a)outlook.com> --- arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 123 ++++++++++++++++++++++++++++-------- configs/pine_h64_defconfig | 1 + 3 files changed, 98 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 74e234cded..81b5948454 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -972,7 +972,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN50I_H6 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 043d9f6ead..cdf6d53ec5 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -28,7 +28,7 @@ * A10/A13/A20 (sun4i variant) and everything else (sun6i variant). * Both of them are supported. * - * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are + * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64/H6 are * supported at the moment. */ @@ -70,6 +70,25 @@ #define SUN6I_TCR_XCH BIT(31) /*****************************************************************************/ +/* SUN50I_H6 variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN50I_H6_SPI0_CCTL (0x05010000 + 0x24) +#define SUN50I_H6_SPI0_GCR (0x05010000 + 0x04) +#define SUN50I_H6_SPI0_TCR (0x05010000 + 0x08) +#define SUN50I_H6_SPI0_FIFO_STA (0x05010000 + 0x1C) +#define SUN50I_H6_SPI0_MBC (0x05010000 + 0x30) +#define SUN50I_H6_SPI0_MTC (0x05010000 + 0x34) +#define SUN50I_H6_SPI0_BCC (0x05010000 + 0x38) +#define SUN50I_H6_SPI0_TXD (0x05010000 + 0x200) +#define SUN50I_H6_SPI0_RXD (0x05010000 + 0x300) + +#define SUN50I_H6_SPI_GATING_REG (0x03001000 + 0x96C) +#define SUN50I_H6_SPI0_RST BIT(16) +#define SUN50I_H6_SPI0_GATING_CLK BIT(0) +#define SUN50I_H6_CCU_SPI0_CLK (0x03001000 + 0x940) + +/*****************************************************************************/ #define CCM_AHB_GATING0 (0x01C20000 + 0x60) #define CCM_SPI0_CLK (0x01C20000 + 0xA0) @@ -85,19 +104,29 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + * from SPI Flash, H6 using PC0,PC2,PC3,PC5 , everything else is using + * pins PC0,PC1,PC2,PC3. */ static void spi0_pinmux_setup(unsigned int pin_function) { unsigned int pin; - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) - sunxi_gpio_set_cfgpin(pin, pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); - else + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); + } else { + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) + sunxi_gpio_set_cfgpin(pin, pin_function); + + if (IS_ENABLED(CONFIG_MACH_SUN4I) || + IS_ENABLED(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + } } /* @@ -106,26 +135,43 @@ static void spi0_pinmux_setup(unsigned int pin_function) static void spi0_enable_clock(void) { /* Deassert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_RST); + else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); /* Open the SPI0 gate */ - setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_GATING_CLK); + else + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Divide by 4 */ - writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? - SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + writel(SPI0_CLK_DIV_BY_4, SUN50I_H6_SPI0_CCTL); + else + writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + /* 24MHz from OSC24M */ - writel((1 << 31), CCM_SPI0_CLK); + writel((1 << 31), IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_CCU_SPI0_CLK : CCM_SPI0_CLK); - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { /* Enable SPI in the master mode and do a soft reset */ - setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE | - SUN6I_CTL_SRST); + setbits_le32(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR, + SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | + SUN6I_CTL_SRST); + /* Wait for completion */ - while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + while (readl(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) ; } else { /* Enable SPI in the master mode and reset FIFO */ @@ -139,22 +185,33 @@ static void spi0_enable_clock(void) static void spi0_disable_clock(void) { /* Disable the SPI0 controller */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | - SUN6I_CTL_ENABLE); + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_SPI0_GCR : SUN6I_SPI0_GCR, + SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE); else clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | SUN4I_CTL_ENABLE); /* Disable the SPI0 clock */ - writel(0, CCM_SPI0_CLK); + writel(0, IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? + SUN50I_H6_CCU_SPI0_CLK : CCM_SPI0_CLK); /* Close the SPI0 gate */ - clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + clrbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_GATING_CLK); + else + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); /* Assert SPI0 reset on SUN6I */ - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) - clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) + setbits_le32(SUN50I_H6_SPI_GATING_REG, + SUN50I_H6_SPI0_RST); + else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + setbits_le32(SUN6I_BUS_SOFT_RST_REG0, (1 << AHB_RESET_SPI0_SHIFT)); } @@ -162,7 +219,7 @@ static void spi0_init(void) { unsigned int pin_function = SUNXI_GPC_SPI0; - if (IS_ENABLED(CONFIG_MACH_SUN50I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUN50I_GPC_SPI0; spi0_pinmux_setup(pin_function); @@ -173,7 +230,9 @@ static void spi0_deinit(void) { /* New SoCs can disable pins, older could only set them as input */ unsigned int pin_function = SUNXI_GPIO_INPUT; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) pin_function = SUNXI_GPIO_DISABLE; spi0_disable_clock(); @@ -233,7 +292,17 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) if (chunk_len > SPI_READ_MAX_SIZE) chunk_len = SPI_READ_MAX_SIZE; - if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN50I_H6_SPI0_TCR, + SUN6I_TCR_XCH, + SUN50I_H6_SPI0_FIFO_STA, + SUN50I_H6_SPI0_TXD, + SUN50I_H6_SPI0_RXD, + SUN50I_H6_SPI0_MBC, + SUN50I_H6_SPI0_MTC, + SUN50I_H6_SPI0_BCC); + } else if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { sunxi_spi0_read_data(buf8, addr, chunk_len, SUN6I_SPI0_TCR, SUN6I_TCR_XCH, diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index e34f4fd1e4..baddc33abb 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -6,6 +6,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -- 2.11.0

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[U-Boot] [PATCH] net: mvpp2: support setting hardware addresses from ethernet core
by Matt Pelland 04 Sep '19

04 Sep '19

mvpp2 already has support for setting MAC addresses but this functionality was not exposed to the ethernet core. This commit exposes this functionality so that MAC address assignments stored in U-Boot's environment are correctly applied before Linux boots. Signed-off-by: Matt Pelland <mpelland(a)starry.com> --- drivers/net/mvpp2.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index bcc6fe92a9..d2d17f1417 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -5321,6 +5321,13 @@ static void mvpp2_stop(struct udevice *dev) mvpp2_cleanup_txqs(port); } +static mvpp2_write_hwaddr(struct udevice *dev) +{ + struct mvpp2_port *port = dev_get_priv(dev); + + mvpp2_prs_update_mac_da(port, port->dev_addr); +} + static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port) { writel(port->phyaddr, port->priv->iface_base + @@ -5525,6 +5532,7 @@ static const struct eth_ops mvpp2_ops = { .send = mvpp2_send, .recv = mvpp2_recv, .stop = mvpp2_stop, + .write_hwaddr = mvpp2_write_hwaddr }; static struct driver mvpp2_driver = { -- 2.21.0

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[U-Boot] [u-boot 1/2] drivers/fsl-mc: Create Kconfig file to manage driver specific configs better
by Florinel Iordache 04 Sep '19

04 Sep '19

Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig Signed-off-by: Florinel Iordache <florinel.iordache(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 17 ----------------- drivers/net/Kconfig | 1 + drivers/net/fsl-mc/Kconfig | 25 +++++++++++++++++++++++++ 3 files changed, 26 insertions(+), 17 deletions(-) create mode 100644 drivers/net/fsl-mc/Kconfig diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f48481f..87f84f7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -226,14 +226,6 @@ config FSL_LSCH3 config NXP_LSCH3_2 bool -config FSL_MC_ENET - bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A - default y - select RESV_RAM - help - Enable Management Complex (MC) network - menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 @@ -567,15 +559,6 @@ config SYS_FSL_HAS_RGMII bool depends on SYS_FSL_EC1 || SYS_FSL_EC2 - -config SYS_MC_RSV_MEM_ALIGN - hex "Management Complex reserved memory alignment" - depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A - help - Reserved memory needs to be aligned for MC to use. Default value - is 512MB. - config SPL_LDSCRIPT default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 77d0b3a..3627456 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1,5 +1,6 @@ source "drivers/net/phy/Kconfig" source "drivers/net/pfe_eth/Kconfig" +source "drivers/net/fsl-mc/Kconfig" config DM_ETH bool "Enable Driver Model for Ethernet drivers" diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig new file mode 100644 index 0000000..25a2cb8 --- /dev/null +++ b/drivers/net/fsl-mc/Kconfig @@ -0,0 +1,25 @@ +# +# NXP Management Complex +# + +menuconfig FSL_MC_ENET + bool "NXP Management Complex" + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + default y + select RESV_RAM + help + Enable Management Complex (MC) network + This is NXP Management Complex menuconfig + that contains all MC related config options + +if FSL_MC_ENET + +config SYS_MC_RSV_MEM_ALIGN + hex "Management Complex reserved memory alignment" + depends on RESV_RAM + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + help + Reserved memory needs to be aligned for MC to use. Default value + is 512MB. + +endif # FSL_MC_ENET -- 1.9.1

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[U-Boot] RSA in U-Boot
by AKASHI, Takahiro 28 Aug '19

28 Aug '19

Hi, I'd like to discuss this topic in public. I will appreciate your comments here. # FYI, I now started to experimentally port linux's pkcs7/x509 # parser. Thanks, -Takahiro Akashi ----- Forwarded message from Simon Glass <sjg(a)chromium.org> ----- Date: Thu, 7 Mar 2019 19:56:10 -0700 From: Simon Glass <sjg(a)chromium.org> To: "AKASHI, Takahiro" <takahiro.akashi(a)linaro.org> Subject: Re: RSA in U-Boot Hi Takahiro, On Thu, 7 Mar 2019 at 17:27, AKASHI, Takahiro <takahiro.akashi(a)linaro.org> wrote: > > Hi Simon, > > Before I start discussions publicly, I'd like to hear > your opinion first. I do think it is better to discuss this in public since there will be other opinions. > > I'm now working on implementing "secure boot" > for UEFI U-Boot. > > As you might know, there are a couple of features > required to achieve "secure boot": > (I won't discuss about secure storage here though.) > - x509 certificate decoder > - pkcs7 decoder (for PE file's signature) > - RSA verification > - (hash digest, sha256) > > The original code, which was written by some other guy, > Patrick, uses BearSSL for x509 and RSA and > I'm now wondering what is the best solution. > Obviously, I can think of several options here: > 1. use BearSSL > 1.a just import minimum set of files akin lib/libfdt > 1.b link whole BearSSL as a library, merging the code > as git submodule > 2. use openssl > 3. import linux kernel code, particularly x509 & pkcs7 parser > 4. write our own code > > I suppose that you weighed similar choices when you implemented > "FIT image signing". > Can you share your opinion with me? I think if you can do 3 then it keeps U-Boot self-contained and perhaps provides for simple code. That said, if the amount of code is large and has an upstream there is clear precident for 1a, as you say. I am not sure about 4. If it is a relatively small amount of code, then maybe, but surely it makes sense to use the linux code where possible. That is what I did with the U-Boot livetree code. 1b sounds painful to me. > > Regarding your lib/rsa code, you intentionally avoided to > add formula of inverse-mod and power-mod of R. Do you still > believe that the assumption is appropriate? > (BearSSL implements its own montgomery. If you look at a talk I gave on this, you can see that one of the goals was to implement it efficiently, with minimal extra code at run-time, and minimal memory usage. So unpacking complex key structures did not seem like a good idea. From memory you can do verified boot in about 7KB of extra code in U-Boot and it runs in a small number of milliseconds. UEFI is obviously pretty big, so perhaps efficiency concerns are less important. More important probably is wide compatibility, supporting all possible options, etc. I hope this is helpful. Regards, Simon ----- End forwarded message -----

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