April 2019 - U-Boot

[U-Boot] [PATCH v1 0/5] colibri imx8qxp 2gb wb it v1.0b module support
by Marcel Ziswiler 09 Apr '19

09 Apr '19

This series fixes the i.MX 8QXP SCFW API header file, adds support for more lpuart instances, cleans-up and extends the Toradex SKU handling and last but not least introduces support for the Toradex Colibri iMX8QXP 2GB WB IT V1.0B module. This series is available together with my previous series addressing Apalis and Colibri iMX6 as well as Colibri Vybrid aka VF50/VF61 and Colibri iMX6ULL on our git server [1]. [1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Marcel Ziswiler (5): misc: imx8: remove duplicates from scfw api arm: dts: imx8dx: add lpuart1, lpuart2, lpuart3 board: toradex: tdx-cfg-block: clean-up sku handling board: toradex: tdx-cfg-block: add new skus board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support arch/arm/dts/Makefile | 4 +- arch/arm/dts/fsl-imx8dx.dtsi | 54 +++ arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 112 ++++++ arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++++++++++++++++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 4 - arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/colibri-imx8qxp/Kconfig | 30 ++ board/toradex/colibri-imx8qxp/MAINTAINERS | 9 + board/toradex/colibri-imx8qxp/Makefile | 7 + board/toradex/colibri-imx8qxp/README | 67 ++++ .../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 211 +++++++++++ board/toradex/colibri-imx8qxp/imximage.cfg | 24 ++ board/toradex/common/tdx-cfg-block.c | 19 +- board/toradex/common/tdx-cfg-block.h | 29 +- configs/colibri-imx8qxp_defconfig | 53 +++ include/configs/colibri-imx8qxp.h | 240 +++++++++++++ 16 files changed, 1178 insertions(+), 19 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts create mode 100644 board/toradex/colibri-imx8qxp/Kconfig create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS create mode 100644 board/toradex/colibri-imx8qxp/Makefile create mode 100644 board/toradex/colibri-imx8qxp/README create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg create mode 100644 configs/colibri-imx8qxp_defconfig create mode 100644 include/configs/colibri-imx8qxp.h -- 2.20.1

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[U-Boot] [PATCH] arm: sunxi: Add support for the RerVision H3-DVK board
by Paul Kocialkowski 09 Apr '19

09 Apr '19

This is an H3-based board that sticks close to the reference design. Supported features: * UART * DRAM * MMC * eMMC * Ethernet * USB host * USB peripheral * HDMI Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-h3-rervision-dvk.dts | 107 ++++++++++++++++++++++++ configs/rervision_h3_dvk_defconfig | 17 ++++ 3 files changed, 126 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun8i-h3-rervision-dvk.dts create mode 100644 configs/rervision_h3_dvk_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2a040b20a539..a64c0fada4cb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -401,7 +401,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb + sun8i-h3-orangepi-plus2e.dtb \ + sun8i-h3-rervision-dvk.dtb dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v40-bananapi-m2-berry.dtb diff --git a/arch/arm/dts/sun8i-h3-rervision-dvk.dts b/arch/arm/dts/sun8i-h3-rervision-dvk.dts new file mode 100644 index 000000000000..8a4b83a02d9d --- /dev/null +++ b/arch/arm/dts/sun8i-h3-rervision-dvk.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Bootlin + * Author: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "RerVision H3-DVK"; + compatible = "rervision,h3-dvk", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_input: endpoint { + remote-endpoint = <&hdmi_connector_output>; + }; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_connector_output: endpoint { + remote-endpoint = <&hdmi_connector_input>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; + vmmc-supply = <&reg_vcc3v3>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + drive-strength = <40>; + bias-pull-up; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/configs/rervision_h3_dvk_defconfig b/configs/rervision_h3_dvk_defconfig new file mode 100644 index 000000000000..895a985ccdcd --- /dev/null +++ b/configs/rervision_h3_dvk_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-rervision-dvk" +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_FASTBOOT=y -- 2.20.1

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[U-Boot] [ANN] U-Boot v2019.04-rc4 released
by Tom Rini 09 Apr '19

09 Apr '19

Hey all, So it's release day and I've put up v2019.04-rc4, I've updated git and the tarballs are also up now. Thanks again to having signed tags, between -rc3 and -rc4 we have a good changelog under 'git log --merges v2019.04-rc3..v2019.04-rc4' Right now I have outstanding changes in u-boot-socfpga and u-boot-usb to apply. I will, I've just been kicking builds on migrating CONFIG_SPL_TEXT_BASE today, and I don't want to hold everything up on being able to test those PRs. We're looking at release on April 8th, 2019. Thanks all! -- Tom

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[U-Boot] [PATCH] test: dm: regmap: Fix the long test delay
by Simon Glass 09 Apr '19

09 Apr '19

At present one of the regmap tests takes 5 seconds to run since it waits for a timeout. This should be handled using sandbox_timer_add_offset() which advances time for test purposes. This requires a little change to make the regmap_read_poll_timeout() testable. Update the macro and the test. Fixes: ebe3497c9c ("test: regmap: add regmap_read_poll_timeout test") Signed-off-by: Simon Glass <sjg(a)chromium.org> --- include/regmap.h | 14 +++++++++++++- test/dm/regmap.c | 7 ++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/include/regmap.h b/include/regmap.h index a3afb72df51..8359c511d25 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -248,6 +248,8 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, * @cond: Break condition (usually involving @val) * @sleep_us: Maximum time to sleep between reads in us (0 tight-loops). * @timeout_ms: Timeout in ms, 0 means never timeout + * @test_add_time: Used for sandbox testing - amount of time to add after + * starting the loop (0 if not testing) * * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read * error return value in case of a error read. In the two former cases, @@ -256,8 +258,12 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, * * This is modelled after the regmap_read_poll_timeout macros in linux but * with millisecond timeout. + * + * The _test version is for sandbox testing only. Do not use this in normal + * code as it advances the timer. */ -#define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_ms) \ +#define regmap_read_poll_timeout_test(map, addr, val, cond, sleep_us, \ + timeout_ms, test_add_time) \ ({ \ unsigned long __start = get_timer(0); \ int __ret; \ @@ -267,6 +273,8 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, break; \ if (cond) \ break; \ + if (IS_ENABLED(CONFIG_SANDBOX) && test_add_time) \ + sandbox_timer_add_offset(test_add_time); \ if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \ __ret = regmap_read((map), (addr), &(val)); \ break; \ @@ -277,6 +285,10 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, __ret ?: ((cond) ? 0 : -ETIMEDOUT); \ }) +#define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_ms) \ + regmap_read_poll_timeout_test(map, addr, val, cond, sleep_us, \ + timeout_ms, 0) \ + /** * regmap_update_bits() - Perform a read/modify/write using a mask * diff --git a/test/dm/regmap.c b/test/dm/regmap.c index 9a70c159ddb..82de295cb8f 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -160,9 +160,10 @@ static int dm_test_regmap_poll(struct unit_test_state *uts) start = get_timer(0); ut_asserteq(-ETIMEDOUT, - regmap_read_poll_timeout(map, 0, reg, - (reg == 0xcacafafa), - 1, 5 * CONFIG_SYS_HZ)); + regmap_read_poll_timeout_test(map, 0, reg, + (reg == 0xcacafafa), + 1, 5 * CONFIG_SYS_HZ, + 5 * CONFIG_SYS_HZ)); ut_assert(get_timer(start) > (5 * CONFIG_SYS_HZ)); -- 2.20.0.rc2.403.gdbc3b29805-goog

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[U-Boot] [PATCH v5] arm: dts: Stratix10: Add QSPI node
by Ley Foon Tan 09 Apr '19

09 Apr '19

Merge qspi dts node from Linux. Commit 0cb140d07fc75fb (arm64: dts: stratix10: Add QSPI support for Stratix10) Add -u-boot.dtsi files for non Linux dts properties and update properties for Uboot. - add u-boot,dm-pre-reloc - add alias for spi0 - change compatible for flash - support quad read and quad write - change maximum frequency to 100MHz Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- v4->v5: - Add -u-boot.dtsi - Update commit message with Linux commit ID v3->v4: - Add qspi node to dtsi based on alphabetical order - Add spi-tx-bus-width and spi-rx-bus-width v2->v3: - Change flash compatible to "jedec,spi-nor" - Change spi-max-frequency to 100MHz --- arch/arm/dts/socfpga_stratix10.dtsi | 13 +++++++ .../dts/socfpga_stratix10_socdk-u-boot.dtsi | 25 +++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 35 +++++++++++++++++++ 3 files changed, 73 insertions(+) mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10.dtsi create mode 100755 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi mode change 100644 => 100755 arch/arm/dts/socfpga_stratix10_socdk.dts diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi old mode 100644 new mode 100755 index ee93725d648..d1ae2fabae0 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -237,6 +237,19 @@ reg = <0xffe00000 0x100000>; }; + qspi: spi@ff8d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + status = "disabled"; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi new file mode 100755 index 00000000000..e1cfb522bfc --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +/{ + aliases { + spi0 = &qspi; + }; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts old mode 100644 new mode 100755 index 6e8ddcd9f4c..09c8a174671 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -85,6 +85,41 @@ smplsel = <0>; }; +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00a"; + reg = <0>; + spi-max-frequency = <50000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x4000000>; + }; + + qspi_rootfs: partition@4000000 { + label = "Root Filesystem - JFFS2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + &uart0 { status = "okay"; }; -- 2.19.0

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[U-Boot] [PATCH 1/3] arm: sunxi: Allow per-platform DRAM ZQ configuration on sun8i
by Paul Kocialkowski 09 Apr '19

09 Apr '19

A few sun8i platforms define specific default DRAM ZQ values, but they are not taken in account because of MACH_SUN8I being used for the 123 default first. Replace MACH_SUN8I with the list of platforms that don't have specific DRAM ZQ values, to avoid overwriting the default for those that do. Signed-off-by: Paul Kocialkowski <paul.kocialkowski(a)bootlin.com> --- arch/arm/mach-sunxi/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 74e234cded75..c557c79ef097 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -414,7 +414,9 @@ endif config DRAM_ZQ int "sunxi dram zq value" - default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I + default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ + MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T || \ + MACH_SUNXI_H3_H5 default 127 if MACH_SUN7I default 14779 if MACH_SUN8I_V3S default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6 -- 2.20.1

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[U-Boot] [V3 1/3] sunxi: Fix A33 memory initialization
by Shyam Saini 09 Apr '19

09 Apr '19

From: Michael Trimarchi <michael(a)amarulasolutions.com> While the exact problem is not known, based on discussion between Philipp Tomsich and André Przywara it is guessed that exit self-refresh timing is not set with correct value. There may be implicit enter or exit Self-Refresh anywhere as part of some training phase. In ZynqMP register guide [1], which is close to the various Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL tXS is bits [6:0]: Self refresh exit delay. So it could be safely increased and it only affects the time after the self-refresh “exit”, which happens only after (re-)initialisation. There was no document for cpu in question so based on oscilloscope readings [2][3] and observed result by comparing allwinner architecture. So set it same as Allwinner H5 silicon. Before this patch, failure rate of was 7%. This was tested on A33 allwinner cpu, dual rank connection connected with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3 1.5V [1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html [2] https://ibb.co/R70zmyS [3] https://ibb.co/HVVCGQ8 Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> Signed-off-by: Shyam Saini <shyam.saini(a)amarulasolutions.com> --- Changelogs: V1->V2: adjust commit message V2->V3: Adjust commit message based on V2 Discussion --- arch/arm/mach-sunxi/dram_sun8i_a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index 1da2727f9874..5da01922bfaf 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -152,7 +152,7 @@ static void auto_set_timing_para(struct dram_para *para) reg_val &= ~(0xff << 8); reg_val &= ~(0xff << 0); reg_val |= (0x33 << 8); - reg_val |= (0x8 << 0); + reg_val |= (0x10 << 0); writel(reg_val, &mctl_ctl->dramtmg8); /* Set phy interface time */ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) -- 2.11.0

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[U-Boot] [PATCH 1/3] i2c: muxes: pca954x: update list of supported devices
by Luca Ceresoli 09 Apr '19

09 Apr '19

The Kconfig help has not been updated while adding PCA9547 and PCA9646. Signed-off-by: Luca Ceresoli <luca(a)lucaceresoli.net> --- drivers/i2c/muxes/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index b0da67ce2c6b..26be78f685de 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -33,7 +33,7 @@ config I2C_MUX_PCA954x I2C mux/switch devices. It is x width I2C multiplexer which enables to partitioning I2C bus and connect multiple devices with the same address to the same I2C controller where driver handles proper routing to - target i2c device. PCA9544 and PCA9548 are supported. + target i2c device. PCA9544, PCA9547 PCA9548 and PCA9646 are supported. config I2C_MUX_GPIO tristate "GPIO-based I2C multiplexer" -- 2.21.0

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[U-Boot] [PATCH 1/1] efi_loader: debug output file handle in efi_file_open()
by Heinrich Schuchardt 09 Apr '19

09 Apr '19

For debugging it is helpful to know the address of the file handle created by the Open() method of the EFI file protocol. So let's write it with EFI_PRINT(). Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/efi_file.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 0483403be0d..39e37749fe2 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -257,10 +257,12 @@ static efi_status_t EFIAPI efi_file_open(struct efi_file_handle *file, /* Open file */ *new_handle = file_open(fh->fs, fh, file_name, open_mode, attributes); - if (*new_handle) + if (*new_handle) { + EFI_PRINT("file handle %p\n", *new_handle); ret = EFI_SUCCESS; - else + } else { ret = EFI_NOT_FOUND; + } out: return EFI_EXIT(ret); } -- 2.20.1

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[U-Boot] [PATCH 1/1] efi_loader: define development target in README.uefi
by Heinrich Schuchardt 09 Apr '19

09 Apr '19

Describe the target scope of the UEFI implementation in U-Boot. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- doc/README.uefi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/doc/README.uefi b/doc/README.uefi index b38efbc0cc..66b6abece5 100644 --- a/doc/README.uefi +++ b/doc/README.uefi @@ -12,6 +12,15 @@ the interaction of drivers and applications with the firmware. The API comprises access to block storage, network, and console to name a few. The Linux kernel and boot loaders like GRUB or the FreeBSD loader can be executed. +## Development target + +The implementation of UEFI in U-Boot strives to reach the minimum requirements +described in "Server Base Boot Requirements System Software on ARM Platforms - +Version 1.1" [4]. + +A full blown UEFI implementation would contradict the U-Boot design principle +"keep it small". + ## Building for UEFI The UEFI standard supports only little-endian systems. The UEFI support can be @@ -335,3 +344,5 @@ This driver is only available if U-Boot is configured with http://uefi.org/specifications - UEFI specifications * [2](./driver-model/README.txt) doc/driver-model/README.txt - Driver model * [3](./README.iscsi) doc/README.iscsi - iSCSI booting with U-Boot and iPXE +* [4](https://developer.arm.com/docs/den0044/latest/server-base-boot-requireme… + Server Base Boot Requirements System Software on ARM Platforms - Version 1.1 -- 2.20.1

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