April 2019 - U-Boot

[U-Boot] [PATCH 1/2] ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration
by Ludwig Zenz 12 Apr '19

12 Apr '19

The four x16 DDR3 are wired in T-topology. From NXP AN4467: 'Although not required, T-Topologies may also benefit from performing Write Leveling as there are package delays on both the processor and DDR devices that can be de-skewed by performing Write Leveling. Therefore, Freescale recommends determining Write Leveling calibration parameters for all boards, regardless of topology used.' That is why write level calibration is also done. Signed-off-by: Ludwig Zenz <lzenz(a)dh-electronics.com> --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index 04e9eab272a..bbd2dc26828 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -482,6 +482,29 @@ static void setup_iomux_usb(void) SETUP_IOMUX_PADS(usb_pads); } +/* Perform DDR DRAM calibration */ +static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret = 0; + +#ifdef CONFIG_MX6_DDRCAL + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR3: Write level calibration error [%d]\n", ret); + return ret; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR3: DQS calibration error [%d]\n", ret); + return ret; + } +#endif /* CONFIG_MX6_DDRCAL */ + + return ret; +} + /* DRAM */ static void dhcom_spl_dram_init(void) @@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6DL)) { mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, @@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, @@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_32bit); + spl_dram_perform_cal(&dhcom_ddr_32bit); } } -- 2.11.0

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[U-Boot] [PATCH] MAINTAINERS: Change Jagan's email address
by Jagan Teki 12 Apr '19

12 Apr '19

Missed few mails from openedev, since most of the day I look at amarulasolutions mail box so change the email address to use amarulasolutions mail id. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- MAINTAINERS | 6 +++--- board/sunxi/MAINTAINERS | 2 +- doc/git-mailrc | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index f9ee4281d9..1598dc866e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -308,7 +308,7 @@ F: arch/arm/cpu/armv7/stv0991/ F: arch/arm/include/asm/arch-stv0991/ ARM SUNXI -M: Jagan Teki <jagan(a)openedev.com> +M: Jagan Teki <jagan(a)amarulasolutions.com> M: Maxime Ripard <maxime.ripard(a)bootlin.com> S: Maintained T: git git://git.denx.de/u-boot-sunxi.git @@ -689,14 +689,14 @@ T: git git://git.denx.de/u-boot-sh.git F: arch/sh/ SPI -M: Jagan Teki <jagan(a)openedev.com> +M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained T: git git://git.denx.de/u-boot-spi.git F: drivers/spi/ F: include/spi* SPI-NOR -M: Jagan Teki <jagan(a)openedev.com> +M: Jagan Teki <jagan(a)amarulasolutions.com> M: Vignesh R <vigneshr(a)ti.com> S: Maintained F: drivers/mtd/spi/ diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 8e2f90fc68..8dd0da4aeb 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -348,7 +348,7 @@ F: configs/A20-Olimex-SOM204-EVB_defconfig F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig ORANGEPI LITE2 BOARD -M: Jagan Teki <jagan(a)openedev.com> +M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/orangepi_lite2_defconfig diff --git a/doc/git-mailrc b/doc/git-mailrc index b75ebab02b..9cf180779c 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -24,7 +24,7 @@ alias dinh Dinh Nguyen <dinguyen(a)kernel.org> alias hs Heiko Schocher <hs(a)denx.de> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> alias jaehoon Jaehoon Chung <jh80.chung(a)samsung.com> -alias jagan Jagan Teki <jagan(a)openedev.com> +alias jagan Jagan Teki <jagan(a)amarulasolutions.com> alias jhersh Joe Hershberger <joe.hershberger(a)ni.com> alias luka Luka Perkov <luka.perkov(a)sartura.hr> alias lukma Lukasz Majewski <lukma(a)denx.de> -- 2.18.0.321.gffc6fa0e3

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[U-Boot] mvebu spl: translation offset set too late?
by Pierre Bourdon 12 Apr '19

12 Apr '19

[cc: mvebu maintainers] I've spent the best part of today trying to get upstream u-boot running on my Armada 835 device (Turris Omnia). I think in the process I might have uncovered a bug with SPL u-boot on these SoC. mvebu is "special" in having a different memory map in SPL vs. "main" mode. The arch SPL initialization code calls dm_set_translation_offset to tell the DM subsystem how to translate addresses. However, this is called *after* spl_init, which triggers a DM scan. So at the point where the DM subsystem is aware of the translation offset, drivers might have already cached addresses (priv->base) or even performed initialization (the TWSI i2c module does some configuration at bind time). This seems broken but I'm not experienced enough with u-boot to suggest a good fix here. Could someone confirm that at least I'm not completely off base with this analysis? Thanks, Best, -- Pierre Bourdon <delroth(a)gmail.com> Software Engineer @ Zürich, Switzerland https://delroth.net/

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[U-Boot] [PATCH] mtd: spi-nor-ids: Add Gigadevice gd25lq128 ID
by Neil Armstrong 12 Apr '19

12 Apr '19

This adds support for the Gigadevice gd25lq128 ID needed on the upcoming libretech-ac board. SPI_NOR_QUAD_READ is not set since it has not been tested in Quad mode. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3215e2431d..f658528a53 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -106,6 +106,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- 2.21.0

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[U-Boot] [PATCH v2 0/2] Update pinctrl-uclass
by Patrice Chotard 12 Apr '19

12 Apr '19

This series adds: - For system with multiple pincontroller device, insure probe order to avoid race condition using sequence number (alias) - Avoid to bind child node with gpio-controller properties. Changes in v2: - Update commit message with explanaition Patrice Chotard (1): dm: pinctrl: Avoid race condition on probe for UCLASS_PINCTRL Patrick Delaunay (1): dm: pinctrl: Skip gpio-controller node in pinconfig_post_bind() drivers/pinctrl/pinctrl-uclass.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) -- 1.9.1

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[U-Boot] [PATCH v2 1/2] common: spl_fit: Default to IH_OS_U_BOOT if FIT_IMAGE_TINY enabled
by Abel Vesa 12 Apr '19

12 Apr '19

If FIT_IMAGE_TINY is enabled, spl_fit_image_get_os returns -ENOTSUPP. In this case, we should default to IH_OS_U_BOOT not to IH_OS_INVALID. Signed-off-by: Abel Vesa <abel.vesa(a)nxp.com> --- Changes since v1: * added the #if FIT_IMAGE_TINY as suggested by Mark Vasut common/spl/spl_fit.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index db43626..c9bfe0c 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -491,6 +491,10 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (!spl_fit_image_get_os(fit, node, &os_type)) debug("Loadable is %s\n", genimg_get_os_name(os_type)); +#if CONFIG_IS_ENABLED(FIT_IMAGE_TINY) + else + os_type = IH_OS_U_BOOT; +#endif if (os_type == IH_OS_U_BOOT) { spl_fit_append_fdt(&image_info, info, sector, -- 2.7.4

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[U-Boot] [PATCH 0/2] ti_qspi: Move to spi-mem framework
by Vignesh R 12 Apr '19

12 Apr '19

Now that SPI NOR Supports MMIO SPI controllers via spi-mem framework, move TI QSPI to SPI MEM framework for better performance and avoid repeating SPI NOR generic code in the driver. While at that get rid of non DM code, as all boards are expected to support DM and DT by now. Note: This *breaks cl-som-am57x_defconfig*, as defconfig does not enable even basic CONFIG_DM and would surely be dropped in next merge window. Tested on AM43xx, dra7xx EVMs Vignesh R (2): spi: ti_qspi: Drop non DM code spi: ti_qspi: Convert to spi-mem ops drivers/spi/Kconfig | 12 +- drivers/spi/Makefile | 2 +- drivers/spi/ti_qspi.c | 351 ++++++++++----------------------- include/configs/am43xx_evm.h | 2 - include/configs/am57xx_evm.h | 2 - include/configs/cl-som-am57x.h | 1 - include/configs/cm_t43.h | 1 - include/configs/dra7xx_evm.h | 2 - scripts/config_whitelist.txt | 2 - 9 files changed, 107 insertions(+), 268 deletions(-) -- 2.20.1

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[U-Boot] U-Boot API example doesn't support 64-bit
by Priebe, Sebastian 12 Apr '19

12 Apr '19

Hello, I'd like to use the U-Boot external API with an ARM64 SoC. If I enable CONFIG_API I get the following build error for the API example: examples/api/crt0.S: Assembler messages: examples/api/crt0.S:33: Error: operand 1 should be an integer register -- `ldr ip,=search_hint' examples/api/crt0.S:34: Error: operand 1 should be an integer register -- `str sp,[ip]' examples/api/crt0.S:40: Error: operand 1 should be an integer register -- `ldr ip,=syscall_ptr' examples/api/crt0.S:41: Error: operand 1 should be an integer register -- `ldr pc,[ip]' scripts/Makefile.build:316: recipe for target 'examples/api/crt0.o' failed For me it seems that the example lacks support for 64-bit. Can anybody help me to get the example running on 64-bit? Apparently I have only very litte knowledge of assembler :-( Best regards Sebastian Priebe SII Technologies GmbH SII Technologies GmbH Geschäftsführer: Robert Bauer Sitz der Gesellschaft: 86167 Augsburg Registergericht: Amtsgericht Augsburg HRB 31802

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[U-Boot] [PATCH v2 0/5] net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver
by Keerthy 12 Apr '19

12 Apr '19

Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. The series is based on top of Vignesh's v3: https://patchwork.ozlabs.org/patch/1032504/ Tested for tftp and booting to kernel on am654-evm. Grygorii Strashko (4): driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addr arm64: dts: ti: k3-am65: add mcu cpsw node arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defs configs: am65x_evm_a53: enable networking Keerthy (1): net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver arch/arm/dts/k3-am65.dtsi | 2 + arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 170 ++++ configs/am65x_evm_a53_defconfig | 7 + drivers/net/ti/Kconfig | 8 + drivers/net/ti/Makefile | 1 + drivers/net/ti/am65-cpsw-nuss.c | 794 +++++++++++++++++++ drivers/net/ti/cpsw_mdio.c | 2 +- drivers/net/ti/cpsw_mdio.h | 2 +- 8 files changed, 984 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ti/am65-cpsw-nuss.c -- 2.17.1

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[U-Boot] [PATCH v2 1/2] ARM: mvebu: rename armada-385-amc.dts to armada-385-db-88f6820-amc.dts
by Chris Packham 12 Apr '19

12 Apr '19

This board was added to u-boot first but the Linux maintainers requested a more descriptive name. Rename the file to match the Linux usage and update the board defconfig. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- Changes in v2: - rebase against u-boot-marvell/master arch/arm/dts/Makefile | 2 +- .../dts/{armada-385-amc.dts => armada-385-db-88f6820-amc.dts} | 0 configs/db-88f6820-amc_defconfig | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/dts/{armada-385-amc.dts => armada-385-db-88f6820-amc.dts} (100%) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7704dfb81334..4f661552b0a6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -140,7 +140,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-clearfog.dtb \ armada-388-gp.dtb \ armada-388-helios4.dtb \ - armada-385-amc.dtb \ + armada-385-db-88f6820-amc.dtb \ armada-385-turris-omnia.dtb \ armada-7040-db.dtb \ armada-7040-db-nand.dtb \ diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-db-88f6820-amc.dts similarity index 100% rename from arch/arm/dts/armada-385-amc.dts rename to arch/arm/dts/armada-385-db-88f6820-amc.dts diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index dcf2a25395e2..e8ba5184c4d7 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set -CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc" +CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=50000000 -- 2.21.0

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