April 2019 - U-Boot

[U-Boot] [PATCH 1/2] scsi: ceva: Clean up the driver code
by Peng Ma 17 Apr '19

17 Apr '19

Distinguish the ecc val by chassis version and move the ecc addr to dts. Add ls1028a soc support. Signed-off-by: Peng Ma <peng.ma(a)nxp.com> --- drivers/ata/sata_ceva.c | 43 +++++++++++++++++++++++++------------------ 1 files changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 8887be9..d26f712 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -88,20 +88,16 @@ #define LS1021_CEVA_PHY4_CFG 0x064a080b #define LS1021_CEVA_PHY5_CFG 0x2aa86470 -/* for ls1088a */ -#define LS1088_ECC_DIS_ADDR_CH2 0x100520 -#define LS1088_ECC_DIS_VAL_CH2 0x40000000 - -/* ecc addr-val pair */ -#define ECC_DIS_ADDR_CH2 0x20140520 +/* ecc val pair */ +#define ECC_DIS_VAL_CH1 0x00020000 #define ECC_DIS_VAL_CH2 0x80000000 -#define SATA_ECC_REG_ADDR 0x20220520 -#define SATA_ECC_DISABLE 0x00020000 +#define ECC_DIS_VAL_CH3 0x40000000 enum ceva_soc { CEVA_1V84, CEVA_LS1012A, CEVA_LS1021A, + CEVA_LS1028A, CEVA_LS1043A, CEVA_LS1046A, CEVA_LS1088A, @@ -110,12 +106,14 @@ enum ceva_soc { struct ceva_sata_priv { ulong base; + ulong ecc_base; enum ceva_soc soc; ulong flag; }; static int ceva_init_sata(struct ceva_sata_priv *priv) { + ulong ecc_addr = priv->ecc_base; ulong base = priv->base; ulong tmp; @@ -132,38 +130,38 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) break; case CEVA_LS1021A: - writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR); + if (ecc_addr) + writel(ECC_DIS_VAL_CH1, ecc_addr); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C); writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C); writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C); writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); - if (priv->flag & FLAG_COHERENT) - writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC); break; case CEVA_LS1012A: case CEVA_LS1043A: case CEVA_LS1046A: - writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2); - /* fallthrough */ case CEVA_LS2080A: + if (ecc_addr) + writel(ECC_DIS_VAL_CH2, ecc_addr); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); - if (priv->flag & FLAG_COHERENT) - writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); break; + case CEVA_LS1028A: case CEVA_LS1088A: - writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2); + if (ecc_addr) + writel(ECC_DIS_VAL_CH3, ecc_addr); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); - if (priv->flag & FLAG_COHERENT) - writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); break; } + if (priv->flag & FLAG_COHERENT) + writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); + return 0; } @@ -187,6 +185,7 @@ static const struct udevice_id sata_ceva_ids[] = { { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 }, { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, + { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A }, { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A }, @@ -205,8 +204,16 @@ static int sata_ceva_ofdata_to_platdata(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; + priv->ecc_base = dev_read_addr_index(dev, 1); + if (priv->ecc_base == FDT_ADDR_T_NONE) + priv->ecc_base = 0; + priv->soc = dev_get_driver_data(dev); + debug("ccsr-sata-base %lx\t ecc-base %lx\n", + priv->base, + priv->ecc_base); + return 0; } -- 1.7.1

2 15

[U-Boot] SPL
by Linder Pascal 17 Apr '19

17 Apr '19

Hello everyone, With my NanoPi NEO Plus2 board, I try to make some modifications on the Flattened Image Tree (FIT). This includes compression and also some security features like signing/verifying. But I do not know if my modifications worked out. It is a FIT that is started by the SPL, i.e. it includes U-Boot, the ATF and the device tree blob for the bootloader. Therefore, I cannot see anything in the console that assures the proper function. Also, I wonder if it is even possible to sign the U-Boot image and verify it by the SPL. What functions does the sunxi SPL even support? For your answers I would be really grateful. Sincerely, Pascal Linder Student Telekommunikation Netzwerke und Sicherheit Klasse T-3b

1 0

[U-Boot] [PATCH v2 1/1] colibri_imx7: migrate usb to driver model
by Igor Opaniuk 17 Apr '19

17 Apr '19

Migrate USB to Driver Model (CONFIG_DM_USB=y). Tested-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk(a)toradex.com> --- v2: - Drop vbus-supply property for usbotg1 node, as on Colibri the turning on of the USB host power is actually done purely in hardware based on the cable detect pin arch/arm/dts/imx7-colibri-emmc.dts | 36 +++++++++++++++++++++++++ arch/arm/dts/imx7-colibri-rawnand.dts | 39 +++++++++++++++++++++++++++ configs/colibri_imx7_defconfig | 1 + configs/colibri_imx7_emmc_defconfig | 1 + 4 files changed, 77 insertions(+) diff --git a/arch/arm/dts/imx7-colibri-emmc.dts b/arch/arm/dts/imx7-colibri-emmc.dts index efd600091d..371c680025 100644 --- a/arch/arm/dts/imx7-colibri-emmc.dts +++ b/arch/arm/dts/imx7-colibri-emmc.dts @@ -13,11 +13,30 @@ aliases { mmc0 = &usdhc3; mmc1 = &usdhc1; + usb0 = &usbotg1; /* required for ums */ }; chosen { stdout-path = &uart1; }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <&reg_5v0>; + }; }; &usdhc3 { @@ -44,4 +63,21 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 >; }; + + pinctrl_usbh_reg: gpio-usbh-vbus { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; +}; + +&usbotg2 { + dr_mode = "host"; + vbus-supply = <&reg_usbh_vbus>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; }; diff --git a/arch/arm/dts/imx7-colibri-rawnand.dts b/arch/arm/dts/imx7-colibri-rawnand.dts index 4eb86fb011..69a9c6a914 100644 --- a/arch/arm/dts/imx7-colibri-rawnand.dts +++ b/arch/arm/dts/imx7-colibri-rawnand.dts @@ -13,6 +13,28 @@ chosen { stdout-path = &uart1; }; + + aliases { + usb0 = &usbotg1; /* required for ums */ + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <&reg_5v0>; + }; }; &gpmi { @@ -43,4 +65,21 @@ MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 >; }; + + pinctrl_usbh_reg: gpio-usbh-vbus { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; +}; + +&usbotg2 { + dr_mode = "host"; + vbus-supply = <&reg_usbh_vbus>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; }; diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 7a52361a2a..43af825d5c 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -62,6 +62,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y +CONFIG_DM_USB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 5e2a204a88..beec2704c5 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -64,3 +64,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_VIDEO=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_USB=y -- 2.17.1

2 2

[U-Boot] [PATCH v5] arm: socfpga: move gen5 SDR driver to DM
by Simon Goldschmidt 16 Apr '19

16 Apr '19

To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- Changes in v5: - fix Kconfig dependencies so that non-gen5 socfpga is fixed Changes in v2: - port DDR driver to DM UCLASS_RAM - don't change DDR calibration training driver (code got too big) - use reset.h code instead of socfpga_per_reset() For v5, this is the only patch left with changes (all other patches are OK from v4, but this one needed changes). Being like that, this patch alone isn't applicable but needs all other patches from v4. --- arch/arm/dts/socfpga.dtsi | 4 +- .../mach-socfpga/include/mach/sdram_gen5.h | 4 - arch/arm/mach-socfpga/spl_gen5.c | 29 ++-- drivers/ddr/altera/Kconfig | 2 + drivers/ddr/altera/sdram_gen5.c | 143 ++++++++++++++++-- drivers/ddr/altera/sequencer.c | 9 +- drivers/ddr/altera/sequencer.h | 35 +++++ 7 files changed, 184 insertions(+), 42 deletions(-) diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index ec1966480f..51a6a51b53 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -791,9 +791,9 @@ reg = <0xfffec000 0x100>; }; - sdr: sdr@ffc25000 { + sdr: sdr@ffc20000 { compatible = "altr,sdr-ctl", "syscon"; - reg = <0xffc25000 0x1000>; + reg = <0xffc20000 0x6000>; resets = <&rst SDR_RESET>; }; diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h index a238d5d17f..c41208591a 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -7,10 +7,6 @@ #ifndef __ASSEMBLY__ -unsigned long sdram_calculate_size(void); -int sdram_mmr_init_full(unsigned int sdr_phy_reg); -int sdram_calibration_full(void); - const struct socfpga_sdram_config *socfpga_get_sdram_config(void); void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 142b60f887..c5399bb697 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -21,6 +21,7 @@ #include <debug_uart.h> #include <fdtdec.h> #include <watchdog.h> +#include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -123,9 +124,9 @@ static void socfpga_pl310_clear(void) void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); - unsigned long sdram_size; unsigned long reg; int ret; + struct udevice *dev; /* * First C code to run. Clear fake OCRAM ECC first as SBE @@ -156,7 +157,6 @@ void board_init_f(ulong dummy) socfpga_bridges_reset(1); } - socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); @@ -200,27 +200,16 @@ void board_init_f(ulong dummy) hang(); } + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) + debug("Reset init failed: %d\n", ret); + /* enable console uart printing */ preloader_console_init(); - if (sdram_mmr_init_full(0xffffffff) != 0) { - puts("SDRAM init failed.\n"); - hang(); - } - - debug("SDRAM: Calibrating PHY\n"); - /* SDRAM calibration */ - if (sdram_calibration_full() == 0) { - puts("SDRAM calibration failed.\n"); - hang(); - } - - sdram_size = sdram_calculate_size(); - debug("SDRAM: %ld MiB\n", sdram_size >> 20); - - /* Sanity check ensure correct SDRAM size specified */ - if (get_ram_size(0, sdram_size) != sdram_size) { - puts("SDRAM size check failed!\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); hang(); } diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 2b28a97f6e..8f60b56eb8 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,5 +1,7 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select RAM if TARGET_SOCFPGA_GEN5 + select SPL_RAM if TARGET_SOCFPGA_GEN5 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 821060459c..fcd89b619d 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -3,14 +3,30 @@ * Copyright Altera Corporation (C) 2014-2015 */ #include <common.h> +#include <dm.h> #include <errno.h> #include <div64.h> +#include <ram.h> +#include <reset.h> #include <watchdog.h> #include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> #include <asm/arch/sdram.h> #include <asm/arch/system_manager.h> #include <asm/io.h> +#include "sequencer.h" + +#ifdef CONFIG_SPL_BUILD + +struct altera_gen5_sdram_priv { + struct ram_info info; +}; + +struct altera_gen5_sdram_platdata { + struct socfpga_sdr *sdr; +}; + struct sdram_prot_rule { u32 sdram_start; /* SDRAM start address */ u32 sdram_end; /* SDRAM end address */ @@ -26,8 +42,8 @@ struct sdram_prot_rule { static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl); /** * get_errata_rows() - Up the number of DRAM rows to cover entire address space @@ -104,7 +120,8 @@ static int get_errata_rows(const struct socfpga_sdram_config *cfg) } /* SDRAM protection rules vary from 0-19, a total of 20 rules. */ -static void sdram_set_rule(struct sdram_prot_rule *prule) +static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 lo_addr_bits; u32 hi_addr_bits; @@ -141,7 +158,8 @@ static void sdram_set_rule(struct sdram_prot_rule *prule) writel(0, &sdr_ctrl->prot_rule_rdwr); } -static void sdram_get_rule(struct sdram_prot_rule *prule) +static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl, + struct sdram_prot_rule *prule) { u32 addr; u32 id; @@ -172,7 +190,8 @@ static void sdram_get_rule(struct sdram_prot_rule *prule) } static void -sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) +sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl, + const u32 sdram_start, const u32 sdram_end) { struct sdram_prot_rule rule; int rules; @@ -185,7 +204,7 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule); } /* new rule: accept SDRAM */ @@ -200,13 +219,13 @@ sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) rule.rule = 0; /* set new rule */ - sdram_set_rule(&rule); + sdram_set_rule(sdr_ctrl, &rule); /* default rule: reject everything */ writel(0x3ff, &sdr_ctrl->protport_default); } -static void sdram_dump_protection_config(void) +static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl) { struct sdram_prot_rule rule; int rules; @@ -216,7 +235,7 @@ static void sdram_dump_protection_config(void) for (rules = 0; rules < 20; rules++) { rule.rule = rules; - sdram_get_rule(&rule); + sdram_get_rule(sdr_ctrl, &rule); debug("Rule %d, rules ...\n", rules); debug(" sdram start %x\n", rule.sdram_start); debug(" sdram end %x\n", rule.sdram_end); @@ -322,7 +341,8 @@ static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) * * This function loads the register values into the SDRAM controller block. */ -static void sdr_load_regs(const struct socfpga_sdram_config *cfg) +static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl, + const struct socfpga_sdram_config *cfg) { const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); const u32 dram_addrw = sdr_get_addr_rw(cfg); @@ -426,7 +446,8 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg) * * Initialize the SDRAM MMR. */ -int sdram_mmr_init_full(unsigned int sdr_phy_reg) +int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl, + unsigned int sdr_phy_reg) { const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); const unsigned int rows = @@ -436,7 +457,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) writel(rows, &sysmgr_regs->iswgrp_handoff[4]); - sdr_load_regs(cfg); + sdr_load_regs(sdr_ctrl, cfg); /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); @@ -459,9 +480,10 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); - sdram_set_protection_config(0, sdram_calculate_size() - 1); + sdram_set_protection_config(sdr_ctrl, 0, + sdram_calculate_size(sdr_ctrl) - 1); - sdram_dump_protection_config(); + sdram_dump_protection_config(sdr_ctrl); return 0; } @@ -472,7 +494,7 @@ int sdram_mmr_init_full(unsigned int sdr_phy_reg) * Calculate SDRAM device size based on SDRAM controller parameters. * Size is specified in bytes. */ -unsigned long sdram_calculate_size(void) +static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) { unsigned long temp; unsigned long row, bank, col, cs, width; @@ -534,3 +556,94 @@ unsigned long sdram_calculate_size(void) return temp; } + +static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_gen5_sdram_platdata *plat = dev->platdata; + + plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0); + if (!plat->sdr) + return -ENODEV; + + return 0; +} + +static int altera_gen5_sdram_probe(struct udevice *dev) +{ + int ret; + unsigned long sdram_size; + struct altera_gen5_sdram_platdata *plat = dev->platdata; + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl; + struct reset_ctl_bulk resets; + + ret = reset_get_bulk(dev, &resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + reset_deassert_bulk(&resets); + + if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) { + puts("SDRAM init failed.\n"); + goto failed; + } + + debug("SDRAM: Calibrating PHY\n"); + /* SDRAM calibration */ + if (sdram_calibration_full(plat->sdr) == 0) { + puts("SDRAM calibration failed.\n"); + goto failed; + } + + sdram_size = sdram_calculate_size(sdr_ctrl); + debug("SDRAM: %ld MiB\n", sdram_size >> 20); + + /* Sanity check ensure correct SDRAM size specified */ + if (get_ram_size(0, sdram_size) != sdram_size) { + puts("SDRAM size check failed!\n"); + goto failed; + } + + priv->info.base = 0; + priv->info.size = sdram_size; + + return 0; + +failed: + reset_release_bulk(&resets); + return -ENODEV; +} + +static int altera_gen5_sdram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct altera_gen5_sdram_priv *priv = dev_get_priv(dev); + + info->base = priv->info.base; + info->size = priv->info.size; + + return 0; +} + +static struct ram_ops altera_gen5_sdram_ops = { + .get_info = altera_gen5_sdram_get_info, +}; + +static const struct udevice_id altera_gen5_sdram_ids[] = { + { .compatible = "altr,sdr-ctl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(altera_gen5_sdram) = { + .name = "altr_sdr_ctl", + .id = UCLASS_RAM, + .of_match = altera_gen5_sdram_ids, + .ops = &altera_gen5_sdram_ops, + .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata), + .probe = altera_gen5_sdram_probe, + .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv), +}; + +#endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 5e7a943b68..0e4526288e 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3705,12 +3705,19 @@ static void initialize_tracking(void) &sdr_reg_file->trk_rfsh); } -int sdram_calibration_full(void) +int sdram_calibration_full(struct socfpga_sdr *sdr) { struct param_type my_param; struct gbl_type my_gbl; u32 pass; + /* + * For size reasons, this file uses hard coded addresses. + * Check if we are called with the correct address. + */ + if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) + return -ENODEV; + memset(&my_param, 0, sizeof(my_param)); memset(&my_gbl, 0, sizeof(my_gbl)); diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index a5760b03a5..d7f6935201 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -223,4 +223,39 @@ struct socfpga_data_mgr { u32 mem_t_add; u32 t_rl_add; }; + +/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */ +struct socfpga_sdr { + /* SDR_PHYGRP_SCCGRP_ADDRESS */ + u8 _align1[0xe00]; + /* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */ + struct socfpga_sdr_scc_mgr sdr_scc_mgr; + u8 _align2[0x1bc]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS */ + struct socfpga_phy_mgr_cmd phy_mgr_cmd; + u8 _align3[0x2c]; + /* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */ + struct socfpga_phy_mgr_cfg phy_mgr_cfg; + u8 _align4[0xfa0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS */ + u8 rwmgr_grp[0x800]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */ + struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs; + u8 _align5[0x3f0]; + /* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */ + struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs; + u8 _align6[0x13f0]; + /* SDR_PHYGRP_DATAMGRGRP_ADDRESS */ + struct socfpga_data_mgr data_mgr; + u8 _align7[0x7f0]; + /* SDR_PHYGRP_REGFILEGRP_ADDRESS */ + struct socfpga_sdr_reg_file sdr_reg_file; + u8 _align8[0x7c8]; + /* SDR_CTRLGRP_ADDRESS */ + struct socfpga_sdr_ctrl sdr_ctrl; + u8 _align9[0xea4]; +}; + +int sdram_calibration_full(struct socfpga_sdr *sdr); + #endif /* _SEQUENCER_H_ */ -- 2.17.1

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[U-Boot] [PATCH 0/2] Add Support for ADMA2 in SDHCI
by Faiz Abbas 16 Apr '19

16 Apr '19

The following patches add support for ADMA2 in SDHCI. Tested with Am65x_evm with some out of tree patches unrelated to MMC. Faiz Abbas (2): mmc: sdhci: Move DMA handling to prepare_dma() function mmc: sdhci: Add Support for ADMA2 drivers/mmc/Kconfig | 14 ++++ drivers/mmc/sdhci.c | 188 +++++++++++++++++++++++++++++++++----------- include/sdhci.h | 44 +++++++++++ 3 files changed, 202 insertions(+), 44 deletions(-) -- 2.19.2

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[U-Boot] [PATCH] sun8i: h3: NanoPi M1 Plus: Add emac configuration
by Emmanuel Vadot 16 Apr '19

16 Apr '19

NanoPi M1 plus have a 10/100/1000M ethernet with external phy. Phy power is controlled by PD6. Add the required configuration for it. Signed-off-by: Emmanuel Vadot <manu(a)freebsd.org> --- configs/nanopi_m1_plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index b83cdf2e1c..ac5497ac2f 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -13,6 +13,8 @@ CONFIG_NR_DRAM_BANKS=1 # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" +CONFIG_MACPWR="PD6" +CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.21.0

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[U-Boot] [PATCH 0/7] sunxi: a20/r40: Migrate DM_MMC and DM_SCSI
by Jagan Teki 16 Apr '19

16 Apr '19

This would Migrate DM_MMC, DM_SCSI for A20 and R40 platforms. Note: - a20-wits-pro-a20-dkt change would need to send Linux first - BPI-M2-Berry would break, but will import Linux dts once approved. Andre Przywara (1): sunxi: update SATA driver to always use DM_SCSI Jagan Teki (6): arm: allwinner: r40: Sync R40 dts(i) files from Linux 5.1-rc2 arm: allwinner: dts: a20: Sync A20 dts(i) files from Linux 5.1-rc2 board: sunxi: Add R40 sata compatible ARM: dts: a20-m5: Enable AHCI ARM: dts: a20-wits-pro-a20-dkt: Enable AHCI arm: sunxi: Enable DM_MMC and DM_SCSI arch/arm/Kconfig | 2 + arch/arm/dts/sun7i-a20-ainol-aw1.dts | 2 +- arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 46 +-- arch/arm/dts/sun7i-a20-bananapi.dts | 49 +-- arch/arm/dts/sun7i-a20-bananapro.dts | 65 +--- arch/arm/dts/sun7i-a20-cubieboard2.dts | 21 +- arch/arm/dts/sun7i-a20-cubietruck.dts | 83 ++-- arch/arm/dts/sun7i-a20-hummingbird.dts | 60 +-- arch/arm/dts/sun7i-a20-i12-tvbox.dts | 47 +-- arch/arm/dts/sun7i-a20-icnova-swac.dts | 10 +- arch/arm/dts/sun7i-a20-itead-ibox.dts | 10 +- arch/arm/dts/sun7i-a20-lamobo-r1.dts | 48 +-- arch/arm/dts/sun7i-a20-m3.dts | 21 +- arch/arm/dts/sun7i-a20-m5.dts | 8 +- arch/arm/dts/sun7i-a20-mk808c.dts | 26 +- .../arm/dts/sun7i-a20-olimex-som-evb-emmc.dts | 35 ++ arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 68 +--- .../dts/sun7i-a20-olimex-som204-evb-emmc.dts | 2 - arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 36 +- arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 22 +- .../dts/sun7i-a20-olinuxino-lime2-emmc.dts | 11 - arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 34 +- .../dts/sun7i-a20-olinuxino-micro-emmc.dts | 2 - arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 54 +-- arch/arm/dts/sun7i-a20-orangepi-mini.dts | 52 +-- arch/arm/dts/sun7i-a20-orangepi.dts | 44 +-- arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 31 +- arch/arm/dts/sun7i-a20-pcduino3.dts | 39 +- arch/arm/dts/sun7i-a20-primo73.dts | 4 +- arch/arm/dts/sun7i-a20-wexler-tab7200.dts | 39 +- arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts | 27 +- .../dts/sun7i-a20-yones-toptech-bd1078.dts | 2 +- arch/arm/dts/sun7i-a20.dtsi | 209 ++++++---- arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 91 ++++- arch/arm/dts/sun8i-r40.dtsi | 364 +++++++++++++++++- arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 2 +- arch/arm/dts/sunxi-itead-core-common.dtsi | 6 +- arch/arm/mach-sunxi/Kconfig | 13 - board/sunxi/Makefile | 3 - drivers/ata/Kconfig | 8 + drivers/ata/Makefile | 1 + .../sunxi/ahci.c => drivers/ata/ahci_sunxi.c | 11 +- include/configs/sunxi-common.h | 6 - scripts/config_whitelist.txt | 1 - 44 files changed, 838 insertions(+), 877 deletions(-) create mode 100644 arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts rename board/sunxi/ahci.c => drivers/ata/ahci_sunxi.c (94%) -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [RFC] Migrating iMX LCDIF drivers to Driver Model
by Igor Opaniuk 16 Apr '19

16 Apr '19

Marek, Peng, Writing to you as you were the main contributors to U-boot mxsfb driver implementation (i.MX23/i.MX28 LCDIF driver). I was about to start working on it's migration to DM (currently mxsfb is being used on our SoM Colibri iMX7S/D), but found it a bit out-dated (no one introduced any changes for the last 5 years) and maybe it's really does make a sense to fetch and port the latest one from the Linux mainline (in a sake of avoiding divergence in implementation and continue fetching future updates from the Linux kernel). So there are 2 questions spinning in my mind: 1) In case if you are maybe aware, if there were any intentions to do this migration before? (maybe someone asked similar questions or even send some patches, but didn't manage to upstream that; or did similar stuff in some downstream U-boot forks, whatever). Unfortunately I can't any information regarding this in U-boot ML archives . 2) Will it be OK if I introduce a brand new mxsfb driver (ported from Linux), which will be used only when U-boot is built with CONFIG_DM_VIDEO enabled? Existing mxsfb will be left as it is, so I can be removed easily when full migration to DM is done for all boards that are using this driver. Simon, Could you also provide you feedback for 2 (if introducing a brand new dm-enabled driver is a good idea), thanks! Thanks in advance for you comments/suggestions! -- Best regards - Freundliche Grüsse - Meilleures salutations Senior Development Engineer, Igor Opaniuk Toradex AG Altsagenstrasse 5 | 6048 Horw/Luzern | Switzerland | T: +41 41 500 48 00 (main line)

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[U-Boot] [PATCH] mtd: spi: Improve data write functionality
by Rajat Srivastava 16 Apr '19

16 Apr '19

Incorporate write enable and status check in the write data function itself. Formerly, Write data function used to break the data to be written into smaller chunks and used to send the smaller chunks without write enable or status check for every iteration. Signed-off-by: Rajat Srivastava <rajat.srivastava(a)nxp.com> --- While writing any data to a SPI flash every write transaction shall be preceded by a WRITE_ENABLE command and shall be followed by a READ_STATUS process (to check if the flash is not busy). This sequence can be roughly represented as: 1. write_enable //issue write enable command 2. execute_write_operation //write data to flash or register 3. spi_nor_wait_till_ready //read status of flash The current framework has two types of write operation: 1. write to register (nor->write_reg) 2. write data to flash memory (nor->write) There seems to be an issue in writing data to flash memory for which the framework uses spi_nor_write_data() function. Before every call to spi_nor_write_data() function the framework sends a WRITE_ENABLE command and later checks if the flash is busy. However, the spi_nor_write_data() function which executes the data write to flash, breaks the data into smaller chunks. For all of these small transactions there is only a single WRITE_ENABLE command issued and a single check made for status, which breaks the write operation. Only the first chunk of the whole data is successfully written on to the flash. This patch fixes the bug making the spi_nor_write_data() function issue WRITE_ENABLE command and status checks with every write transactions. Without this patch write in fsl_qspi.c driver is broken. drivers/mtd/spi/spi-nor-core.c | 30 +++++++++--------------------- 1 file changed, 9 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index c4e2f6a08f..757163369b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -23,6 +23,9 @@ #include "sf_internal.h" +static int spi_nor_wait_till_ready(struct spi_nor *nor); +static int write_enable(struct spi_nor *nor); + /* Define max times to check status register before we give up. */ /* @@ -128,6 +131,8 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, op.addr.nbytes = 0; while (remaining) { + write_enable(nor); + op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; ret = spi_mem_adjust_op_size(nor->spi, &op); if (ret) @@ -137,6 +142,10 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, if (ret) return ret; + ret = spi_nor_wait_till_ready(nor); + if (ret) + return ret; + op.addr.val += op.data.nbytes; remaining -= op.data.nbytes; op.data.buf.out += op.data.nbytes; @@ -961,14 +970,10 @@ static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, for (actual = 0; actual < len; actual++) { nor->program_opcode = SPINOR_OP_BP; - write_enable(nor); /* write one byte. */ ret = nor->write(nor, to, 1, buf + actual); if (ret < 0) goto sst_write_err; - ret = spi_nor_wait_till_ready(nor); - if (ret) - goto sst_write_err; to++; } @@ -989,8 +994,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, if (spi->mode & SPI_TX_BYTE) return sst_write_byteprogram(nor, to, len, retlen, buf); - write_enable(nor); - nor->sst_write_second = false; actual = to % 2; @@ -1002,9 +1005,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, ret = nor->write(nor, to, 1, buf); if (ret < 0) goto sst_write_err; - ret = spi_nor_wait_till_ready(nor); - if (ret) - goto sst_write_err; } to += actual; @@ -1016,9 +1016,6 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, ret = nor->write(nor, to, 2, buf + actual); if (ret < 0) goto sst_write_err; - ret = spi_nor_wait_till_ready(nor); - if (ret) - goto sst_write_err; to += 2; nor->sst_write_second = true; } @@ -1031,15 +1028,10 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, /* Write out trailing byte if it exists. */ if (actual != len) { - write_enable(nor); - nor->program_opcode = SPINOR_OP_BP; ret = nor->write(nor, to, 1, buf + actual); if (ret < 0) goto sst_write_err; - ret = spi_nor_wait_till_ready(nor); - if (ret) - goto sst_write_err; write_disable(nor); actual += 1; } @@ -1090,15 +1082,11 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, if (ret < 0) return ret; #endif - write_enable(nor); ret = nor->write(nor, addr, page_remain, buf + i); if (ret < 0) goto write_err; written = ret; - ret = spi_nor_wait_till_ready(nor); - if (ret) - goto write_err; *retlen += written; i += written; if (written != page_remain) { -- 2.17.1

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[U-Boot] [PATCH v2] sunxi: Add support for Olimex A64-Teres-I board
by Jonas Smedegaard 16 Apr '19

16 Apr '19

Olimex Teres-I is a laptop DIY kit, and A64-Teres-I is its mainboard. https://linux-sunxi.org/Olimex_Teres-A64 This patch enables support for the A64-Teres-I board to u-boot, including enabling screen backlight (lacking from Linux device-tree). sun50i-a64-teres-i.dts is copied verbatim from linux v5.0 (d91ebb9). Cosmetic warnings regarding whitespace and placement of SPDX notice for above file was ignored. config and .dtsi file are adapted from pinebook files. Tested-by: Jonas Smedegaard <dr(a)jones.dk> Signed-off-by: Jonas Smedegaard <dr(a)jones.dk> --- Changes for v2: * List Icenowy and Jonas as MAINTAINERS * Add commit hash in linux tree for sun50i-a64-teres-i.dts * Drop superfluous and unsupported Author: tag --- MAINTAINERS | 8 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi | 41 +++ arch/arm/dts/sun50i-a64-teres-i.dts | 270 ++++++++++++++++++++ configs/teres_i_defconfig | 21 ++ 5 files changed, 342 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts create mode 100644 configs/teres_i_defconfig diff --git a/MAINTAINERS b/MAINTAINERS index c77abba1e5..d6ba87a0ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -319,6 +319,14 @@ F: arch/arm/include/asm/arch-sunxi/ F: arch/arm/mach-sunxi/ F: board/sunxi/ +ARM SUNXI OLIMEX TERES-I +M: Jonas Smedegaard <dr(a)jones.dk> +M: Icenowy Zheng <icenowy(a)aosc.io> +S: Maintained +T: git https://salsa.debian.org/js/u-boot +F: arch/arm/dts/sun50i-a64-teres-i* +F: configs/teres_i_defconfig + ARM TEGRA M: Tom Warren <twarren(a)nvidia.com> S: Maintained diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8167cdb4e8..a12ed81f49 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -483,7 +483,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb \ sun50i-a64-pinebook.dtb \ - sun50i-a64-sopine-baseboard.dtb + sun50i-a64-sopine-baseboard.dtb \ + sun50i-a64-teres-i.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb \ diff --git a/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi new file mode 100644 index 0000000000..1a64b7d09c --- /dev/null +++ b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Vasily Khoruzhick <anarsoul(a)gmail.com> + * + */ + +#include "sunxi-u-boot.dtsi" + +/ { + vdd_bl: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "bl-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 0>; + brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; + default-brightness-level = <2>; + enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + power-supply = <&vdd_bl>; + }; +}; + +/* The ANX6345 eDP-bridge is on i2c */ +&i2c0 { + anx6345: edp-bridge@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ + status = "okay"; + }; +}; + +&pwm { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts new file mode 100644 index 0000000000..c455b24dd0 --- /dev/null +++ b/arch/arm/dts/sun50i-a64-teres-i.dts @@ -0,0 +1,270 @@ +/* + * Copyright (C) Harald Geyer <harald(a)ccbib.org> + * based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki(a)openedev.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; + +#include "sun50i-a64.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Olimex A64 Teres-I"; + compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + + framebuffer-lcd { + eDP25-supply = <&reg_dldo2>; + eDP12-supply = <&reg_dldo3>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid-switch { + label = "Lid Switch"; + gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + capslock { + label = "teres-i:green:capslock"; + gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ + }; + + numlock { + label = "teres-i:green:numlock"; + gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ + }; + }; + + reg_usb1_vbus: usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + status = "okay"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; +}; + +&ehci1 { + status = "okay"; +}; + + +/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline) + * driver for this chip at the moment, the bootloader initializes it. + * However it can be accessed with the i2c-dev driver from user space. + */ +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&reg_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&reg_aldo2>; + vqmmc-supply = <&reg_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: wifi@1 { + reg = <1>; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&reg_dcdc1>; + vqmmc-supply = <&reg_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp803: pmic@3a3 { + compatible = "x-powers,axp803"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +#include "axp803.dtsi" + +&reg_aldo1 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; + +&reg_aldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; +}; + +&reg_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-pll-avcc"; +}; + +&reg_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +&reg_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpux"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +&reg_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-ddr3"; +}; + +&reg_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +&reg_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-hdmi"; +}; + +&reg_dldo2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pd"; +}; + +&reg_dldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-edp"; +}; + +&reg_dldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +&reg_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "cpvdd"; +}; + +&reg_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dvdd-csi"; +}; + +&reg_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-1v2-hsic"; +}; + +/* + * The A64 chip cannot work without this regulator off, although + * it seems to be only driving the AR100 core. + * Maybe we don't still know well about CPUs domain. + */ +&reg_fldo2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +&reg_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_hdmi { + vcc-hdmi-supply = <&reg_dldo1>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <&reg_usb1_vbus>; + status = "okay"; +}; diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig new file mode 100644 index 0000000000..939dc24408 --- /dev/null +++ b/configs/teres_i_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=3881949 +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_I2C0_ENABLE=y +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-teres-i" +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_SUNXI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +# CONFIG_USB_GADGET is not set +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y -- 2.20.1

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