April 2019 - U-Boot

[U-Boot] [PATCH] sf: Add support for Macronix mx25u12835f
by Vladimir Vid 12 Jul '19

12 Jul '19

Add ID for Macronix mx25u12835f flash. Signed-off-by: Vladimir Vid <vladimir.vid(a)sartura.hr> --- drivers/mtd/spi/spi_flash_ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index ad0a0c8150..4876007ef6 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -89,6 +89,7 @@ const struct spi_flash_info spi_flash_ids[] = { {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, {"mx25l1633e", INFO(0xc22415, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, {"mx25u6435f", INFO(0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {"mx25u12835f", INFO(0xc22538, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, -- 2.19.0

2 2

[U-Boot] [PATCH v3 0/4] Add Cadence PCIe endpoint driver with new uclass
by Ramon Fried 12 Jul '19

12 Jul '19

This patchset adds support for new uclass, UCLASS_PCI_EP allowing new set of PCI endpoint drivers. Included in the patch is also a driver for Cadence PCIe endpoint. Changes in V2: - Removed "pci.h: add missing maskbit" as it was already merged by Simon. - Added PCI endpoint sandbox driver - Added testing for sandbox driver - Addressed issues raised by Simon in UCLASS_PCI_EP class implementation Changes in v3: - Added function to read bar config - Fixed a bug in set MSI implementation (missing -1) - Elaborate a bit more in comments - Added MAINTAINER entry for PCI Endpoint - Added more description to commit message and kmsg - Removed some unused functionality that can't be tested. - Removed entries from sandbox config and added implies and select to arch/Kconfig sandbox entry. - Added more testing of sandbox driver Ramon Fried (4): drivers: pci_ep: Introduce UCLASS_PCI_EP uclass pci_ep: add Cadence PCIe endpoint driver pci_ep: add pci endpoint sandbox driver test: pci_ep: add basic pci_ep tests MAINTAINERS | 6 + arch/Kconfig | 2 + arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/test.h | 8 + .../pci_endpoint/cdns,cdns-pcie-ep.txt | 18 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/pci_endpoint/Kconfig | 34 ++ drivers/pci_endpoint/Makefile | 8 + drivers/pci_endpoint/pci_ep-uclass.c | 211 +++++++++ drivers/pci_endpoint/pcie-cadence-ep.c | 177 ++++++++ drivers/pci_endpoint/pcie-cadence.h | 309 +++++++++++++ drivers/pci_endpoint/sandbox-pci_ep.c | 182 ++++++++ include/dm/uclass-id.h | 1 + include/pci_ep.h | 414 ++++++++++++++++++ test/dm/Makefile | 1 + test/dm/pci_ep.c | 64 +++ 17 files changed, 1442 insertions(+) create mode 100644 doc/device-tree-bindings/pci_endpoint/cdns,cdns-pcie-ep.txt create mode 100644 drivers/pci_endpoint/Kconfig create mode 100644 drivers/pci_endpoint/Makefile create mode 100644 drivers/pci_endpoint/pci_ep-uclass.c create mode 100644 drivers/pci_endpoint/pcie-cadence-ep.c create mode 100644 drivers/pci_endpoint/pcie-cadence.h create mode 100644 drivers/pci_endpoint/sandbox-pci_ep.c create mode 100644 include/pci_ep.h create mode 100644 test/dm/pci_ep.c -- 2.21.0

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[U-Boot] [PATCH] treewide: Replace CONFIG_DM_SPI_FLASH with CONFIG_IS_ENABLED(DM_SPI_FLASH)
by Marek Vasut 01 Jul '19

01 Jul '19

Perform the replacement to allow platforms use non-DM SPI flash access in SPL/TPL. This is thus far needed on platforms with size constraints. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Jagan Teki <jagan(a)openedev.com> Cc: Vignesh R <vigneshr(a)ti.com> --- cmd/sf.c | 4 ++-- drivers/mtd/spi/sf_probe.c | 2 +- drivers/net/fm/fm.c | 4 ++-- env/sf.c | 2 +- include/spi_flash.h | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/cmd/sf.c b/cmd/sf.c index 738ef0e46d..7e92a43b2c 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -84,7 +84,7 @@ static int do_spi_flash_probe(int argc, char * const argv[]) unsigned int speed = CONFIG_SF_DEFAULT_SPEED; unsigned int mode = CONFIG_SF_DEFAULT_MODE; char *endp; -#ifdef CONFIG_DM_SPI_FLASH +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) struct udevice *new, *bus_dev; int ret; /* In DM mode defaults will be taken from DT */ @@ -119,7 +119,7 @@ static int do_spi_flash_probe(int argc, char * const argv[]) return -1; } -#ifdef CONFIG_DM_SPI_FLASH +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) /* Remove the old device, otherwise probe will just be a nop */ ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new); if (!ret) { diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 7f1378f494..4282d48f26 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -53,7 +53,7 @@ err_read_id: return ret; } -#ifndef CONFIG_DM_SPI_FLASH +#if !CONFIG_IS_ENABLED(DM_SPI_FLASH) struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs, unsigned int max_hz, unsigned int spi_mode) { diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index e19d7777dc..6a5c9bbc9d 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -377,7 +377,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); int ret = 0; -#ifdef CONFIG_DM_SPI_FLASH +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) struct udevice *new; /* speed and mode will be read from DT */ @@ -464,7 +464,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); int ret = 0; -#ifdef CONFIG_DM_SPI_FLASH +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) struct udevice *new; /* speed and mode will be read from DT */ diff --git a/env/sf.c b/env/sf.c index b3dec82c35..ee639b90fc 100644 --- a/env/sf.c +++ b/env/sf.c @@ -52,7 +52,7 @@ static struct spi_flash *env_flash; static int setup_flash_device(void) { -#ifdef CONFIG_DM_SPI_FLASH +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) struct udevice *new; int ret; diff --git a/include/spi_flash.h b/include/spi_flash.h index 7f691e8559..09f3896fb9 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -51,7 +51,7 @@ struct dm_spi_flash_ops { /* Access the serial operations for a device */ #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops) -#ifdef CONFIG_DM_SPI_FLASH +#if CONFIG_IS_ENABLED(DM_SPI_FLASH) /** * spi_flash_read_dm() - Read data from SPI flash * -- 2.19.2

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[U-Boot] [PATCH] mmc: Do not poll using CMD13 when changing timing
by Marek Vasut 26 Jun '19

26 Jun '19

When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy, do not poll for the completion status using CMD13, but rather wait 50mS. Once the card receives the CMD6 and starts executing it, the bus is in undefined state until both the card finishes executing the command and until the controller switches the bus to matching timing configuration. During this time, it is not possible to transport any commands or data across the bus, which includes the CMD13. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- NOTE: Linux does the same thing. --- drivers/mmc/mmc.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c7730c9233..ababacf65a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -720,7 +720,8 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) return err; } -int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, + bool send_status) { struct mmc_cmd cmd; int timeout = 1000; @@ -736,19 +737,29 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) while (retries > 0) { ret = mmc_send_cmd(mmc, &cmd, NULL); - /* Waiting for the ready status */ - if (!ret) { - ret = mmc_send_status(mmc, timeout); - return ret; + if (ret) { + retries--; + continue; + } + + if (!send_status) { + mdelay(50); + return 0; } - retries--; + /* Waiting for the ready status */ + return mmc_send_status(mmc, timeout); } return ret; } +int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +{ + return __mmc_switch(mmc, set, index, value, true); +} + #if !CONFIG_IS_ENABLED(MMC_TINY) static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, bool hsdowngrade) @@ -780,8 +791,9 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, default: return -EINVAL; } - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, - speed_bits); + + err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, + speed_bits, !hsdowngrade); if (err) return err; -- 2.19.2

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[U-Boot] [PATCH v4 0/4] add command env erase
by Frank Wunderlich 24 Jun '19

24 Jun '19

sometimes it is needed to erase the non-volatile environment e.g. for boot-up with builtin-environment or after resizing env this series add basic functionality for erasing environment from storage as a first storage-driver mmc is introduced, other needs to be added later changes since v3: - fixes - Kconfig-option as suggested by Simon Goldschmidt - including CONFIG_ENV_OFFSET_REDUND (4/4 is RFC) Frank Wunderlich (4): env: register erase command env: mmc: add erase-function env: add option to use redundant offset [RFC] env: call env_erase twice if CONFIG_ENV_OFFSET_REDUND is set cmd/Kconfig | 8 ++++++++ cmd/nvedit.c | 26 ++++++++++++++++++++++++++ env/env.c | 30 ++++++++++++++++++++++++++++++ env/mmc.c | 36 ++++++++++++++++++++++++++++++++++++ include/environment.h | 17 +++++++++++++++++ 5 files changed, 117 insertions(+) -- 2.17.1

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[U-Boot] [PATCH] drivers: serial: lpuart: Enable Little Endian Support
by Vabhav Sharma 24 Jun '19

24 Jun '19

By default LPUART driver with compatible string "fsl,ls1021a-lpuart" support big-endian mode.On NXP SoC like LS1028A LPUART IP is little-endian,Added support to Fetch LPUART IP Endianness from lpuart device-tree node. Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> --- drivers/serial/serial_lpuart.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index a357b00..57dd4a7 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright 2019 NXP * Copyright 2013 Freescale Semiconductor, Inc. */ @@ -502,6 +503,9 @@ static int lpuart_serial_ofdata_to_platdata(struct udevice *dev) plat->reg = (void *)addr; plat->flags = dev_get_driver_data(dev); + if (fdtdec_get_bool(blob, node, "little-endian")) + plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG; + if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) plat->devtype = DEV_LS1021A; else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) -- 2.7.4

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[U-Boot] [PATCH v3 00/11] clk: Port Linux common clock framework [CCF] to U-boot (tag: 5.0-rc3)
by Lukasz Majewski 22 Jun '19

22 Jun '19

This patch series brings the files from Linux kernel to provide clocks support as it is used on the Linux kernel with common clock framework [CCF] setup. This series also fixes several problems with current clocks and provides sandbox tests for functions addded to clk-uclass.c file. Design decisions/issues: ========================= - U-boot's DM for clk differs from Linux CCF. The most notably difference is the lack of support for hierarchical clocks and "clock as a manager driver" (single clock DTS node acts as a starting point for all other clocks). - The clk_get_rate() now caches the previously read data (no need for recursive access. - On purpose the "manager" clk driver (clk-imx6q.c) is not using large table to store pointers to clocks - e.g. clk[IMX6QDL_CLK_USDHC2_SEL] = .... Instead we use udevice's linked list for the same class (UCLASS_CLK). The rationale - when porting the code as is from Linux, one would need ~1KiB of RAM to store it. This is way too much if we do plan to use this driver in SPL. - The "central" structure of this patch series is struct udevice and its driver_data field contains the struct clk pointer (to the originally created one). - Up till now U-boot's driver model's CLK operates on udevice (main access to clock is by udevice ops) In the CCF the access to struct clk (comprising pointer to *dev) is possible via dev_get_driver_data() Storing back pointer (from udevice to struct clk) as driver_data is a convention for CCF. - I could use *private_alloc_size to allocate driver's 'private" structures (dev->priv) for e.g. divider (struct clk_divider *divider) for IMX6Q clock, but this would change the original structure of the CCF code. The question is if it would be better to use private_alloc_size (and dev->private) or stay with driver_data. The former requires some rewritting in CCF original code (to remove (c)malloc, etc), but comply with u-boot DM. The latter allows re-using the CCF code as is, but introduces some convention special for CCF (I'm not sure thought if dev->priv is NOT another convention as well). - I've added the clk_get_parent(), which reads parent's dev->driver_data to provide parent's struct clk pointer. This seems the easiest way to get child/parent relationship for struct clk in U-boot's udevice based clocks. - For tests I had to "emulate" CCF code structure to test functionality of clk_get_parent_rate() and clk_get_by_id(). Those functions will not work properly with "standard" (i.e. non CCF) clock setup(with not set dev->driver_data to struct clk). Repository: https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3 Changes in v3: - New patch - The rate information is now cached into struct clk field - The clk_get_parent() is used to get pointer to the parent struct clk - Replace -ENODEV with -ENOENT - Use **clkp instead of **c - New patch - New patch Lukasz Majewski (11): dm: Fix documentation entry as there is no UCLASS_CLOCK uclass cmd: Do not show frequency for clocks which .get_rate() return error clk: Remove clock ID check in .get_rate() of clk_fixed_* clk: Extend struct clk to provide information regarding clock rate clk: Provide struct clk for fixed rate clock (clk_fixed_rate.c) dm: clk: Define clk_get_parent() for clk operations dm: clk: Define clk_get_parent_rate() for clk operations dm: clk: Define clk_get_by_id() for clk operations clk: test: Provide unit test for clk_get_by_id() method clk: test: Provide unit test for clk_get_parent_rate() method clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: 5.0-rc3) arch/sandbox/include/asm/clk.h | 16 ++++ cmd/clk.c | 5 +- drivers/clk/Kconfig | 14 ++++ drivers/clk/Makefile | 2 + drivers/clk/clk-divider.c | 148 ++++++++++++++++++++++++++++++++++ drivers/clk/clk-fixed-factor.c | 87 ++++++++++++++++++++ drivers/clk/clk-mux.c | 164 +++++++++++++++++++++++++++++++++++++ drivers/clk/clk-uclass.c | 59 ++++++++++++++ drivers/clk/clk.c | 56 +++++++++++++ drivers/clk/clk_fixed_factor.c | 3 - drivers/clk/clk_fixed_rate.c | 8 +- drivers/clk/clk_sandbox_test.c | 49 +++++++++++ drivers/clk/imx/Kconfig | 9 +++ drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-gate2.c | 113 ++++++++++++++++++++++++++ drivers/clk/imx/clk-imx6q.c | 179 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-pfd.c | 91 +++++++++++++++++++++ drivers/clk/imx/clk-pllv3.c | 83 +++++++++++++++++++ drivers/clk/imx/clk.h | 75 +++++++++++++++++ include/clk.h | 33 +++++++- include/linux/clk-provider.h | 94 ++++++++++++++++++++++ test/dm/clk.c | 4 +- 22 files changed, 1285 insertions(+), 9 deletions(-) create mode 100644 drivers/clk/clk-divider.c create mode 100644 drivers/clk/clk-fixed-factor.c create mode 100644 drivers/clk/clk-mux.c create mode 100644 drivers/clk/clk.c create mode 100644 drivers/clk/imx/clk-gate2.c create mode 100644 drivers/clk/imx/clk-imx6q.c create mode 100644 drivers/clk/imx/clk-pfd.c create mode 100644 drivers/clk/imx/clk-pllv3.c create mode 100644 drivers/clk/imx/clk.h create mode 100644 include/linux/clk-provider.h -- 2.11.0

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[U-Boot] [PATCH] board/fsl/layerscape: Modify the aliases names
by Pankaj Bansal 19 Jun '19

19 Jun '19

when compiling dts file using DTC_FLAG='-@', the device tree compiler reports these warnings: Warning (alias_paths): /aliases: aliases property name must include only lowercase and '-' Fixed the node aliases to silence these warnings. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- board/freescale/ls1043aqds/eth.c | 33 +++++++++++++++--------------- board/freescale/ls1046aqds/eth.c | 26 +++++++++++------------ 2 files changed, 30 insertions(+), 29 deletions(-) diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 8763913e31..e1919d2988 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -161,16 +162,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { if (port == FM1_DTSEC9) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s1_p1"); + "sgmii-riser-s1-p1"); } else if (port == FM1_DTSEC2) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s2_p1"); + "sgmii-riser-s2-p1"); } else if (port == FM1_DTSEC5) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s3_p1"); + "sgmii-riser-s3-p1"); } else if (port == FM1_DTSEC6) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s4_p1"); + "sgmii-riser-s4-p1"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { @@ -191,19 +192,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p1"); + "qsgmii-s1-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p2"); + "qsgmii-s1-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p3"); + "qsgmii-s1-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p4"); + "qsgmii-s1-p4"); break; default: break; @@ -213,19 +214,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p1"); + "qsgmii-s2-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p2"); + "qsgmii-s2-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p3"); + "qsgmii-s2-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p4"); + "qsgmii-s2-p4"); break; default: break; @@ -268,16 +269,16 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); + fdt_status_okay_by_alias(fdt, "emi1-slot3"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index abe8ee95d4..1eb40677b5 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #include <common.h> @@ -161,19 +161,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { switch (port) { case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); break; case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); break; default: break; @@ -193,16 +193,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); break; default: break; @@ -246,13 +246,13 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; -- 2.17.1

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[U-Boot] [PATCH] configs: lx2160a: change env location to SPI_FLASH
by Rajat Srivastava 17 Jun '19

17 Jun '19

Change env location to SPI_FLASH. Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Rajat Srivastava <rajat.srivastava(a)nxp.com> --- configs/lx2160ardb_tfa_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 2dc49c7f5d..2a2609f80b 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- 2.17.1

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[U-Boot] [RFC] Reserve ATF memory on Marvell Armdada 3700/7K/8K
by Mark Kettenis 13 Jun '19

13 Jun '19

Currently U-Boot doesn't make any effort to reserve the memory used by ARM Trusted Firmware on these platforms. The result is that the memory is listed as available in the EFI memory map. And as soon as a loaded kernel tries to use this memory things explode. I've seen this with the OpenBSD kernel. But I totally expect a Linux kernel to suffer the same fate. I'm currently using the diff below, but it is not entirely clear to me if arch_early_init_r() is the appropriate place to do this. I'm also wondering whether the block should also be marked as reserved in the FDT using fdt_add_mem_rsv(). If the latter is required this probably needs to be done by ft_board_setup() or ft_system_setup(). The address and size of the region have been taken from Marvell's ATF fork at https://github.com/MarvellEmbeddedProcessors/atf-marvell The memory layout is defined in plat/marvell/a8k/common/include/platform_def.h where there are lots of defines and a diagram that attempt to describe the memory. It is not entirely obvious to me what part needs to be reserved. But 0x0400000-0x04200000 works. diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 3c84043a2c..895cd2852f 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -95,5 +95,11 @@ int arch_early_init_r(void) pci_init(); #endif +#ifdef CONFIG_EFI_LOADER + /* Reserve trusted SRAM section */ + efi_add_memory_map(0x04000000, 0x00200000 >> EFI_PAGE_SHIFT, + EFI_RESERVED_MEMORY_TYPE, false); +#endif + return 0; }

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